projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 7423d2d8 SR |
1 | /* |
| 2 | * Copyright 2012 Stefan Roese | |
| 3 | * Stefan Roese <sr@denx.de> | |
| 4 | * | |
| 5 | * The code contained herein is licensed under the GNU General Public | |
| 6 | * License. You may obtain a copy of the GNU General Public License | |
| 7 | * Version 2 or later at the following locations: | |
| 8 | * | |
| 9 | * http://www.opensource.org/licenses/gpl-license.html | |
| 10 | * http://www.gnu.org/copyleft/gpl.html | |
| 11 | */ | |
| 12 | ||
| 13 | /include/ "sunxi.dtsi" | |
| 14 | ||
| 15 | / { | |
| 16 | memory { | |
| 17 | reg = <0x40000000 0x80000000>; | |
| 18 | }; | |
| 874b4e45 MR |
19 | |
| 20 | soc { | |
| e10911e1 | 21 | pio: pinctrl@01c20800 { |
| 874b4e45 MR |
22 | compatible = "allwinner,sun4i-a10-pinctrl"; |
| 23 | reg = <0x01c20800 0x400>; | |
| 36386d6e | 24 | clocks = <&apb0_gates 5>; |
| e10911e1 | 25 | gpio-controller; |
| 874b4e45 MR |
26 | #address-cells = <1>; |
| 27 | #size-cells = <0>; | |
| e10911e1 | 28 | #gpio-cells = <3>; |
| 581981be MR |
29 | |
| 30 | uart0_pins_a: uart0@0 { | |
| 31 | allwinner,pins = "PB22", "PB23"; | |
| 32 | allwinner,function = "uart0"; | |
| 33 | allwinner,drive = <0>; | |
| 34 | allwinner,pull = <0>; | |
| 35 | }; | |
| 36 | ||
| 37 | uart0_pins_b: uart0@1 { | |
| 38 | allwinner,pins = "PF2", "PF4"; | |
| 39 | allwinner,function = "uart0"; | |
| 40 | allwinner,drive = <0>; | |
| 41 | allwinner,pull = <0>; | |
| 42 | }; | |
| 43 | ||
| 44 | uart1_pins_a: uart1@0 { | |
| 45 | allwinner,pins = "PA10", "PA11"; | |
| 46 | allwinner,function = "uart1"; | |
| 47 | allwinner,drive = <0>; | |
| 48 | allwinner,pull = <0>; | |
| 49 | }; | |
| 874b4e45 | 50 | }; |
| 89b3c99f MR |
51 | |
| 52 | uart0: serial@01c28000 { | |
| 53 | compatible = "snps,dw-apb-uart"; | |
| 54 | reg = <0x01c28000 0x400>; | |
| 55 | interrupts = <1>; | |
| 56 | reg-shift = <2>; | |
| 57 | reg-io-width = <4>; | |
| 9ff49ec7 | 58 | clocks = <&apb1_gates 16>; |
| 89b3c99f MR |
59 | status = "disabled"; |
| 60 | }; | |
| 76f14d0a MR |
61 | |
| 62 | uart2: serial@01c28800 { | |
| 63 | compatible = "snps,dw-apb-uart"; | |
| 64 | reg = <0x01c28800 0x400>; | |
| 65 | interrupts = <3>; | |
| 66 | reg-shift = <2>; | |
| 67 | reg-io-width = <4>; | |
| 9ff49ec7 | 68 | clocks = <&apb1_gates 18>; |
| 76f14d0a MR |
69 | status = "disabled"; |
| 70 | }; | |
| 71 | ||
| 72 | uart4: serial@01c29000 { | |
| 73 | compatible = "snps,dw-apb-uart"; | |
| 74 | reg = <0x01c29000 0x400>; | |
| 75 | interrupts = <17>; | |
| 76 | reg-shift = <2>; | |
| 77 | reg-io-width = <4>; | |
| 9ff49ec7 | 78 | clocks = <&apb1_gates 20>; |
| 76f14d0a MR |
79 | status = "disabled"; |
| 80 | }; | |
| 81 | ||
| 82 | uart5: serial@01c29400 { | |
| 83 | compatible = "snps,dw-apb-uart"; | |
| 84 | reg = <0x01c29400 0x400>; | |
| 85 | interrupts = <18>; | |
| 86 | reg-shift = <2>; | |
| 87 | reg-io-width = <4>; | |
| 9ff49ec7 | 88 | clocks = <&apb1_gates 21>; |
| 76f14d0a MR |
89 | status = "disabled"; |
| 90 | }; | |
| 91 | ||
| 92 | uart6: serial@01c29800 { | |
| 93 | compatible = "snps,dw-apb-uart"; | |
| 94 | reg = <0x01c29800 0x400>; | |
| 95 | interrupts = <19>; | |
| 96 | reg-shift = <2>; | |
| 97 | reg-io-width = <4>; | |
| 9ff49ec7 | 98 | clocks = <&apb1_gates 22>; |
| 76f14d0a MR |
99 | status = "disabled"; |
| 100 | }; | |
| 101 | ||
| 102 | uart7: serial@01c29c00 { | |
| 103 | compatible = "snps,dw-apb-uart"; | |
| 104 | reg = <0x01c29c00 0x400>; | |
| 105 | interrupts = <20>; | |
| 106 | reg-shift = <2>; | |
| 107 | reg-io-width = <4>; | |
| 9ff49ec7 | 108 | clocks = <&apb1_gates 23>; |
| 76f14d0a MR |
109 | status = "disabled"; |
| 110 | }; | |
| 874b4e45 | 111 | }; |
| 7423d2d8 | 112 | }; |