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Commit | Line | Data |
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7423d2d8 SR |
1 | /* |
2 | * Copyright 2012 Stefan Roese | |
3 | * Stefan Roese <sr@denx.de> | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
69144e3b | 13 | /include/ "skeleton.dtsi" |
7423d2d8 SR |
14 | |
15 | / { | |
69144e3b MR |
16 | interrupt-parent = <&intc>; |
17 | ||
e751cce9 EL |
18 | aliases { |
19 | ethernet0 = &emac; | |
10b302a2 MR |
20 | serial0 = &uart0; |
21 | serial1 = &uart1; | |
143b13d6 MR |
22 | serial2 = &uart2; |
23 | serial3 = &uart3; | |
24 | serial4 = &uart4; | |
25 | serial5 = &uart5; | |
26 | serial6 = &uart6; | |
27 | serial7 = &uart7; | |
e751cce9 EL |
28 | }; |
29 | ||
5790d4ee HG |
30 | chosen { |
31 | #address-cells = <1>; | |
32 | #size-cells = <1>; | |
33 | ranges; | |
34 | ||
35 | framebuffer0-hdmi { | |
36 | compatible = "simple-framebuffer"; | |
37 | clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>; | |
38 | status = "disabled"; | |
39 | }; | |
40 | }; | |
41 | ||
69144e3b | 42 | cpus { |
8b2efa89 AB |
43 | #address-cells = <1>; |
44 | #size-cells = <0>; | |
69144e3b | 45 | cpu@0 { |
14c44aa5 | 46 | device_type = "cpu"; |
69144e3b | 47 | compatible = "arm,cortex-a8"; |
14c44aa5 | 48 | reg = <0x0>; |
69144e3b MR |
49 | }; |
50 | }; | |
51 | ||
7423d2d8 SR |
52 | memory { |
53 | reg = <0x40000000 0x80000000>; | |
54 | }; | |
874b4e45 | 55 | |
69144e3b MR |
56 | clocks { |
57 | #address-cells = <1>; | |
58 | #size-cells = <1>; | |
59 | ranges; | |
60 | ||
61 | /* | |
62 | * This is a dummy clock, to be used as placeholder on | |
63 | * other mux clocks when a specific parent clock is not | |
64 | * yet implemented. It should be dropped when the driver | |
65 | * is complete. | |
66 | */ | |
67 | dummy: dummy { | |
68 | #clock-cells = <0>; | |
69 | compatible = "fixed-clock"; | |
70 | clock-frequency = <0>; | |
71 | }; | |
72 | ||
dfb12c0c | 73 | osc24M: clk@01c20050 { |
69144e3b | 74 | #clock-cells = <0>; |
bf6534a1 | 75 | compatible = "allwinner,sun4i-a10-osc-clk"; |
69144e3b | 76 | reg = <0x01c20050 0x4>; |
92fd6e06 | 77 | clock-frequency = <24000000>; |
dfb12c0c | 78 | clock-output-names = "osc24M"; |
69144e3b MR |
79 | }; |
80 | ||
dfb12c0c | 81 | osc32k: clk@0 { |
69144e3b MR |
82 | #clock-cells = <0>; |
83 | compatible = "fixed-clock"; | |
84 | clock-frequency = <32768>; | |
dfb12c0c | 85 | clock-output-names = "osc32k"; |
69144e3b MR |
86 | }; |
87 | ||
dfb12c0c | 88 | pll1: clk@01c20000 { |
69144e3b | 89 | #clock-cells = <0>; |
bf6534a1 | 90 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
69144e3b MR |
91 | reg = <0x01c20000 0x4>; |
92 | clocks = <&osc24M>; | |
dfb12c0c | 93 | clock-output-names = "pll1"; |
69144e3b MR |
94 | }; |
95 | ||
dfb12c0c | 96 | pll4: clk@01c20018 { |
ec5589f7 | 97 | #clock-cells = <0>; |
bf6534a1 | 98 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
ec5589f7 EL |
99 | reg = <0x01c20018 0x4>; |
100 | clocks = <&osc24M>; | |
dfb12c0c | 101 | clock-output-names = "pll4"; |
ec5589f7 EL |
102 | }; |
103 | ||
dfb12c0c | 104 | pll5: clk@01c20020 { |
c3e5e66b | 105 | #clock-cells = <1>; |
bf6534a1 | 106 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
c3e5e66b EL |
107 | reg = <0x01c20020 0x4>; |
108 | clocks = <&osc24M>; | |
109 | clock-output-names = "pll5_ddr", "pll5_other"; | |
110 | }; | |
111 | ||
dfb12c0c | 112 | pll6: clk@01c20028 { |
c3e5e66b | 113 | #clock-cells = <1>; |
bf6534a1 | 114 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
c3e5e66b EL |
115 | reg = <0x01c20028 0x4>; |
116 | clocks = <&osc24M>; | |
117 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
118 | }; | |
119 | ||
69144e3b MR |
120 | /* dummy is 200M */ |
121 | cpu: cpu@01c20054 { | |
122 | #clock-cells = <0>; | |
bf6534a1 | 123 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
69144e3b MR |
124 | reg = <0x01c20054 0x4>; |
125 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
dfb12c0c | 126 | clock-output-names = "cpu"; |
69144e3b MR |
127 | }; |
128 | ||
129 | axi: axi@01c20054 { | |
130 | #clock-cells = <0>; | |
bf6534a1 | 131 | compatible = "allwinner,sun4i-a10-axi-clk"; |
69144e3b MR |
132 | reg = <0x01c20054 0x4>; |
133 | clocks = <&cpu>; | |
dfb12c0c | 134 | clock-output-names = "axi"; |
69144e3b MR |
135 | }; |
136 | ||
dfb12c0c | 137 | axi_gates: clk@01c2005c { |
69144e3b | 138 | #clock-cells = <1>; |
bf6534a1 | 139 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
69144e3b MR |
140 | reg = <0x01c2005c 0x4>; |
141 | clocks = <&axi>; | |
142 | clock-output-names = "axi_dram"; | |
143 | }; | |
144 | ||
145 | ahb: ahb@01c20054 { | |
146 | #clock-cells = <0>; | |
bf6534a1 | 147 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
69144e3b MR |
148 | reg = <0x01c20054 0x4>; |
149 | clocks = <&axi>; | |
dfb12c0c | 150 | clock-output-names = "ahb"; |
69144e3b MR |
151 | }; |
152 | ||
dfb12c0c | 153 | ahb_gates: clk@01c20060 { |
69144e3b | 154 | #clock-cells = <1>; |
bf6534a1 | 155 | compatible = "allwinner,sun4i-a10-ahb-gates-clk"; |
69144e3b MR |
156 | reg = <0x01c20060 0x8>; |
157 | clocks = <&ahb>; | |
158 | clock-output-names = "ahb_usb0", "ahb_ehci0", | |
159 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", | |
160 | "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", | |
161 | "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", | |
162 | "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", | |
163 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", | |
164 | "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", | |
165 | "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", | |
166 | "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", | |
167 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
168 | "ahb_de_fe1", "ahb_mp", "ahb_mali400"; | |
169 | }; | |
170 | ||
171 | apb0: apb0@01c20054 { | |
172 | #clock-cells = <0>; | |
bf6534a1 | 173 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
69144e3b MR |
174 | reg = <0x01c20054 0x4>; |
175 | clocks = <&ahb>; | |
dfb12c0c | 176 | clock-output-names = "apb0"; |
69144e3b MR |
177 | }; |
178 | ||
dfb12c0c | 179 | apb0_gates: clk@01c20068 { |
69144e3b | 180 | #clock-cells = <1>; |
bf6534a1 | 181 | compatible = "allwinner,sun4i-a10-apb0-gates-clk"; |
69144e3b MR |
182 | reg = <0x01c20068 0x4>; |
183 | clocks = <&apb0>; | |
184 | clock-output-names = "apb0_codec", "apb0_spdif", | |
185 | "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", | |
186 | "apb0_ir1", "apb0_keypad"; | |
187 | }; | |
188 | ||
69144e3b MR |
189 | apb1_mux: apb1_mux@01c20058 { |
190 | #clock-cells = <0>; | |
bf6534a1 | 191 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
69144e3b | 192 | reg = <0x01c20058 0x4>; |
c3e5e66b | 193 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
dfb12c0c | 194 | clock-output-names = "apb1_mux"; |
69144e3b MR |
195 | }; |
196 | ||
197 | apb1: apb1@01c20058 { | |
198 | #clock-cells = <0>; | |
bf6534a1 | 199 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
69144e3b MR |
200 | reg = <0x01c20058 0x4>; |
201 | clocks = <&apb1_mux>; | |
dfb12c0c | 202 | clock-output-names = "apb1"; |
69144e3b MR |
203 | }; |
204 | ||
dfb12c0c | 205 | apb1_gates: clk@01c2006c { |
69144e3b | 206 | #clock-cells = <1>; |
bf6534a1 | 207 | compatible = "allwinner,sun4i-a10-apb1-gates-clk"; |
69144e3b MR |
208 | reg = <0x01c2006c 0x4>; |
209 | clocks = <&apb1>; | |
210 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
211 | "apb1_i2c2", "apb1_can", "apb1_scr", | |
212 | "apb1_ps20", "apb1_ps21", "apb1_uart0", | |
213 | "apb1_uart1", "apb1_uart2", "apb1_uart3", | |
214 | "apb1_uart4", "apb1_uart5", "apb1_uart6", | |
215 | "apb1_uart7"; | |
216 | }; | |
4b756ffb EL |
217 | |
218 | nand_clk: clk@01c20080 { | |
219 | #clock-cells = <0>; | |
bf6534a1 | 220 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
221 | reg = <0x01c20080 0x4>; |
222 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
223 | clock-output-names = "nand"; | |
224 | }; | |
225 | ||
226 | ms_clk: clk@01c20084 { | |
227 | #clock-cells = <0>; | |
bf6534a1 | 228 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
229 | reg = <0x01c20084 0x4>; |
230 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
231 | clock-output-names = "ms"; | |
232 | }; | |
233 | ||
234 | mmc0_clk: clk@01c20088 { | |
235 | #clock-cells = <0>; | |
bf6534a1 | 236 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
237 | reg = <0x01c20088 0x4>; |
238 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
239 | clock-output-names = "mmc0"; | |
240 | }; | |
241 | ||
242 | mmc1_clk: clk@01c2008c { | |
243 | #clock-cells = <0>; | |
bf6534a1 | 244 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
245 | reg = <0x01c2008c 0x4>; |
246 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
247 | clock-output-names = "mmc1"; | |
248 | }; | |
249 | ||
250 | mmc2_clk: clk@01c20090 { | |
251 | #clock-cells = <0>; | |
bf6534a1 | 252 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
253 | reg = <0x01c20090 0x4>; |
254 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
255 | clock-output-names = "mmc2"; | |
256 | }; | |
257 | ||
258 | mmc3_clk: clk@01c20094 { | |
259 | #clock-cells = <0>; | |
bf6534a1 | 260 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
261 | reg = <0x01c20094 0x4>; |
262 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
263 | clock-output-names = "mmc3"; | |
264 | }; | |
265 | ||
266 | ts_clk: clk@01c20098 { | |
267 | #clock-cells = <0>; | |
bf6534a1 | 268 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
269 | reg = <0x01c20098 0x4>; |
270 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
271 | clock-output-names = "ts"; | |
272 | }; | |
273 | ||
274 | ss_clk: clk@01c2009c { | |
275 | #clock-cells = <0>; | |
bf6534a1 | 276 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
277 | reg = <0x01c2009c 0x4>; |
278 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
279 | clock-output-names = "ss"; | |
280 | }; | |
281 | ||
282 | spi0_clk: clk@01c200a0 { | |
283 | #clock-cells = <0>; | |
bf6534a1 | 284 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
285 | reg = <0x01c200a0 0x4>; |
286 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
287 | clock-output-names = "spi0"; | |
288 | }; | |
289 | ||
290 | spi1_clk: clk@01c200a4 { | |
291 | #clock-cells = <0>; | |
bf6534a1 | 292 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
293 | reg = <0x01c200a4 0x4>; |
294 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
295 | clock-output-names = "spi1"; | |
296 | }; | |
297 | ||
298 | spi2_clk: clk@01c200a8 { | |
299 | #clock-cells = <0>; | |
bf6534a1 | 300 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
301 | reg = <0x01c200a8 0x4>; |
302 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
303 | clock-output-names = "spi2"; | |
304 | }; | |
305 | ||
306 | pata_clk: clk@01c200ac { | |
307 | #clock-cells = <0>; | |
bf6534a1 | 308 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
309 | reg = <0x01c200ac 0x4>; |
310 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
311 | clock-output-names = "pata"; | |
312 | }; | |
313 | ||
314 | ir0_clk: clk@01c200b0 { | |
315 | #clock-cells = <0>; | |
bf6534a1 | 316 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
317 | reg = <0x01c200b0 0x4>; |
318 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
319 | clock-output-names = "ir0"; | |
320 | }; | |
321 | ||
322 | ir1_clk: clk@01c200b4 { | |
323 | #clock-cells = <0>; | |
bf6534a1 | 324 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
325 | reg = <0x01c200b4 0x4>; |
326 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
327 | clock-output-names = "ir1"; | |
328 | }; | |
329 | ||
0076c8bd RB |
330 | usb_clk: clk@01c200cc { |
331 | #clock-cells = <1>; | |
332 | #reset-cells = <1>; | |
333 | compatible = "allwinner,sun4i-a10-usb-clk"; | |
334 | reg = <0x01c200cc 0x4>; | |
335 | clocks = <&pll6 1>; | |
336 | clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; | |
337 | }; | |
338 | ||
4b756ffb EL |
339 | spi3_clk: clk@01c200d4 { |
340 | #clock-cells = <0>; | |
bf6534a1 | 341 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
342 | reg = <0x01c200d4 0x4>; |
343 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
344 | clock-output-names = "spi3"; | |
345 | }; | |
69144e3b MR |
346 | }; |
347 | ||
b74aec1a | 348 | soc@01c00000 { |
69144e3b MR |
349 | compatible = "simple-bus"; |
350 | #address-cells = <1>; | |
351 | #size-cells = <1>; | |
69144e3b MR |
352 | ranges; |
353 | ||
1324f532 EL |
354 | dma: dma-controller@01c02000 { |
355 | compatible = "allwinner,sun4i-a10-dma"; | |
356 | reg = <0x01c02000 0x1000>; | |
357 | interrupts = <27>; | |
358 | clocks = <&ahb_gates 6>; | |
359 | #dma-cells = <2>; | |
360 | }; | |
361 | ||
65918e26 MR |
362 | spi0: spi@01c05000 { |
363 | compatible = "allwinner,sun4i-a10-spi"; | |
364 | reg = <0x01c05000 0x1000>; | |
365 | interrupts = <10>; | |
366 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
367 | clock-names = "ahb", "mod"; | |
4192ff81 EL |
368 | dmas = <&dma 1 27>, <&dma 1 26>; |
369 | dma-names = "rx", "tx"; | |
65918e26 MR |
370 | status = "disabled"; |
371 | #address-cells = <1>; | |
372 | #size-cells = <0>; | |
373 | }; | |
374 | ||
375 | spi1: spi@01c06000 { | |
376 | compatible = "allwinner,sun4i-a10-spi"; | |
377 | reg = <0x01c06000 0x1000>; | |
378 | interrupts = <11>; | |
379 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
380 | clock-names = "ahb", "mod"; | |
4192ff81 EL |
381 | dmas = <&dma 1 9>, <&dma 1 8>; |
382 | dma-names = "rx", "tx"; | |
65918e26 MR |
383 | status = "disabled"; |
384 | #address-cells = <1>; | |
385 | #size-cells = <0>; | |
386 | }; | |
387 | ||
e38afcb3 | 388 | emac: ethernet@01c0b000 { |
1c70e099 | 389 | compatible = "allwinner,sun4i-a10-emac"; |
e38afcb3 MR |
390 | reg = <0x01c0b000 0x1000>; |
391 | interrupts = <55>; | |
392 | clocks = <&ahb_gates 17>; | |
393 | status = "disabled"; | |
394 | }; | |
395 | ||
396 | mdio@01c0b080 { | |
1c70e099 | 397 | compatible = "allwinner,sun4i-a10-mdio"; |
e38afcb3 MR |
398 | reg = <0x01c0b080 0x14>; |
399 | status = "disabled"; | |
400 | #address-cells = <1>; | |
401 | #size-cells = <0>; | |
402 | }; | |
403 | ||
b258b369 DL |
404 | mmc0: mmc@01c0f000 { |
405 | compatible = "allwinner,sun4i-a10-mmc"; | |
406 | reg = <0x01c0f000 0x1000>; | |
407 | clocks = <&ahb_gates 8>, <&mmc0_clk>; | |
408 | clock-names = "ahb", "mmc"; | |
409 | interrupts = <32>; | |
410 | status = "disabled"; | |
411 | }; | |
412 | ||
413 | mmc1: mmc@01c10000 { | |
414 | compatible = "allwinner,sun4i-a10-mmc"; | |
415 | reg = <0x01c10000 0x1000>; | |
416 | clocks = <&ahb_gates 9>, <&mmc1_clk>; | |
417 | clock-names = "ahb", "mmc"; | |
418 | interrupts = <33>; | |
419 | status = "disabled"; | |
420 | }; | |
421 | ||
422 | mmc2: mmc@01c11000 { | |
423 | compatible = "allwinner,sun4i-a10-mmc"; | |
424 | reg = <0x01c11000 0x1000>; | |
425 | clocks = <&ahb_gates 10>, <&mmc2_clk>; | |
426 | clock-names = "ahb", "mmc"; | |
427 | interrupts = <34>; | |
428 | status = "disabled"; | |
429 | }; | |
430 | ||
431 | mmc3: mmc@01c12000 { | |
432 | compatible = "allwinner,sun4i-a10-mmc"; | |
433 | reg = <0x01c12000 0x1000>; | |
434 | clocks = <&ahb_gates 11>, <&mmc3_clk>; | |
435 | clock-names = "ahb", "mmc"; | |
436 | interrupts = <35>; | |
437 | status = "disabled"; | |
438 | }; | |
439 | ||
6ab1ce24 RB |
440 | usbphy: phy@01c13400 { |
441 | #phy-cells = <1>; | |
442 | compatible = "allwinner,sun4i-a10-usb-phy"; | |
443 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
444 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
445 | clocks = <&usb_clk 8>; | |
446 | clock-names = "usb_phy"; | |
447 | resets = <&usb_clk 1>, <&usb_clk 2>; | |
448 | reset-names = "usb1_reset", "usb2_reset"; | |
449 | status = "disabled"; | |
450 | }; | |
451 | ||
452 | ehci0: usb@01c14000 { | |
453 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
454 | reg = <0x01c14000 0x100>; | |
455 | interrupts = <39>; | |
456 | clocks = <&ahb_gates 1>; | |
457 | phys = <&usbphy 1>; | |
458 | phy-names = "usb"; | |
459 | status = "disabled"; | |
460 | }; | |
461 | ||
462 | ohci0: usb@01c14400 { | |
463 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
464 | reg = <0x01c14400 0x100>; | |
465 | interrupts = <64>; | |
466 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
467 | phys = <&usbphy 1>; | |
468 | phy-names = "usb"; | |
469 | status = "disabled"; | |
470 | }; | |
471 | ||
65918e26 MR |
472 | spi2: spi@01c17000 { |
473 | compatible = "allwinner,sun4i-a10-spi"; | |
474 | reg = <0x01c17000 0x1000>; | |
475 | interrupts = <12>; | |
476 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
477 | clock-names = "ahb", "mod"; | |
4192ff81 EL |
478 | dmas = <&dma 1 29>, <&dma 1 28>; |
479 | dma-names = "rx", "tx"; | |
65918e26 MR |
480 | status = "disabled"; |
481 | #address-cells = <1>; | |
482 | #size-cells = <0>; | |
483 | }; | |
484 | ||
248bd1e2 OS |
485 | ahci: sata@01c18000 { |
486 | compatible = "allwinner,sun4i-a10-ahci"; | |
487 | reg = <0x01c18000 0x1000>; | |
488 | interrupts = <56>; | |
489 | clocks = <&pll6 0>, <&ahb_gates 25>; | |
490 | status = "disabled"; | |
491 | }; | |
492 | ||
6ab1ce24 RB |
493 | ehci1: usb@01c1c000 { |
494 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
495 | reg = <0x01c1c000 0x100>; | |
496 | interrupts = <40>; | |
497 | clocks = <&ahb_gates 3>; | |
498 | phys = <&usbphy 2>; | |
499 | phy-names = "usb"; | |
500 | status = "disabled"; | |
501 | }; | |
502 | ||
503 | ohci1: usb@01c1c400 { | |
504 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
505 | reg = <0x01c1c400 0x100>; | |
506 | interrupts = <65>; | |
507 | clocks = <&usb_clk 7>, <&ahb_gates 4>; | |
508 | phys = <&usbphy 2>; | |
509 | phy-names = "usb"; | |
510 | status = "disabled"; | |
511 | }; | |
512 | ||
65918e26 MR |
513 | spi3: spi@01c1f000 { |
514 | compatible = "allwinner,sun4i-a10-spi"; | |
515 | reg = <0x01c1f000 0x1000>; | |
516 | interrupts = <50>; | |
517 | clocks = <&ahb_gates 23>, <&spi3_clk>; | |
518 | clock-names = "ahb", "mod"; | |
4192ff81 EL |
519 | dmas = <&dma 1 31>, <&dma 1 30>; |
520 | dma-names = "rx", "tx"; | |
65918e26 MR |
521 | status = "disabled"; |
522 | #address-cells = <1>; | |
523 | #size-cells = <0>; | |
524 | }; | |
525 | ||
69144e3b | 526 | intc: interrupt-controller@01c20400 { |
09504a7d | 527 | compatible = "allwinner,sun4i-a10-ic"; |
69144e3b MR |
528 | reg = <0x01c20400 0x400>; |
529 | interrupt-controller; | |
530 | #interrupt-cells = <1>; | |
531 | }; | |
532 | ||
e10911e1 | 533 | pio: pinctrl@01c20800 { |
874b4e45 MR |
534 | compatible = "allwinner,sun4i-a10-pinctrl"; |
535 | reg = <0x01c20800 0x400>; | |
39138bc6 | 536 | interrupts = <28>; |
36386d6e | 537 | clocks = <&apb0_gates 5>; |
e10911e1 | 538 | gpio-controller; |
39138bc6 | 539 | interrupt-controller; |
7d4ff96d | 540 | #interrupt-cells = <2>; |
874b4e45 | 541 | #size-cells = <0>; |
e10911e1 | 542 | #gpio-cells = <3>; |
581981be | 543 | |
1d5726e9 AB |
544 | pwm0_pins_a: pwm0@0 { |
545 | allwinner,pins = "PB2"; | |
546 | allwinner,function = "pwm"; | |
547 | allwinner,drive = <0>; | |
548 | allwinner,pull = <0>; | |
549 | }; | |
550 | ||
551 | pwm1_pins_a: pwm1@0 { | |
552 | allwinner,pins = "PI3"; | |
553 | allwinner,function = "pwm"; | |
554 | allwinner,drive = <0>; | |
555 | allwinner,pull = <0>; | |
556 | }; | |
557 | ||
581981be MR |
558 | uart0_pins_a: uart0@0 { |
559 | allwinner,pins = "PB22", "PB23"; | |
560 | allwinner,function = "uart0"; | |
561 | allwinner,drive = <0>; | |
562 | allwinner,pull = <0>; | |
563 | }; | |
564 | ||
565 | uart0_pins_b: uart0@1 { | |
566 | allwinner,pins = "PF2", "PF4"; | |
567 | allwinner,function = "uart0"; | |
568 | allwinner,drive = <0>; | |
569 | allwinner,pull = <0>; | |
570 | }; | |
571 | ||
572 | uart1_pins_a: uart1@0 { | |
573 | allwinner,pins = "PA10", "PA11"; | |
574 | allwinner,function = "uart1"; | |
575 | allwinner,drive = <0>; | |
576 | allwinner,pull = <0>; | |
577 | }; | |
27cce4ff MR |
578 | |
579 | i2c0_pins_a: i2c0@0 { | |
580 | allwinner,pins = "PB0", "PB1"; | |
581 | allwinner,function = "i2c0"; | |
582 | allwinner,drive = <0>; | |
583 | allwinner,pull = <0>; | |
584 | }; | |
585 | ||
586 | i2c1_pins_a: i2c1@0 { | |
587 | allwinner,pins = "PB18", "PB19"; | |
588 | allwinner,function = "i2c1"; | |
589 | allwinner,drive = <0>; | |
590 | allwinner,pull = <0>; | |
591 | }; | |
592 | ||
593 | i2c2_pins_a: i2c2@0 { | |
594 | allwinner,pins = "PB20", "PB21"; | |
595 | allwinner,function = "i2c2"; | |
596 | allwinner,drive = <0>; | |
597 | allwinner,pull = <0>; | |
598 | }; | |
496322bc | 599 | |
b21da664 MR |
600 | emac_pins_a: emac0@0 { |
601 | allwinner,pins = "PA0", "PA1", "PA2", | |
602 | "PA3", "PA4", "PA5", "PA6", | |
603 | "PA7", "PA8", "PA9", "PA10", | |
604 | "PA11", "PA12", "PA13", "PA14", | |
605 | "PA15", "PA16"; | |
606 | allwinner,function = "emac"; | |
607 | allwinner,drive = <0>; | |
608 | allwinner,pull = <0>; | |
609 | }; | |
b5f86a3a HG |
610 | |
611 | mmc0_pins_a: mmc0@0 { | |
612 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | |
613 | allwinner,function = "mmc0"; | |
614 | allwinner,drive = <2>; | |
615 | allwinner,pull = <0>; | |
616 | }; | |
617 | ||
618 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { | |
619 | allwinner,pins = "PH1"; | |
620 | allwinner,function = "gpio_in"; | |
621 | allwinner,drive = <0>; | |
622 | allwinner,pull = <1>; | |
623 | }; | |
a4e1099a HG |
624 | |
625 | ir0_pins_a: ir0@0 { | |
626 | allwinner,pins = "PB3","PB4"; | |
627 | allwinner,function = "ir0"; | |
628 | allwinner,drive = <0>; | |
629 | allwinner,pull = <0>; | |
630 | }; | |
631 | ||
632 | ir1_pins_a: ir1@0 { | |
633 | allwinner,pins = "PB22","PB23"; | |
634 | allwinner,function = "ir1"; | |
635 | allwinner,drive = <0>; | |
636 | allwinner,pull = <0>; | |
637 | }; | |
874b4e45 | 638 | }; |
89b3c99f | 639 | |
69144e3b | 640 | timer@01c20c00 { |
b4f26440 | 641 | compatible = "allwinner,sun4i-a10-timer"; |
69144e3b MR |
642 | reg = <0x01c20c00 0x90>; |
643 | interrupts = <22>; | |
644 | clocks = <&osc24M>; | |
645 | }; | |
646 | ||
647 | wdt: watchdog@01c20c90 { | |
ca5d04d9 | 648 | compatible = "allwinner,sun4i-a10-wdt"; |
69144e3b MR |
649 | reg = <0x01c20c90 0x10>; |
650 | }; | |
651 | ||
b5d905c7 | 652 | rtc: rtc@01c20d00 { |
5fc4bc89 | 653 | compatible = "allwinner,sun4i-a10-rtc"; |
b5d905c7 CC |
654 | reg = <0x01c20d00 0x20>; |
655 | interrupts = <24>; | |
656 | }; | |
657 | ||
4b57a395 AB |
658 | pwm: pwm@01c20e00 { |
659 | compatible = "allwinner,sun4i-a10-pwm"; | |
660 | reg = <0x01c20e00 0xc>; | |
661 | clocks = <&osc24M>; | |
662 | #pwm-cells = <3>; | |
663 | status = "disabled"; | |
664 | }; | |
665 | ||
a4e1099a HG |
666 | ir0: ir@01c21800 { |
667 | compatible = "allwinner,sun4i-a10-ir"; | |
668 | clocks = <&apb0_gates 6>, <&ir0_clk>; | |
669 | clock-names = "apb", "ir"; | |
670 | interrupts = <5>; | |
671 | reg = <0x01c21800 0x40>; | |
672 | status = "disabled"; | |
673 | }; | |
674 | ||
675 | ir1: ir@01c21c00 { | |
676 | compatible = "allwinner,sun4i-a10-ir"; | |
677 | clocks = <&apb0_gates 7>, <&ir1_clk>; | |
678 | clock-names = "apb", "ir"; | |
679 | interrupts = <6>; | |
680 | reg = <0x01c21c00 0x40>; | |
681 | status = "disabled"; | |
682 | }; | |
683 | ||
2bad969f | 684 | sid: eeprom@01c23800 { |
043d56ee | 685 | compatible = "allwinner,sun4i-a10-sid"; |
2bad969f OS |
686 | reg = <0x01c23800 0x10>; |
687 | }; | |
688 | ||
57c8839c | 689 | rtp: rtp@01c25000 { |
40dd8f3b | 690 | compatible = "allwinner,sun4i-a10-ts"; |
57c8839c HG |
691 | reg = <0x01c25000 0x100>; |
692 | interrupts = <29>; | |
693 | }; | |
694 | ||
89b3c99f MR |
695 | uart0: serial@01c28000 { |
696 | compatible = "snps,dw-apb-uart"; | |
697 | reg = <0x01c28000 0x400>; | |
698 | interrupts = <1>; | |
699 | reg-shift = <2>; | |
700 | reg-io-width = <4>; | |
9ff49ec7 | 701 | clocks = <&apb1_gates 16>; |
89b3c99f MR |
702 | status = "disabled"; |
703 | }; | |
76f14d0a | 704 | |
69144e3b MR |
705 | uart1: serial@01c28400 { |
706 | compatible = "snps,dw-apb-uart"; | |
707 | reg = <0x01c28400 0x400>; | |
708 | interrupts = <2>; | |
709 | reg-shift = <2>; | |
710 | reg-io-width = <4>; | |
711 | clocks = <&apb1_gates 17>; | |
712 | status = "disabled"; | |
713 | }; | |
714 | ||
76f14d0a MR |
715 | uart2: serial@01c28800 { |
716 | compatible = "snps,dw-apb-uart"; | |
717 | reg = <0x01c28800 0x400>; | |
718 | interrupts = <3>; | |
719 | reg-shift = <2>; | |
720 | reg-io-width = <4>; | |
9ff49ec7 | 721 | clocks = <&apb1_gates 18>; |
76f14d0a MR |
722 | status = "disabled"; |
723 | }; | |
724 | ||
69144e3b MR |
725 | uart3: serial@01c28c00 { |
726 | compatible = "snps,dw-apb-uart"; | |
727 | reg = <0x01c28c00 0x400>; | |
728 | interrupts = <4>; | |
729 | reg-shift = <2>; | |
730 | reg-io-width = <4>; | |
731 | clocks = <&apb1_gates 19>; | |
732 | status = "disabled"; | |
733 | }; | |
734 | ||
76f14d0a MR |
735 | uart4: serial@01c29000 { |
736 | compatible = "snps,dw-apb-uart"; | |
737 | reg = <0x01c29000 0x400>; | |
738 | interrupts = <17>; | |
739 | reg-shift = <2>; | |
740 | reg-io-width = <4>; | |
9ff49ec7 | 741 | clocks = <&apb1_gates 20>; |
76f14d0a MR |
742 | status = "disabled"; |
743 | }; | |
744 | ||
745 | uart5: serial@01c29400 { | |
746 | compatible = "snps,dw-apb-uart"; | |
747 | reg = <0x01c29400 0x400>; | |
748 | interrupts = <18>; | |
749 | reg-shift = <2>; | |
750 | reg-io-width = <4>; | |
9ff49ec7 | 751 | clocks = <&apb1_gates 21>; |
76f14d0a MR |
752 | status = "disabled"; |
753 | }; | |
754 | ||
755 | uart6: serial@01c29800 { | |
756 | compatible = "snps,dw-apb-uart"; | |
757 | reg = <0x01c29800 0x400>; | |
758 | interrupts = <19>; | |
759 | reg-shift = <2>; | |
760 | reg-io-width = <4>; | |
9ff49ec7 | 761 | clocks = <&apb1_gates 22>; |
76f14d0a MR |
762 | status = "disabled"; |
763 | }; | |
764 | ||
765 | uart7: serial@01c29c00 { | |
766 | compatible = "snps,dw-apb-uart"; | |
767 | reg = <0x01c29c00 0x400>; | |
768 | interrupts = <20>; | |
769 | reg-shift = <2>; | |
770 | reg-io-width = <4>; | |
9ff49ec7 | 771 | clocks = <&apb1_gates 23>; |
76f14d0a MR |
772 | status = "disabled"; |
773 | }; | |
f1741fda MR |
774 | |
775 | i2c0: i2c@01c2ac00 { | |
d275545e | 776 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
777 | reg = <0x01c2ac00 0x400>; |
778 | interrupts = <7>; | |
779 | clocks = <&apb1_gates 0>; | |
f1741fda | 780 | status = "disabled"; |
60bbe316 HG |
781 | #address-cells = <1>; |
782 | #size-cells = <0>; | |
f1741fda MR |
783 | }; |
784 | ||
785 | i2c1: i2c@01c2b000 { | |
d275545e | 786 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
787 | reg = <0x01c2b000 0x400>; |
788 | interrupts = <8>; | |
789 | clocks = <&apb1_gates 1>; | |
f1741fda | 790 | status = "disabled"; |
60bbe316 HG |
791 | #address-cells = <1>; |
792 | #size-cells = <0>; | |
f1741fda MR |
793 | }; |
794 | ||
795 | i2c2: i2c@01c2b400 { | |
d275545e | 796 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
797 | reg = <0x01c2b400 0x400>; |
798 | interrupts = <9>; | |
799 | clocks = <&apb1_gates 2>; | |
f1741fda | 800 | status = "disabled"; |
60bbe316 HG |
801 | #address-cells = <1>; |
802 | #size-cells = <0>; | |
f1741fda | 803 | }; |
874b4e45 | 804 | }; |
7423d2d8 | 805 | }; |