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Commit | Line | Data |
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7423d2d8 SR |
1 | /* |
2 | * Copyright 2012 Stefan Roese | |
3 | * Stefan Roese <sr@denx.de> | |
4 | * | |
033ba3d7 MR |
5 | * This file is dual-licensed: you can use it either under the terms |
6 | * of the GPL or the X11 license, at your option. Note that this dual | |
7 | * licensing only applies to this file, and not this project as a | |
8 | * whole. | |
7423d2d8 | 9 | * |
033ba3d7 MR |
10 | * a) This library is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of the | |
13 | * License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
033ba3d7 MR |
20 | * Or, alternatively, |
21 | * | |
22 | * b) Permission is hereby granted, free of charge, to any person | |
23 | * obtaining a copy of this software and associated documentation | |
24 | * files (the "Software"), to deal in the Software without | |
25 | * restriction, including without limitation the rights to use, | |
26 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
27 | * sell copies of the Software, and to permit persons to whom the | |
28 | * Software is furnished to do so, subject to the following | |
29 | * conditions: | |
30 | * | |
31 | * The above copyright notice and this permission notice shall be | |
32 | * included in all copies or substantial portions of the Software. | |
33 | * | |
34 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
35 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
36 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
37 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
38 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
39 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
40 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
41 | * OTHER DEALINGS IN THE SOFTWARE. | |
7423d2d8 SR |
42 | */ |
43 | ||
71455701 | 44 | #include "skeleton.dtsi" |
7423d2d8 | 45 | |
541ce2ca CYT |
46 | #include <dt-bindings/thermal/thermal.h> |
47 | ||
b516fa5d | 48 | #include <dt-bindings/clock/sun4i-a10-pll2.h> |
1f9f6a78 | 49 | #include <dt-bindings/dma/sun4i-a10.h> |
092a0c3b | 50 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
7423d2d8 SR |
51 | |
52 | / { | |
69144e3b MR |
53 | interrupt-parent = <&intc>; |
54 | ||
e751cce9 EL |
55 | aliases { |
56 | ethernet0 = &emac; | |
57 | }; | |
58 | ||
5790d4ee HG |
59 | chosen { |
60 | #address-cells = <1>; | |
61 | #size-cells = <1>; | |
62 | ranges; | |
63 | ||
a9f8cda3 | 64 | framebuffer@0 { |
d8cacaa3 MR |
65 | compatible = "allwinner,simple-framebuffer", |
66 | "simple-framebuffer"; | |
a9f8cda3 | 67 | allwinner,pipeline = "de_be0-lcd0-hdmi"; |
678e75d3 | 68 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, |
82f8582f | 69 | <&ahb_gates 44>, <&dram_gates 26>; |
5790d4ee HG |
70 | status = "disabled"; |
71 | }; | |
8cedd662 HG |
72 | |
73 | framebuffer@1 { | |
d8cacaa3 MR |
74 | compatible = "allwinner,simple-framebuffer", |
75 | "simple-framebuffer"; | |
8cedd662 HG |
76 | allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; |
77 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, | |
82f8582f CYT |
78 | <&ahb_gates 44>, <&ahb_gates 46>, |
79 | <&dram_gates 25>, <&dram_gates 26>; | |
8cedd662 HG |
80 | status = "disabled"; |
81 | }; | |
fd18c7ea HG |
82 | |
83 | framebuffer@2 { | |
84 | compatible = "allwinner,simple-framebuffer", | |
85 | "simple-framebuffer"; | |
86 | allwinner,pipeline = "de_fe0-de_be0-lcd0"; | |
87 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, | |
82f8582f CYT |
88 | <&ahb_gates 46>, <&dram_gates 25>, |
89 | <&dram_gates 26>; | |
fd18c7ea HG |
90 | status = "disabled"; |
91 | }; | |
92 | ||
93 | framebuffer@3 { | |
94 | compatible = "allwinner,simple-framebuffer", | |
95 | "simple-framebuffer"; | |
96 | allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; | |
97 | clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, | |
82f8582f CYT |
98 | <&ahb_gates 44>, <&ahb_gates 46>, |
99 | <&dram_gates 25>, <&dram_gates 26>; | |
fd18c7ea HG |
100 | status = "disabled"; |
101 | }; | |
5790d4ee HG |
102 | }; |
103 | ||
69144e3b | 104 | cpus { |
8b2efa89 AB |
105 | #address-cells = <1>; |
106 | #size-cells = <0>; | |
7294be5d | 107 | cpu0: cpu@0 { |
14c44aa5 | 108 | device_type = "cpu"; |
69144e3b | 109 | compatible = "arm,cortex-a8"; |
14c44aa5 | 110 | reg = <0x0>; |
7294be5d CYT |
111 | clocks = <&cpu>; |
112 | clock-latency = <244144>; /* 8 32k periods */ | |
113 | operating-points = < | |
8358aada | 114 | /* kHz uV */ |
7294be5d | 115 | 1008000 1400000 |
8358aada MR |
116 | 912000 1350000 |
117 | 864000 1300000 | |
118 | 624000 1250000 | |
7294be5d CYT |
119 | >; |
120 | #cooling-cells = <2>; | |
121 | cooling-min-level = <0>; | |
370a9b5f | 122 | cooling-max-level = <3>; |
69144e3b MR |
123 | }; |
124 | }; | |
125 | ||
541ce2ca CYT |
126 | thermal-zones { |
127 | cpu_thermal { | |
128 | /* milliseconds */ | |
129 | polling-delay-passive = <250>; | |
130 | polling-delay = <1000>; | |
131 | thermal-sensors = <&rtp>; | |
132 | ||
133 | cooling-maps { | |
134 | map0 { | |
135 | trip = <&cpu_alert0>; | |
136 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
137 | }; | |
138 | }; | |
139 | ||
140 | trips { | |
141 | cpu_alert0: cpu_alert0 { | |
142 | /* milliCelsius */ | |
143 | temperature = <850000>; | |
144 | hysteresis = <2000>; | |
145 | type = "passive"; | |
146 | }; | |
147 | ||
148 | cpu_crit: cpu_crit { | |
149 | /* milliCelsius */ | |
150 | temperature = <100000>; | |
151 | hysteresis = <2000>; | |
152 | type = "critical"; | |
153 | }; | |
154 | }; | |
69144e3b MR |
155 | }; |
156 | }; | |
157 | ||
7423d2d8 SR |
158 | memory { |
159 | reg = <0x40000000 0x80000000>; | |
160 | }; | |
874b4e45 | 161 | |
69144e3b MR |
162 | clocks { |
163 | #address-cells = <1>; | |
164 | #size-cells = <1>; | |
165 | ranges; | |
166 | ||
167 | /* | |
168 | * This is a dummy clock, to be used as placeholder on | |
169 | * other mux clocks when a specific parent clock is not | |
170 | * yet implemented. It should be dropped when the driver | |
171 | * is complete. | |
172 | */ | |
173 | dummy: dummy { | |
174 | #clock-cells = <0>; | |
175 | compatible = "fixed-clock"; | |
176 | clock-frequency = <0>; | |
177 | }; | |
178 | ||
dfb12c0c | 179 | osc24M: clk@01c20050 { |
69144e3b | 180 | #clock-cells = <0>; |
bf6534a1 | 181 | compatible = "allwinner,sun4i-a10-osc-clk"; |
69144e3b | 182 | reg = <0x01c20050 0x4>; |
92fd6e06 | 183 | clock-frequency = <24000000>; |
dfb12c0c | 184 | clock-output-names = "osc24M"; |
69144e3b MR |
185 | }; |
186 | ||
dfb12c0c | 187 | osc32k: clk@0 { |
69144e3b MR |
188 | #clock-cells = <0>; |
189 | compatible = "fixed-clock"; | |
190 | clock-frequency = <32768>; | |
dfb12c0c | 191 | clock-output-names = "osc32k"; |
69144e3b MR |
192 | }; |
193 | ||
dfb12c0c | 194 | pll1: clk@01c20000 { |
69144e3b | 195 | #clock-cells = <0>; |
bf6534a1 | 196 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
69144e3b MR |
197 | reg = <0x01c20000 0x4>; |
198 | clocks = <&osc24M>; | |
dfb12c0c | 199 | clock-output-names = "pll1"; |
69144e3b MR |
200 | }; |
201 | ||
6ee93e12 MR |
202 | pll2: clk@01c20008 { |
203 | #clock-cells = <1>; | |
204 | compatible = "allwinner,sun4i-a10-pll2-clk"; | |
205 | reg = <0x01c20008 0x8>; | |
206 | clocks = <&osc24M>; | |
207 | clock-output-names = "pll2-1x", "pll2-2x", | |
208 | "pll2-4x", "pll2-8x"; | |
209 | }; | |
210 | ||
dfb12c0c | 211 | pll4: clk@01c20018 { |
ec5589f7 | 212 | #clock-cells = <0>; |
bf6534a1 | 213 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
ec5589f7 EL |
214 | reg = <0x01c20018 0x4>; |
215 | clocks = <&osc24M>; | |
dfb12c0c | 216 | clock-output-names = "pll4"; |
ec5589f7 EL |
217 | }; |
218 | ||
dfb12c0c | 219 | pll5: clk@01c20020 { |
c3e5e66b | 220 | #clock-cells = <1>; |
bf6534a1 | 221 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
c3e5e66b EL |
222 | reg = <0x01c20020 0x4>; |
223 | clocks = <&osc24M>; | |
224 | clock-output-names = "pll5_ddr", "pll5_other"; | |
225 | }; | |
226 | ||
dfb12c0c | 227 | pll6: clk@01c20028 { |
c3e5e66b | 228 | #clock-cells = <1>; |
bf6534a1 | 229 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
c3e5e66b EL |
230 | reg = <0x01c20028 0x4>; |
231 | clocks = <&osc24M>; | |
232 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
233 | }; | |
234 | ||
69144e3b MR |
235 | /* dummy is 200M */ |
236 | cpu: cpu@01c20054 { | |
237 | #clock-cells = <0>; | |
bf6534a1 | 238 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
69144e3b MR |
239 | reg = <0x01c20054 0x4>; |
240 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
dfb12c0c | 241 | clock-output-names = "cpu"; |
69144e3b MR |
242 | }; |
243 | ||
244 | axi: axi@01c20054 { | |
245 | #clock-cells = <0>; | |
bf6534a1 | 246 | compatible = "allwinner,sun4i-a10-axi-clk"; |
69144e3b MR |
247 | reg = <0x01c20054 0x4>; |
248 | clocks = <&cpu>; | |
dfb12c0c | 249 | clock-output-names = "axi"; |
69144e3b MR |
250 | }; |
251 | ||
dfb12c0c | 252 | axi_gates: clk@01c2005c { |
69144e3b | 253 | #clock-cells = <1>; |
bf6534a1 | 254 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
69144e3b MR |
255 | reg = <0x01c2005c 0x4>; |
256 | clocks = <&axi>; | |
a3854006 | 257 | clock-indices = <0>; |
69144e3b MR |
258 | clock-output-names = "axi_dram"; |
259 | }; | |
260 | ||
261 | ahb: ahb@01c20054 { | |
262 | #clock-cells = <0>; | |
bf6534a1 | 263 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
69144e3b MR |
264 | reg = <0x01c20054 0x4>; |
265 | clocks = <&axi>; | |
dfb12c0c | 266 | clock-output-names = "ahb"; |
69144e3b MR |
267 | }; |
268 | ||
dfb12c0c | 269 | ahb_gates: clk@01c20060 { |
69144e3b | 270 | #clock-cells = <1>; |
bf6534a1 | 271 | compatible = "allwinner,sun4i-a10-ahb-gates-clk"; |
69144e3b MR |
272 | reg = <0x01c20060 0x8>; |
273 | clocks = <&ahb>; | |
a3854006 MR |
274 | clock-indices = <0>, <1>, |
275 | <2>, <3>, | |
276 | <4>, <5>, <6>, | |
277 | <7>, <8>, <9>, | |
278 | <10>, <11>, <12>, | |
279 | <13>, <14>, <16>, | |
280 | <17>, <18>, <20>, | |
281 | <21>, <22>, <23>, | |
282 | <24>, <25>, <26>, | |
283 | <32>, <33>, <34>, | |
284 | <35>, <36>, <37>, | |
285 | <40>, <41>, <43>, | |
286 | <44>, <45>, | |
287 | <46>, <47>, | |
288 | <50>, <52>; | |
69144e3b | 289 | clock-output-names = "ahb_usb0", "ahb_ehci0", |
a3854006 MR |
290 | "ahb_ohci0", "ahb_ehci1", |
291 | "ahb_ohci1", "ahb_ss", "ahb_dma", | |
292 | "ahb_bist", "ahb_mmc0", "ahb_mmc1", | |
293 | "ahb_mmc2", "ahb_mmc3", "ahb_ms", | |
294 | "ahb_nand", "ahb_sdram", "ahb_ace", | |
295 | "ahb_emac", "ahb_ts", "ahb_spi0", | |
296 | "ahb_spi1", "ahb_spi2", "ahb_spi3", | |
297 | "ahb_pata", "ahb_sata", "ahb_gps", | |
298 | "ahb_ve", "ahb_tvd", "ahb_tve0", | |
299 | "ahb_tve1", "ahb_lcd0", "ahb_lcd1", | |
300 | "ahb_csi0", "ahb_csi1", "ahb_hdmi", | |
301 | "ahb_de_be0", "ahb_de_be1", | |
302 | "ahb_de_fe0", "ahb_de_fe1", | |
303 | "ahb_mp", "ahb_mali400"; | |
69144e3b MR |
304 | }; |
305 | ||
306 | apb0: apb0@01c20054 { | |
307 | #clock-cells = <0>; | |
bf6534a1 | 308 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
69144e3b MR |
309 | reg = <0x01c20054 0x4>; |
310 | clocks = <&ahb>; | |
dfb12c0c | 311 | clock-output-names = "apb0"; |
69144e3b MR |
312 | }; |
313 | ||
dfb12c0c | 314 | apb0_gates: clk@01c20068 { |
69144e3b | 315 | #clock-cells = <1>; |
bf6534a1 | 316 | compatible = "allwinner,sun4i-a10-apb0-gates-clk"; |
69144e3b MR |
317 | reg = <0x01c20068 0x4>; |
318 | clocks = <&apb0>; | |
a3854006 MR |
319 | clock-indices = <0>, <1>, |
320 | <2>, <3>, | |
321 | <5>, <6>, | |
322 | <7>, <10>; | |
69144e3b | 323 | clock-output-names = "apb0_codec", "apb0_spdif", |
a3854006 MR |
324 | "apb0_ac97", "apb0_iis", |
325 | "apb0_pio", "apb0_ir0", | |
326 | "apb0_ir1", "apb0_keypad"; | |
69144e3b MR |
327 | }; |
328 | ||
acbcc0f0 | 329 | apb1: clk@01c20058 { |
69144e3b | 330 | #clock-cells = <0>; |
bf6534a1 | 331 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
69144e3b | 332 | reg = <0x01c20058 0x4>; |
acbcc0f0 | 333 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
dfb12c0c | 334 | clock-output-names = "apb1"; |
69144e3b MR |
335 | }; |
336 | ||
dfb12c0c | 337 | apb1_gates: clk@01c2006c { |
69144e3b | 338 | #clock-cells = <1>; |
bf6534a1 | 339 | compatible = "allwinner,sun4i-a10-apb1-gates-clk"; |
69144e3b MR |
340 | reg = <0x01c2006c 0x4>; |
341 | clocks = <&apb1>; | |
a3854006 MR |
342 | clock-indices = <0>, <1>, |
343 | <2>, <4>, | |
344 | <5>, <6>, | |
345 | <7>, <16>, | |
346 | <17>, <18>, | |
347 | <19>, <20>, | |
348 | <21>, <22>, | |
349 | <23>; | |
69144e3b | 350 | clock-output-names = "apb1_i2c0", "apb1_i2c1", |
a3854006 MR |
351 | "apb1_i2c2", "apb1_can", |
352 | "apb1_scr", "apb1_ps20", | |
353 | "apb1_ps21", "apb1_uart0", | |
354 | "apb1_uart1", "apb1_uart2", | |
355 | "apb1_uart3", "apb1_uart4", | |
356 | "apb1_uart5", "apb1_uart6", | |
357 | "apb1_uart7"; | |
69144e3b | 358 | }; |
4b756ffb EL |
359 | |
360 | nand_clk: clk@01c20080 { | |
361 | #clock-cells = <0>; | |
bf6534a1 | 362 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
363 | reg = <0x01c20080 0x4>; |
364 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
365 | clock-output-names = "nand"; | |
366 | }; | |
367 | ||
368 | ms_clk: clk@01c20084 { | |
369 | #clock-cells = <0>; | |
bf6534a1 | 370 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
371 | reg = <0x01c20084 0x4>; |
372 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
373 | clock-output-names = "ms"; | |
374 | }; | |
375 | ||
376 | mmc0_clk: clk@01c20088 { | |
d8c3a392 MR |
377 | #clock-cells = <1>; |
378 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
379 | reg = <0x01c20088 0x4>; |
380 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
381 | clock-output-names = "mmc0", |
382 | "mmc0_output", | |
383 | "mmc0_sample"; | |
4b756ffb EL |
384 | }; |
385 | ||
386 | mmc1_clk: clk@01c2008c { | |
d8c3a392 MR |
387 | #clock-cells = <1>; |
388 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
389 | reg = <0x01c2008c 0x4>; |
390 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
391 | clock-output-names = "mmc1", |
392 | "mmc1_output", | |
393 | "mmc1_sample"; | |
4b756ffb EL |
394 | }; |
395 | ||
396 | mmc2_clk: clk@01c20090 { | |
d8c3a392 MR |
397 | #clock-cells = <1>; |
398 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
399 | reg = <0x01c20090 0x4>; |
400 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
401 | clock-output-names = "mmc2", |
402 | "mmc2_output", | |
403 | "mmc2_sample"; | |
4b756ffb EL |
404 | }; |
405 | ||
406 | mmc3_clk: clk@01c20094 { | |
d8c3a392 MR |
407 | #clock-cells = <1>; |
408 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
409 | reg = <0x01c20094 0x4>; |
410 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
411 | clock-output-names = "mmc3", |
412 | "mmc3_output", | |
413 | "mmc3_sample"; | |
4b756ffb EL |
414 | }; |
415 | ||
416 | ts_clk: clk@01c20098 { | |
417 | #clock-cells = <0>; | |
bf6534a1 | 418 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
419 | reg = <0x01c20098 0x4>; |
420 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
421 | clock-output-names = "ts"; | |
422 | }; | |
423 | ||
424 | ss_clk: clk@01c2009c { | |
425 | #clock-cells = <0>; | |
bf6534a1 | 426 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
427 | reg = <0x01c2009c 0x4>; |
428 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
429 | clock-output-names = "ss"; | |
430 | }; | |
431 | ||
432 | spi0_clk: clk@01c200a0 { | |
433 | #clock-cells = <0>; | |
bf6534a1 | 434 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
435 | reg = <0x01c200a0 0x4>; |
436 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
437 | clock-output-names = "spi0"; | |
438 | }; | |
439 | ||
440 | spi1_clk: clk@01c200a4 { | |
441 | #clock-cells = <0>; | |
bf6534a1 | 442 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
443 | reg = <0x01c200a4 0x4>; |
444 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
445 | clock-output-names = "spi1"; | |
446 | }; | |
447 | ||
448 | spi2_clk: clk@01c200a8 { | |
449 | #clock-cells = <0>; | |
bf6534a1 | 450 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
451 | reg = <0x01c200a8 0x4>; |
452 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
453 | clock-output-names = "spi2"; | |
454 | }; | |
455 | ||
456 | pata_clk: clk@01c200ac { | |
457 | #clock-cells = <0>; | |
bf6534a1 | 458 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
459 | reg = <0x01c200ac 0x4>; |
460 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
461 | clock-output-names = "pata"; | |
462 | }; | |
463 | ||
464 | ir0_clk: clk@01c200b0 { | |
465 | #clock-cells = <0>; | |
bf6534a1 | 466 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
467 | reg = <0x01c200b0 0x4>; |
468 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
469 | clock-output-names = "ir0"; | |
470 | }; | |
471 | ||
472 | ir1_clk: clk@01c200b4 { | |
473 | #clock-cells = <0>; | |
bf6534a1 | 474 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
475 | reg = <0x01c200b4 0x4>; |
476 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
477 | clock-output-names = "ir1"; | |
478 | }; | |
479 | ||
1010cd54 MC |
480 | spdif_clk: clk@01c200c0 { |
481 | #clock-cells = <0>; | |
482 | compatible = "allwinner,sun4i-a10-mod1-clk"; | |
483 | reg = <0x01c200c0 0x4>; | |
484 | clocks = <&pll2 SUN4I_A10_PLL2_8X>, | |
485 | <&pll2 SUN4I_A10_PLL2_4X>, | |
486 | <&pll2 SUN4I_A10_PLL2_2X>, | |
487 | <&pll2 SUN4I_A10_PLL2_1X>; | |
488 | clock-output-names = "spdif"; | |
489 | }; | |
490 | ||
0076c8bd RB |
491 | usb_clk: clk@01c200cc { |
492 | #clock-cells = <1>; | |
8358aada | 493 | #reset-cells = <1>; |
0076c8bd RB |
494 | compatible = "allwinner,sun4i-a10-usb-clk"; |
495 | reg = <0x01c200cc 0x4>; | |
496 | clocks = <&pll6 1>; | |
d8cacaa3 MR |
497 | clock-output-names = "usb_ohci0", "usb_ohci1", |
498 | "usb_phy"; | |
0076c8bd RB |
499 | }; |
500 | ||
4b756ffb EL |
501 | spi3_clk: clk@01c200d4 { |
502 | #clock-cells = <0>; | |
bf6534a1 | 503 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
504 | reg = <0x01c200d4 0x4>; |
505 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
506 | clock-output-names = "spi3"; | |
507 | }; | |
b516fa5d | 508 | |
82f8582f CYT |
509 | dram_gates: clk@01c20100 { |
510 | #clock-cells = <1>; | |
511 | compatible = "allwinner,sun4i-a10-dram-gates-clk"; | |
512 | reg = <0x01c20100 0x4>; | |
513 | clocks = <&pll5 0>; | |
514 | clock-indices = <0>, | |
515 | <1>, <2>, | |
516 | <3>, | |
517 | <4>, | |
518 | <5>, <6>, | |
519 | <15>, | |
520 | <24>, <25>, | |
521 | <26>, <27>, | |
522 | <28>, <29>; | |
523 | clock-output-names = "dram_ve", | |
524 | "dram_csi0", "dram_csi1", | |
525 | "dram_ts", | |
526 | "dram_tvd", | |
527 | "dram_tve0", "dram_tve1", | |
528 | "dram_output", | |
529 | "dram_de_fe1", "dram_de_fe0", | |
530 | "dram_de_be0", "dram_de_be1", | |
531 | "dram_de_mp", "dram_ace"; | |
532 | }; | |
533 | ||
1ccc4939 CYT |
534 | ve_clk: clk@01c2013c { |
535 | #clock-cells = <0>; | |
536 | #reset-cells = <0>; | |
537 | compatible = "allwinner,sun4i-a10-ve-clk"; | |
538 | reg = <0x01c2013c 0x4>; | |
539 | clocks = <&pll4>; | |
540 | clock-output-names = "ve"; | |
541 | }; | |
542 | ||
b516fa5d MR |
543 | codec_clk: clk@01c20140 { |
544 | #clock-cells = <0>; | |
545 | compatible = "allwinner,sun4i-a10-codec-clk"; | |
546 | reg = <0x01c20140 0x4>; | |
547 | clocks = <&pll2 SUN4I_A10_PLL2_1X>; | |
548 | clock-output-names = "codec"; | |
549 | }; | |
69144e3b MR |
550 | }; |
551 | ||
b74aec1a | 552 | soc@01c00000 { |
69144e3b MR |
553 | compatible = "simple-bus"; |
554 | #address-cells = <1>; | |
555 | #size-cells = <1>; | |
69144e3b MR |
556 | ranges; |
557 | ||
1fbc1517 MR |
558 | sram-controller@01c00000 { |
559 | compatible = "allwinner,sun4i-a10-sram-controller"; | |
560 | reg = <0x01c00000 0x30>; | |
561 | #address-cells = <1>; | |
562 | #size-cells = <1>; | |
563 | ranges; | |
564 | ||
565 | sram_a: sram@00000000 { | |
566 | compatible = "mmio-sram"; | |
567 | reg = <0x00000000 0xc000>; | |
568 | #address-cells = <1>; | |
569 | #size-cells = <1>; | |
570 | ranges = <0 0x00000000 0xc000>; | |
571 | ||
572 | emac_sram: sram-section@8000 { | |
573 | compatible = "allwinner,sun4i-a10-sram-a3-a4"; | |
574 | reg = <0x8000 0x4000>; | |
575 | status = "disabled"; | |
576 | }; | |
577 | }; | |
578 | ||
579 | sram_d: sram@00010000 { | |
580 | compatible = "mmio-sram"; | |
581 | reg = <0x00010000 0x1000>; | |
582 | #address-cells = <1>; | |
583 | #size-cells = <1>; | |
584 | ranges = <0 0x00010000 0x1000>; | |
585 | ||
586 | otg_sram: sram-section@0000 { | |
587 | compatible = "allwinner,sun4i-a10-sram-d"; | |
588 | reg = <0x0000 0x1000>; | |
589 | status = "disabled"; | |
590 | }; | |
591 | }; | |
592 | }; | |
593 | ||
1324f532 EL |
594 | dma: dma-controller@01c02000 { |
595 | compatible = "allwinner,sun4i-a10-dma"; | |
596 | reg = <0x01c02000 0x1000>; | |
597 | interrupts = <27>; | |
598 | clocks = <&ahb_gates 6>; | |
599 | #dma-cells = <2>; | |
600 | }; | |
601 | ||
65918e26 MR |
602 | spi0: spi@01c05000 { |
603 | compatible = "allwinner,sun4i-a10-spi"; | |
604 | reg = <0x01c05000 0x1000>; | |
605 | interrupts = <10>; | |
606 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
607 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
608 | dmas = <&dma SUN4I_DMA_DEDICATED 27>, |
609 | <&dma SUN4I_DMA_DEDICATED 26>; | |
4192ff81 | 610 | dma-names = "rx", "tx"; |
65918e26 MR |
611 | status = "disabled"; |
612 | #address-cells = <1>; | |
613 | #size-cells = <0>; | |
614 | }; | |
615 | ||
616 | spi1: spi@01c06000 { | |
617 | compatible = "allwinner,sun4i-a10-spi"; | |
618 | reg = <0x01c06000 0x1000>; | |
619 | interrupts = <11>; | |
620 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
621 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
622 | dmas = <&dma SUN4I_DMA_DEDICATED 9>, |
623 | <&dma SUN4I_DMA_DEDICATED 8>; | |
4192ff81 | 624 | dma-names = "rx", "tx"; |
65918e26 MR |
625 | status = "disabled"; |
626 | #address-cells = <1>; | |
627 | #size-cells = <0>; | |
628 | }; | |
629 | ||
e38afcb3 | 630 | emac: ethernet@01c0b000 { |
1c70e099 | 631 | compatible = "allwinner,sun4i-a10-emac"; |
e38afcb3 MR |
632 | reg = <0x01c0b000 0x1000>; |
633 | interrupts = <55>; | |
634 | clocks = <&ahb_gates 17>; | |
1fbc1517 | 635 | allwinner,sram = <&emac_sram 1>; |
e38afcb3 MR |
636 | status = "disabled"; |
637 | }; | |
638 | ||
92395f56 | 639 | mdio: mdio@01c0b080 { |
1c70e099 | 640 | compatible = "allwinner,sun4i-a10-mdio"; |
e38afcb3 MR |
641 | reg = <0x01c0b080 0x14>; |
642 | status = "disabled"; | |
643 | #address-cells = <1>; | |
644 | #size-cells = <0>; | |
645 | }; | |
646 | ||
b258b369 DL |
647 | mmc0: mmc@01c0f000 { |
648 | compatible = "allwinner,sun4i-a10-mmc"; | |
649 | reg = <0x01c0f000 0x1000>; | |
d8c3a392 MR |
650 | clocks = <&ahb_gates 8>, |
651 | <&mmc0_clk 0>, | |
652 | <&mmc0_clk 1>, | |
653 | <&mmc0_clk 2>; | |
654 | clock-names = "ahb", | |
655 | "mmc", | |
656 | "output", | |
657 | "sample"; | |
b258b369 DL |
658 | interrupts = <32>; |
659 | status = "disabled"; | |
4c1bb9c3 HG |
660 | #address-cells = <1>; |
661 | #size-cells = <0>; | |
b258b369 DL |
662 | }; |
663 | ||
664 | mmc1: mmc@01c10000 { | |
665 | compatible = "allwinner,sun4i-a10-mmc"; | |
666 | reg = <0x01c10000 0x1000>; | |
d8c3a392 MR |
667 | clocks = <&ahb_gates 9>, |
668 | <&mmc1_clk 0>, | |
669 | <&mmc1_clk 1>, | |
670 | <&mmc1_clk 2>; | |
671 | clock-names = "ahb", | |
672 | "mmc", | |
673 | "output", | |
674 | "sample"; | |
b258b369 DL |
675 | interrupts = <33>; |
676 | status = "disabled"; | |
4c1bb9c3 HG |
677 | #address-cells = <1>; |
678 | #size-cells = <0>; | |
b258b369 DL |
679 | }; |
680 | ||
681 | mmc2: mmc@01c11000 { | |
682 | compatible = "allwinner,sun4i-a10-mmc"; | |
683 | reg = <0x01c11000 0x1000>; | |
d8c3a392 MR |
684 | clocks = <&ahb_gates 10>, |
685 | <&mmc2_clk 0>, | |
686 | <&mmc2_clk 1>, | |
687 | <&mmc2_clk 2>; | |
688 | clock-names = "ahb", | |
689 | "mmc", | |
690 | "output", | |
691 | "sample"; | |
b258b369 DL |
692 | interrupts = <34>; |
693 | status = "disabled"; | |
4c1bb9c3 HG |
694 | #address-cells = <1>; |
695 | #size-cells = <0>; | |
b258b369 DL |
696 | }; |
697 | ||
698 | mmc3: mmc@01c12000 { | |
699 | compatible = "allwinner,sun4i-a10-mmc"; | |
700 | reg = <0x01c12000 0x1000>; | |
d8c3a392 MR |
701 | clocks = <&ahb_gates 11>, |
702 | <&mmc3_clk 0>, | |
703 | <&mmc3_clk 1>, | |
704 | <&mmc3_clk 2>; | |
705 | clock-names = "ahb", | |
706 | "mmc", | |
707 | "output", | |
708 | "sample"; | |
b258b369 DL |
709 | interrupts = <35>; |
710 | status = "disabled"; | |
4c1bb9c3 HG |
711 | #address-cells = <1>; |
712 | #size-cells = <0>; | |
b258b369 DL |
713 | }; |
714 | ||
ce65037f HG |
715 | usb_otg: usb@01c13000 { |
716 | compatible = "allwinner,sun4i-a10-musb"; | |
717 | reg = <0x01c13000 0x0400>; | |
718 | clocks = <&ahb_gates 0>; | |
719 | interrupts = <38>; | |
720 | interrupt-names = "mc"; | |
721 | phys = <&usbphy 0>; | |
722 | phy-names = "usb"; | |
723 | extcon = <&usbphy 0>; | |
724 | allwinner,sram = <&otg_sram 1>; | |
725 | status = "disabled"; | |
726 | }; | |
727 | ||
6ab1ce24 RB |
728 | usbphy: phy@01c13400 { |
729 | #phy-cells = <1>; | |
730 | compatible = "allwinner,sun4i-a10-usb-phy"; | |
731 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
732 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
733 | clocks = <&usb_clk 8>; | |
734 | clock-names = "usb_phy"; | |
4dba4185 CYT |
735 | resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; |
736 | reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; | |
6ab1ce24 RB |
737 | status = "disabled"; |
738 | }; | |
739 | ||
740 | ehci0: usb@01c14000 { | |
741 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
742 | reg = <0x01c14000 0x100>; | |
743 | interrupts = <39>; | |
744 | clocks = <&ahb_gates 1>; | |
745 | phys = <&usbphy 1>; | |
746 | phy-names = "usb"; | |
747 | status = "disabled"; | |
748 | }; | |
749 | ||
750 | ohci0: usb@01c14400 { | |
751 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
752 | reg = <0x01c14400 0x100>; | |
753 | interrupts = <64>; | |
754 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
755 | phys = <&usbphy 1>; | |
756 | phy-names = "usb"; | |
757 | status = "disabled"; | |
758 | }; | |
759 | ||
56ba8c58 LC |
760 | crypto: crypto-engine@01c15000 { |
761 | compatible = "allwinner,sun4i-a10-crypto"; | |
762 | reg = <0x01c15000 0x1000>; | |
763 | interrupts = <86>; | |
764 | clocks = <&ahb_gates 5>, <&ss_clk>; | |
765 | clock-names = "ahb", "mod"; | |
766 | }; | |
767 | ||
65918e26 MR |
768 | spi2: spi@01c17000 { |
769 | compatible = "allwinner,sun4i-a10-spi"; | |
770 | reg = <0x01c17000 0x1000>; | |
771 | interrupts = <12>; | |
772 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
773 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
774 | dmas = <&dma SUN4I_DMA_DEDICATED 29>, |
775 | <&dma SUN4I_DMA_DEDICATED 28>; | |
4192ff81 | 776 | dma-names = "rx", "tx"; |
65918e26 MR |
777 | status = "disabled"; |
778 | #address-cells = <1>; | |
779 | #size-cells = <0>; | |
780 | }; | |
781 | ||
248bd1e2 OS |
782 | ahci: sata@01c18000 { |
783 | compatible = "allwinner,sun4i-a10-ahci"; | |
784 | reg = <0x01c18000 0x1000>; | |
785 | interrupts = <56>; | |
786 | clocks = <&pll6 0>, <&ahb_gates 25>; | |
787 | status = "disabled"; | |
788 | }; | |
789 | ||
6ab1ce24 RB |
790 | ehci1: usb@01c1c000 { |
791 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
792 | reg = <0x01c1c000 0x100>; | |
793 | interrupts = <40>; | |
794 | clocks = <&ahb_gates 3>; | |
795 | phys = <&usbphy 2>; | |
796 | phy-names = "usb"; | |
797 | status = "disabled"; | |
798 | }; | |
799 | ||
800 | ohci1: usb@01c1c400 { | |
801 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
802 | reg = <0x01c1c400 0x100>; | |
803 | interrupts = <65>; | |
804 | clocks = <&usb_clk 7>, <&ahb_gates 4>; | |
805 | phys = <&usbphy 2>; | |
806 | phy-names = "usb"; | |
807 | status = "disabled"; | |
808 | }; | |
809 | ||
65918e26 MR |
810 | spi3: spi@01c1f000 { |
811 | compatible = "allwinner,sun4i-a10-spi"; | |
812 | reg = <0x01c1f000 0x1000>; | |
813 | interrupts = <50>; | |
814 | clocks = <&ahb_gates 23>, <&spi3_clk>; | |
815 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
816 | dmas = <&dma SUN4I_DMA_DEDICATED 31>, |
817 | <&dma SUN4I_DMA_DEDICATED 30>; | |
4192ff81 | 818 | dma-names = "rx", "tx"; |
65918e26 MR |
819 | status = "disabled"; |
820 | #address-cells = <1>; | |
821 | #size-cells = <0>; | |
822 | }; | |
823 | ||
69144e3b | 824 | intc: interrupt-controller@01c20400 { |
09504a7d | 825 | compatible = "allwinner,sun4i-a10-ic"; |
69144e3b MR |
826 | reg = <0x01c20400 0x400>; |
827 | interrupt-controller; | |
828 | #interrupt-cells = <1>; | |
829 | }; | |
830 | ||
e10911e1 | 831 | pio: pinctrl@01c20800 { |
874b4e45 MR |
832 | compatible = "allwinner,sun4i-a10-pinctrl"; |
833 | reg = <0x01c20800 0x400>; | |
39138bc6 | 834 | interrupts = <28>; |
36386d6e | 835 | clocks = <&apb0_gates 5>; |
e10911e1 | 836 | gpio-controller; |
39138bc6 | 837 | interrupt-controller; |
b03e0816 | 838 | #interrupt-cells = <3>; |
e10911e1 | 839 | #gpio-cells = <3>; |
581981be | 840 | |
1d5726e9 AB |
841 | pwm0_pins_a: pwm0@0 { |
842 | allwinner,pins = "PB2"; | |
843 | allwinner,function = "pwm"; | |
092a0c3b MR |
844 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
845 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1d5726e9 AB |
846 | }; |
847 | ||
848 | pwm1_pins_a: pwm1@0 { | |
849 | allwinner,pins = "PI3"; | |
850 | allwinner,function = "pwm"; | |
092a0c3b MR |
851 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
852 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1d5726e9 AB |
853 | }; |
854 | ||
581981be MR |
855 | uart0_pins_a: uart0@0 { |
856 | allwinner,pins = "PB22", "PB23"; | |
857 | allwinner,function = "uart0"; | |
092a0c3b MR |
858 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
859 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
581981be MR |
860 | }; |
861 | ||
862 | uart0_pins_b: uart0@1 { | |
863 | allwinner,pins = "PF2", "PF4"; | |
864 | allwinner,function = "uart0"; | |
092a0c3b MR |
865 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
866 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
581981be MR |
867 | }; |
868 | ||
869 | uart1_pins_a: uart1@0 { | |
870 | allwinner,pins = "PA10", "PA11"; | |
871 | allwinner,function = "uart1"; | |
092a0c3b MR |
872 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
873 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
581981be | 874 | }; |
27cce4ff MR |
875 | |
876 | i2c0_pins_a: i2c0@0 { | |
877 | allwinner,pins = "PB0", "PB1"; | |
878 | allwinner,function = "i2c0"; | |
092a0c3b MR |
879 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
880 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
27cce4ff MR |
881 | }; |
882 | ||
883 | i2c1_pins_a: i2c1@0 { | |
884 | allwinner,pins = "PB18", "PB19"; | |
885 | allwinner,function = "i2c1"; | |
092a0c3b MR |
886 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
887 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
27cce4ff MR |
888 | }; |
889 | ||
890 | i2c2_pins_a: i2c2@0 { | |
891 | allwinner,pins = "PB20", "PB21"; | |
892 | allwinner,function = "i2c2"; | |
092a0c3b MR |
893 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
894 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
27cce4ff | 895 | }; |
496322bc | 896 | |
b21da664 MR |
897 | emac_pins_a: emac0@0 { |
898 | allwinner,pins = "PA0", "PA1", "PA2", | |
899 | "PA3", "PA4", "PA5", "PA6", | |
900 | "PA7", "PA8", "PA9", "PA10", | |
901 | "PA11", "PA12", "PA13", "PA14", | |
902 | "PA15", "PA16"; | |
903 | allwinner,function = "emac"; | |
092a0c3b MR |
904 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
905 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
b21da664 | 906 | }; |
b5f86a3a HG |
907 | |
908 | mmc0_pins_a: mmc0@0 { | |
d8cacaa3 MR |
909 | allwinner,pins = "PF0", "PF1", "PF2", |
910 | "PF3", "PF4", "PF5"; | |
b5f86a3a | 911 | allwinner,function = "mmc0"; |
092a0c3b MR |
912 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
913 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
b5f86a3a HG |
914 | }; |
915 | ||
916 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { | |
917 | allwinner,pins = "PH1"; | |
918 | allwinner,function = "gpio_in"; | |
092a0c3b MR |
919 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
920 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
b5f86a3a | 921 | }; |
a4e1099a | 922 | |
469a22e6 MC |
923 | ir0_rx_pins_a: ir0@0 { |
924 | allwinner,pins = "PB4"; | |
a4e1099a | 925 | allwinner,function = "ir0"; |
092a0c3b MR |
926 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
927 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
a4e1099a HG |
928 | }; |
929 | ||
469a22e6 MC |
930 | ir0_tx_pins_a: ir0@1 { |
931 | allwinner,pins = "PB3"; | |
932 | allwinner,function = "ir0"; | |
933 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
934 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
935 | }; | |
936 | ||
937 | ir1_rx_pins_a: ir1@0 { | |
938 | allwinner,pins = "PB23"; | |
939 | allwinner,function = "ir1"; | |
940 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
941 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
942 | }; | |
943 | ||
944 | ir1_tx_pins_a: ir1@1 { | |
945 | allwinner,pins = "PB22"; | |
a4e1099a | 946 | allwinner,function = "ir1"; |
092a0c3b MR |
947 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
948 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
a4e1099a | 949 | }; |
ec66d0bb AG |
950 | |
951 | spi0_pins_a: spi0@0 { | |
f3022c6c MR |
952 | allwinner,pins = "PI11", "PI12", "PI13"; |
953 | allwinner,function = "spi0"; | |
954 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
955 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
956 | }; | |
957 | ||
958 | spi0_cs0_pins_a: spi0_cs0@0 { | |
959 | allwinner,pins = "PI10"; | |
ec66d0bb | 960 | allwinner,function = "spi0"; |
092a0c3b MR |
961 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
962 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb AG |
963 | }; |
964 | ||
965 | spi1_pins_a: spi1@0 { | |
f3022c6c MR |
966 | allwinner,pins = "PI17", "PI18", "PI19"; |
967 | allwinner,function = "spi1"; | |
968 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
969 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
970 | }; | |
971 | ||
972 | spi1_cs0_pins_a: spi1_cs0@0 { | |
973 | allwinner,pins = "PI16"; | |
ec66d0bb | 974 | allwinner,function = "spi1"; |
092a0c3b MR |
975 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
976 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb AG |
977 | }; |
978 | ||
979 | spi2_pins_a: spi2@0 { | |
f3022c6c | 980 | allwinner,pins = "PC20", "PC21", "PC22"; |
ec66d0bb | 981 | allwinner,function = "spi2"; |
092a0c3b MR |
982 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
983 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb AG |
984 | }; |
985 | ||
986 | spi2_pins_b: spi2@1 { | |
f3022c6c MR |
987 | allwinner,pins = "PB15", "PB16", "PB17"; |
988 | allwinner,function = "spi2"; | |
989 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
990 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
991 | }; | |
992 | ||
993 | spi2_cs0_pins_a: spi2_cs0@0 { | |
994 | allwinner,pins = "PC19"; | |
995 | allwinner,function = "spi2"; | |
996 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
997 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
998 | }; | |
999 | ||
1000 | spi2_cs0_pins_b: spi2_cs0@1 { | |
1001 | allwinner,pins = "PB14"; | |
ec66d0bb | 1002 | allwinner,function = "spi2"; |
092a0c3b MR |
1003 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1004 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb | 1005 | }; |
1e8d1567 VP |
1006 | |
1007 | ps20_pins_a: ps20@0 { | |
1008 | allwinner,pins = "PI20", "PI21"; | |
1009 | allwinner,function = "ps2"; | |
1010 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1011 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1012 | }; | |
1013 | ||
1014 | ps21_pins_a: ps21@0 { | |
1015 | allwinner,pins = "PH12", "PH13"; | |
1016 | allwinner,function = "ps2"; | |
1017 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1018 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
a4e1099a | 1019 | }; |
79f969f0 MC |
1020 | |
1021 | spdif_tx_pins_a: spdif@0 { | |
1022 | allwinner,pins = "PB13"; | |
1023 | allwinner,function = "spdif"; | |
1024 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1025 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
1026 | }; | |
874b4e45 | 1027 | }; |
89b3c99f | 1028 | |
69144e3b | 1029 | timer@01c20c00 { |
b4f26440 | 1030 | compatible = "allwinner,sun4i-a10-timer"; |
69144e3b MR |
1031 | reg = <0x01c20c00 0x90>; |
1032 | interrupts = <22>; | |
1033 | clocks = <&osc24M>; | |
1034 | }; | |
1035 | ||
1036 | wdt: watchdog@01c20c90 { | |
ca5d04d9 | 1037 | compatible = "allwinner,sun4i-a10-wdt"; |
69144e3b MR |
1038 | reg = <0x01c20c90 0x10>; |
1039 | }; | |
1040 | ||
b5d905c7 | 1041 | rtc: rtc@01c20d00 { |
5fc4bc89 | 1042 | compatible = "allwinner,sun4i-a10-rtc"; |
b5d905c7 CC |
1043 | reg = <0x01c20d00 0x20>; |
1044 | interrupts = <24>; | |
1045 | }; | |
1046 | ||
4b57a395 AB |
1047 | pwm: pwm@01c20e00 { |
1048 | compatible = "allwinner,sun4i-a10-pwm"; | |
1049 | reg = <0x01c20e00 0xc>; | |
1050 | clocks = <&osc24M>; | |
1051 | #pwm-cells = <3>; | |
1052 | status = "disabled"; | |
1053 | }; | |
1054 | ||
a4e1099a HG |
1055 | ir0: ir@01c21800 { |
1056 | compatible = "allwinner,sun4i-a10-ir"; | |
1057 | clocks = <&apb0_gates 6>, <&ir0_clk>; | |
1058 | clock-names = "apb", "ir"; | |
1059 | interrupts = <5>; | |
1060 | reg = <0x01c21800 0x40>; | |
1061 | status = "disabled"; | |
1062 | }; | |
1063 | ||
1064 | ir1: ir@01c21c00 { | |
1065 | compatible = "allwinner,sun4i-a10-ir"; | |
1066 | clocks = <&apb0_gates 7>, <&ir1_clk>; | |
1067 | clock-names = "apb", "ir"; | |
1068 | interrupts = <6>; | |
1069 | reg = <0x01c21c00 0x40>; | |
1070 | status = "disabled"; | |
1071 | }; | |
1072 | ||
b0512e15 HG |
1073 | lradc: lradc@01c22800 { |
1074 | compatible = "allwinner,sun4i-a10-lradc-keys"; | |
1075 | reg = <0x01c22800 0x100>; | |
1076 | interrupts = <31>; | |
1077 | status = "disabled"; | |
1078 | }; | |
1079 | ||
bcf88450 MC |
1080 | codec: codec@01c22c00 { |
1081 | #sound-dai-cells = <0>; | |
1082 | compatible = "allwinner,sun4i-a10-codec"; | |
1083 | reg = <0x01c22c00 0x40>; | |
1084 | interrupts = <30>; | |
1085 | clocks = <&apb0_gates 0>, <&codec_clk>; | |
1086 | clock-names = "apb", "codec"; | |
1087 | dmas = <&dma SUN4I_DMA_NORMAL 19>, | |
1088 | <&dma SUN4I_DMA_NORMAL 19>; | |
1089 | dma-names = "rx", "tx"; | |
1090 | status = "disabled"; | |
1091 | }; | |
1092 | ||
2bad969f | 1093 | sid: eeprom@01c23800 { |
043d56ee | 1094 | compatible = "allwinner,sun4i-a10-sid"; |
2bad969f OS |
1095 | reg = <0x01c23800 0x10>; |
1096 | }; | |
1097 | ||
57c8839c | 1098 | rtp: rtp@01c25000 { |
40dd8f3b | 1099 | compatible = "allwinner,sun4i-a10-ts"; |
57c8839c HG |
1100 | reg = <0x01c25000 0x100>; |
1101 | interrupts = <29>; | |
41e7afb1 | 1102 | #thermal-sensor-cells = <0>; |
57c8839c HG |
1103 | }; |
1104 | ||
89b3c99f MR |
1105 | uart0: serial@01c28000 { |
1106 | compatible = "snps,dw-apb-uart"; | |
1107 | reg = <0x01c28000 0x400>; | |
1108 | interrupts = <1>; | |
1109 | reg-shift = <2>; | |
1110 | reg-io-width = <4>; | |
9ff49ec7 | 1111 | clocks = <&apb1_gates 16>; |
89b3c99f MR |
1112 | status = "disabled"; |
1113 | }; | |
76f14d0a | 1114 | |
69144e3b MR |
1115 | uart1: serial@01c28400 { |
1116 | compatible = "snps,dw-apb-uart"; | |
1117 | reg = <0x01c28400 0x400>; | |
1118 | interrupts = <2>; | |
1119 | reg-shift = <2>; | |
1120 | reg-io-width = <4>; | |
1121 | clocks = <&apb1_gates 17>; | |
1122 | status = "disabled"; | |
1123 | }; | |
1124 | ||
76f14d0a MR |
1125 | uart2: serial@01c28800 { |
1126 | compatible = "snps,dw-apb-uart"; | |
1127 | reg = <0x01c28800 0x400>; | |
1128 | interrupts = <3>; | |
1129 | reg-shift = <2>; | |
1130 | reg-io-width = <4>; | |
9ff49ec7 | 1131 | clocks = <&apb1_gates 18>; |
76f14d0a MR |
1132 | status = "disabled"; |
1133 | }; | |
1134 | ||
69144e3b MR |
1135 | uart3: serial@01c28c00 { |
1136 | compatible = "snps,dw-apb-uart"; | |
1137 | reg = <0x01c28c00 0x400>; | |
1138 | interrupts = <4>; | |
1139 | reg-shift = <2>; | |
1140 | reg-io-width = <4>; | |
1141 | clocks = <&apb1_gates 19>; | |
1142 | status = "disabled"; | |
1143 | }; | |
1144 | ||
76f14d0a MR |
1145 | uart4: serial@01c29000 { |
1146 | compatible = "snps,dw-apb-uart"; | |
1147 | reg = <0x01c29000 0x400>; | |
1148 | interrupts = <17>; | |
1149 | reg-shift = <2>; | |
1150 | reg-io-width = <4>; | |
9ff49ec7 | 1151 | clocks = <&apb1_gates 20>; |
76f14d0a MR |
1152 | status = "disabled"; |
1153 | }; | |
1154 | ||
1155 | uart5: serial@01c29400 { | |
1156 | compatible = "snps,dw-apb-uart"; | |
1157 | reg = <0x01c29400 0x400>; | |
1158 | interrupts = <18>; | |
1159 | reg-shift = <2>; | |
1160 | reg-io-width = <4>; | |
9ff49ec7 | 1161 | clocks = <&apb1_gates 21>; |
76f14d0a MR |
1162 | status = "disabled"; |
1163 | }; | |
1164 | ||
1165 | uart6: serial@01c29800 { | |
1166 | compatible = "snps,dw-apb-uart"; | |
1167 | reg = <0x01c29800 0x400>; | |
1168 | interrupts = <19>; | |
1169 | reg-shift = <2>; | |
1170 | reg-io-width = <4>; | |
9ff49ec7 | 1171 | clocks = <&apb1_gates 22>; |
76f14d0a MR |
1172 | status = "disabled"; |
1173 | }; | |
1174 | ||
1175 | uart7: serial@01c29c00 { | |
1176 | compatible = "snps,dw-apb-uart"; | |
1177 | reg = <0x01c29c00 0x400>; | |
1178 | interrupts = <20>; | |
1179 | reg-shift = <2>; | |
1180 | reg-io-width = <4>; | |
9ff49ec7 | 1181 | clocks = <&apb1_gates 23>; |
76f14d0a MR |
1182 | status = "disabled"; |
1183 | }; | |
f1741fda MR |
1184 | |
1185 | i2c0: i2c@01c2ac00 { | |
d275545e | 1186 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
1187 | reg = <0x01c2ac00 0x400>; |
1188 | interrupts = <7>; | |
1189 | clocks = <&apb1_gates 0>; | |
f1741fda | 1190 | status = "disabled"; |
60bbe316 HG |
1191 | #address-cells = <1>; |
1192 | #size-cells = <0>; | |
f1741fda MR |
1193 | }; |
1194 | ||
1195 | i2c1: i2c@01c2b000 { | |
d275545e | 1196 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
1197 | reg = <0x01c2b000 0x400>; |
1198 | interrupts = <8>; | |
1199 | clocks = <&apb1_gates 1>; | |
f1741fda | 1200 | status = "disabled"; |
60bbe316 HG |
1201 | #address-cells = <1>; |
1202 | #size-cells = <0>; | |
f1741fda MR |
1203 | }; |
1204 | ||
1205 | i2c2: i2c@01c2b400 { | |
d275545e | 1206 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
1207 | reg = <0x01c2b400 0x400>; |
1208 | interrupts = <9>; | |
1209 | clocks = <&apb1_gates 2>; | |
f1741fda | 1210 | status = "disabled"; |
60bbe316 HG |
1211 | #address-cells = <1>; |
1212 | #size-cells = <0>; | |
f1741fda | 1213 | }; |
196654ae VP |
1214 | |
1215 | ps20: ps2@01c2a000 { | |
1216 | compatible = "allwinner,sun4i-a10-ps2"; | |
1217 | reg = <0x01c2a000 0x400>; | |
1218 | interrupts = <62>; | |
1219 | clocks = <&apb1_gates 6>; | |
1220 | status = "disabled"; | |
1221 | }; | |
1222 | ||
1223 | ps21: ps2@01c2a400 { | |
1224 | compatible = "allwinner,sun4i-a10-ps2"; | |
1225 | reg = <0x01c2a400 0x400>; | |
1226 | interrupts = <63>; | |
1227 | clocks = <&apb1_gates 7>; | |
1228 | status = "disabled"; | |
1229 | }; | |
874b4e45 | 1230 | }; |
7423d2d8 | 1231 | }; |