]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blame - arch/arm/boot/dts/sun4i-a10.dtsi
projects / mirror_ubuntu-eoan-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: sunxi: DT: Convert the DTs to use the generic interrupt header
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / sun4i-a10.dtsi
CommitLineData
7423d2d8
SR		 1/*
2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
71455701 13#include "skeleton.dtsi"
7423d2d8 14
1f9f6a78 15#include <dt-bindings/dma/sun4i-a10.h>
092a0c3b 16#include <dt-bindings/pinctrl/sun4i-a10.h>
1f9f6a78 17
7423d2d8 18/ {
69144e3b
MR		 19 interrupt-parent = <&intc>;
20
e751cce9
EL		 21 aliases {
22 ethernet0 = &emac;
10b302a2
MR		 23 serial0 = &uart0;
24 serial1 = &uart1;
143b13d6
MR		 25 serial2 = &uart2;
26 serial3 = &uart3;
27 serial4 = &uart4;
28 serial5 = &uart5;
29 serial6 = &uart6;
30 serial7 = &uart7;
e751cce9
EL		 31 };
32
5790d4ee
HG		 33 chosen {
34 #address-cells = <1>;
35 #size-cells = <1>;
36 ranges;
37
a9f8cda3
HG		 38 framebuffer@0 {
39 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
40 allwinner,pipeline = "de_be0-lcd0-hdmi";
678e75d3
HG		 41 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
42 <&ahb_gates 44>;
5790d4ee
HG		 43 status = "disabled";
44 };
8cedd662
HG		 45
46 framebuffer@1 {
47 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
48 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
49 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
50 <&ahb_gates 44>, <&ahb_gates 46>;
51 status = "disabled";
52 };
5790d4ee
HG		 53 };
54
69144e3b 55 cpus {
8b2efa89
AB		 56 #address-cells = <1>;
57 #size-cells = <0>;
69144e3b 58 cpu@0 {
14c44aa5 59 device_type = "cpu";
69144e3b 60 compatible = "arm,cortex-a8";
14c44aa5 61 reg = <0x0>;
69144e3b
MR		 62 };
63 };
64
7423d2d8
SR		 65 memory {
66 reg = <0x40000000 0x80000000>;
67 };
874b4e45 68
69144e3b
MR		 69 clocks {
70 #address-cells = <1>;
71 #size-cells = <1>;
72 ranges;
73
74 /*
75 * This is a dummy clock, to be used as placeholder on
76 * other mux clocks when a specific parent clock is not
77 * yet implemented. It should be dropped when the driver
78 * is complete.
79 */
80 dummy: dummy {
81 #clock-cells = <0>;
82 compatible = "fixed-clock";
83 clock-frequency = <0>;
84 };
85
dfb12c0c 86 osc24M: clk@01c20050 {
69144e3b 87 #clock-cells = <0>;
bf6534a1 88 compatible = "allwinner,sun4i-a10-osc-clk";
69144e3b 89 reg = <0x01c20050 0x4>;
92fd6e06 90 clock-frequency = <24000000>;
dfb12c0c 91 clock-output-names = "osc24M";
69144e3b
MR		 92 };
93
dfb12c0c 94 osc32k: clk@0 {
69144e3b
MR		 95 #clock-cells = <0>;
96 compatible = "fixed-clock";
97 clock-frequency = <32768>;
dfb12c0c 98 clock-output-names = "osc32k";
69144e3b
MR		 99 };
100
dfb12c0c 101 pll1: clk@01c20000 {
69144e3b 102 #clock-cells = <0>;
bf6534a1 103 compatible = "allwinner,sun4i-a10-pll1-clk";
69144e3b
MR		 104 reg = <0x01c20000 0x4>;
105 clocks = <&osc24M>;
dfb12c0c 106 clock-output-names = "pll1";
69144e3b
MR		 107 };
108
dfb12c0c 109 pll4: clk@01c20018 {
ec5589f7 110 #clock-cells = <0>;
bf6534a1 111 compatible = "allwinner,sun4i-a10-pll1-clk";
ec5589f7
EL		 112 reg = <0x01c20018 0x4>;
113 clocks = <&osc24M>;
dfb12c0c 114 clock-output-names = "pll4";
ec5589f7
EL		 115 };
116
dfb12c0c 117 pll5: clk@01c20020 {
c3e5e66b 118 #clock-cells = <1>;
bf6534a1 119 compatible = "allwinner,sun4i-a10-pll5-clk";
c3e5e66b
EL		 120 reg = <0x01c20020 0x4>;
121 clocks = <&osc24M>;
122 clock-output-names = "pll5_ddr", "pll5_other";
123 };
124
dfb12c0c 125 pll6: clk@01c20028 {
c3e5e66b 126 #clock-cells = <1>;
bf6534a1 127 compatible = "allwinner,sun4i-a10-pll6-clk";
c3e5e66b
EL		 128 reg = <0x01c20028 0x4>;
129 clocks = <&osc24M>;
130 clock-output-names = "pll6_sata", "pll6_other", "pll6";
131 };
132
69144e3b
MR		 133 /* dummy is 200M */
134 cpu: cpu@01c20054 {
135 #clock-cells = <0>;
bf6534a1 136 compatible = "allwinner,sun4i-a10-cpu-clk";
69144e3b
MR		 137 reg = <0x01c20054 0x4>;
138 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
dfb12c0c 139 clock-output-names = "cpu";
69144e3b
MR		 140 };
141
142 axi: axi@01c20054 {
143 #clock-cells = <0>;
bf6534a1 144 compatible = "allwinner,sun4i-a10-axi-clk";
69144e3b
MR		 145 reg = <0x01c20054 0x4>;
146 clocks = <&cpu>;
dfb12c0c 147 clock-output-names = "axi";
69144e3b
MR		 148 };
149
dfb12c0c 150 axi_gates: clk@01c2005c {
69144e3b 151 #clock-cells = <1>;
bf6534a1 152 compatible = "allwinner,sun4i-a10-axi-gates-clk";
69144e3b
MR		 153 reg = <0x01c2005c 0x4>;
154 clocks = <&axi>;
155 clock-output-names = "axi_dram";
156 };
157
158 ahb: ahb@01c20054 {
159 #clock-cells = <0>;
bf6534a1 160 compatible = "allwinner,sun4i-a10-ahb-clk";
69144e3b
MR		 161 reg = <0x01c20054 0x4>;
162 clocks = <&axi>;
dfb12c0c 163 clock-output-names = "ahb";
69144e3b
MR		 164 };
165
dfb12c0c 166 ahb_gates: clk@01c20060 {
69144e3b 167 #clock-cells = <1>;
bf6534a1 168 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
69144e3b
MR		 169 reg = <0x01c20060 0x8>;
170 clocks = <&ahb>;
171 clock-output-names = "ahb_usb0", "ahb_ehci0",
172 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
173 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
174 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
175 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
176 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
177 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
178 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
179 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
180 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
181 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
182 };
183
184 apb0: apb0@01c20054 {
185 #clock-cells = <0>;
bf6534a1 186 compatible = "allwinner,sun4i-a10-apb0-clk";
69144e3b
MR		 187 reg = <0x01c20054 0x4>;
188 clocks = <&ahb>;
dfb12c0c 189 clock-output-names = "apb0";
69144e3b
MR		 190 };
191
dfb12c0c 192 apb0_gates: clk@01c20068 {
69144e3b 193 #clock-cells = <1>;
bf6534a1 194 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
69144e3b
MR		 195 reg = <0x01c20068 0x4>;
196 clocks = <&apb0>;
197 clock-output-names = "apb0_codec", "apb0_spdif",
198 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
199 "apb0_ir1", "apb0_keypad";
200 };
201
acbcc0f0 202 apb1: clk@01c20058 {
69144e3b 203 #clock-cells = <0>;
bf6534a1 204 compatible = "allwinner,sun4i-a10-apb1-clk";
69144e3b 205 reg = <0x01c20058 0x4>;
acbcc0f0 206 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
dfb12c0c 207 clock-output-names = "apb1";
69144e3b
MR		 208 };
209
dfb12c0c 210 apb1_gates: clk@01c2006c {
69144e3b 211 #clock-cells = <1>;
bf6534a1 212 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
69144e3b
MR		 213 reg = <0x01c2006c 0x4>;
214 clocks = <&apb1>;
215 clock-output-names = "apb1_i2c0", "apb1_i2c1",
216 "apb1_i2c2", "apb1_can", "apb1_scr",
217 "apb1_ps20", "apb1_ps21", "apb1_uart0",
218 "apb1_uart1", "apb1_uart2", "apb1_uart3",
219 "apb1_uart4", "apb1_uart5", "apb1_uart6",
220 "apb1_uart7";
221 };
4b756ffb
EL		 222
223 nand_clk: clk@01c20080 {
224 #clock-cells = <0>;
bf6534a1 225 compatible = "allwinner,sun4i-a10-mod0-clk";
4b756ffb
EL		 226 reg = <0x01c20080 0x4>;
227 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
228 clock-output-names = "nand";
229 };
230
231 ms_clk: clk@01c20084 {
232 #clock-cells = <0>;
bf6534a1 233 compatible = "allwinner,sun4i-a10-mod0-clk";
4b756ffb
EL		 234 reg = <0x01c20084 0x4>;
235 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
236 clock-output-names = "ms";
237 };
238
239 mmc0_clk: clk@01c20088 {
240 #clock-cells = <0>;
bf6534a1 241 compatible = "allwinner,sun4i-a10-mod0-clk";
4b756ffb
EL		 242 reg = <0x01c20088 0x4>;
243 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
244 clock-output-names = "mmc0";
245 };
246
247 mmc1_clk: clk@01c2008c {
248 #clock-cells = <0>;
bf6534a1 249 compatible = "allwinner,sun4i-a10-mod0-clk";
4b756ffb
EL		 250 reg = <0x01c2008c 0x4>;
251 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
252 clock-output-names = "mmc1";
253 };
254
255 mmc2_clk: clk@01c20090 {
256 #clock-cells = <0>;
bf6534a1 257 compatible = "allwinner,sun4i-a10-mod0-clk";
4b756ffb
EL		 258 reg = <0x01c20090 0x4>;
259 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
260 clock-output-names = "mmc2";
261 };
262
263 mmc3_clk: clk@01c20094 {
264 #clock-cells = <0>;
bf6534a1 265 compatible = "allwinner,sun4i-a10-mod0-clk";
4b756ffb
EL		 266 reg = <0x01c20094 0x4>;
267 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
268 clock-output-names = "mmc3";
269 };
270
271 ts_clk: clk@01c20098 {
272 #clock-cells = <0>;
bf6534a1 273 compatible = "allwinner,sun4i-a10-mod0-clk";
4b756ffb
EL		 274 reg = <0x01c20098 0x4>;
275 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
276 clock-output-names = "ts";
277 };
278
279 ss_clk: clk@01c2009c {
280 #clock-cells = <0>;
bf6534a1 281 compatible = "allwinner,sun4i-a10-mod0-clk";
4b756ffb
EL		 282 reg = <0x01c2009c 0x4>;
283 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
284 clock-output-names = "ss";
285 };
286
287 spi0_clk: clk@01c200a0 {
288 #clock-cells = <0>;
bf6534a1 289 compatible = "allwinner,sun4i-a10-mod0-clk";
4b756ffb
EL		 290 reg = <0x01c200a0 0x4>;
291 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
292 clock-output-names = "spi0";
293 };
294
295 spi1_clk: clk@01c200a4 {
296 #clock-cells = <0>;
bf6534a1 297 compatible = "allwinner,sun4i-a10-mod0-clk";
4b756ffb
EL		 298 reg = <0x01c200a4 0x4>;
299 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
300 clock-output-names = "spi1";
301 };
302
303 spi2_clk: clk@01c200a8 {
304 #clock-cells = <0>;
bf6534a1 305 compatible = "allwinner,sun4i-a10-mod0-clk";
4b756ffb
EL		 306 reg = <0x01c200a8 0x4>;
307 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
308 clock-output-names = "spi2";
309 };
310
311 pata_clk: clk@01c200ac {
312 #clock-cells = <0>;
bf6534a1 313 compatible = "allwinner,sun4i-a10-mod0-clk";
4b756ffb
EL		 314 reg = <0x01c200ac 0x4>;
315 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
316 clock-output-names = "pata";
317 };
318
319 ir0_clk: clk@01c200b0 {
320 #clock-cells = <0>;
bf6534a1 321 compatible = "allwinner,sun4i-a10-mod0-clk";
4b756ffb
EL		 322 reg = <0x01c200b0 0x4>;
323 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
324 clock-output-names = "ir0";
325 };
326
327 ir1_clk: clk@01c200b4 {
328 #clock-cells = <0>;
bf6534a1 329 compatible = "allwinner,sun4i-a10-mod0-clk";
4b756ffb
EL		 330 reg = <0x01c200b4 0x4>;
331 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
332 clock-output-names = "ir1";
333 };
334
0076c8bd
RB		 335 usb_clk: clk@01c200cc {
336 #clock-cells = <1>;
337 #reset-cells = <1>;
338 compatible = "allwinner,sun4i-a10-usb-clk";
339 reg = <0x01c200cc 0x4>;
340 clocks = <&pll6 1>;
341 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
342 };
343
4b756ffb
EL		 344 spi3_clk: clk@01c200d4 {
345 #clock-cells = <0>;
bf6534a1 346 compatible = "allwinner,sun4i-a10-mod0-clk";
4b756ffb
EL		 347 reg = <0x01c200d4 0x4>;
348 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
349 clock-output-names = "spi3";
350 };
69144e3b
MR		 351 };
352
b74aec1a 353 soc@01c00000 {
69144e3b
MR		 354 compatible = "simple-bus";
355 #address-cells = <1>;
356 #size-cells = <1>;
69144e3b
MR		 357 ranges;
358
1324f532
EL		 359 dma: dma-controller@01c02000 {
360 compatible = "allwinner,sun4i-a10-dma";
361 reg = <0x01c02000 0x1000>;
362 interrupts = <27>;
363 clocks = <&ahb_gates 6>;
364 #dma-cells = <2>;
365 };
366
65918e26
MR		 367 spi0: spi@01c05000 {
368 compatible = "allwinner,sun4i-a10-spi";
369 reg = <0x01c05000 0x1000>;
370 interrupts = <10>;
371 clocks = <&ahb_gates 20>, <&spi0_clk>;
372 clock-names = "ahb", "mod";
1f9f6a78
MR		 373 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
374 <&dma SUN4I_DMA_DEDICATED 26>;
4192ff81 375 dma-names = "rx", "tx";
65918e26
MR		 376 status = "disabled";
377 #address-cells = <1>;
378 #size-cells = <0>;
379 };
380
381 spi1: spi@01c06000 {
382 compatible = "allwinner,sun4i-a10-spi";
383 reg = <0x01c06000 0x1000>;
384 interrupts = <11>;
385 clocks = <&ahb_gates 21>, <&spi1_clk>;
386 clock-names = "ahb", "mod";
1f9f6a78
MR		 387 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
388 <&dma SUN4I_DMA_DEDICATED 8>;
4192ff81 389 dma-names = "rx", "tx";
65918e26
MR		 390 status = "disabled";
391 #address-cells = <1>;
392 #size-cells = <0>;
393 };
394
e38afcb3 395 emac: ethernet@01c0b000 {
1c70e099 396 compatible = "allwinner,sun4i-a10-emac";
e38afcb3
MR		 397 reg = <0x01c0b000 0x1000>;
398 interrupts = <55>;
399 clocks = <&ahb_gates 17>;
400 status = "disabled";
401 };
402
403 mdio@01c0b080 {
1c70e099 404 compatible = "allwinner,sun4i-a10-mdio";
e38afcb3
MR		 405 reg = <0x01c0b080 0x14>;
406 status = "disabled";
407 #address-cells = <1>;
408 #size-cells = <0>;
409 };
410
b258b369
DL		 411 mmc0: mmc@01c0f000 {
412 compatible = "allwinner,sun4i-a10-mmc";
413 reg = <0x01c0f000 0x1000>;
414 clocks = <&ahb_gates 8>, <&mmc0_clk>;
415 clock-names = "ahb", "mmc";
416 interrupts = <32>;
417 status = "disabled";
418 };
419
420 mmc1: mmc@01c10000 {
421 compatible = "allwinner,sun4i-a10-mmc";
422 reg = <0x01c10000 0x1000>;
423 clocks = <&ahb_gates 9>, <&mmc1_clk>;
424 clock-names = "ahb", "mmc";
425 interrupts = <33>;
426 status = "disabled";
427 };
428
429 mmc2: mmc@01c11000 {
430 compatible = "allwinner,sun4i-a10-mmc";
431 reg = <0x01c11000 0x1000>;
432 clocks = <&ahb_gates 10>, <&mmc2_clk>;
433 clock-names = "ahb", "mmc";
434 interrupts = <34>;
435 status = "disabled";
436 };
437
438 mmc3: mmc@01c12000 {
439 compatible = "allwinner,sun4i-a10-mmc";
440 reg = <0x01c12000 0x1000>;
441 clocks = <&ahb_gates 11>, <&mmc3_clk>;
442 clock-names = "ahb", "mmc";
443 interrupts = <35>;
444 status = "disabled";
445 };
446
6ab1ce24
RB		 447 usbphy: phy@01c13400 {
448 #phy-cells = <1>;
449 compatible = "allwinner,sun4i-a10-usb-phy";
450 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
451 reg-names = "phy_ctrl", "pmu1", "pmu2";
452 clocks = <&usb_clk 8>;
453 clock-names = "usb_phy";
4dba4185
CYT		 454 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
455 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
6ab1ce24
RB		 456 status = "disabled";
457 };
458
459 ehci0: usb@01c14000 {
460 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
461 reg = <0x01c14000 0x100>;
462 interrupts = <39>;
463 clocks = <&ahb_gates 1>;
464 phys = <&usbphy 1>;
465 phy-names = "usb";
466 status = "disabled";
467 };
468
469 ohci0: usb@01c14400 {
470 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
471 reg = <0x01c14400 0x100>;
472 interrupts = <64>;
473 clocks = <&usb_clk 6>, <&ahb_gates 2>;
474 phys = <&usbphy 1>;
475 phy-names = "usb";
476 status = "disabled";
477 };
478
65918e26
MR		 479 spi2: spi@01c17000 {
480 compatible = "allwinner,sun4i-a10-spi";
481 reg = <0x01c17000 0x1000>;
482 interrupts = <12>;
483 clocks = <&ahb_gates 22>, <&spi2_clk>;
484 clock-names = "ahb", "mod";
1f9f6a78
MR		 485 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
486 <&dma SUN4I_DMA_DEDICATED 28>;
4192ff81 487 dma-names = "rx", "tx";
65918e26
MR		 488 status = "disabled";
489 #address-cells = <1>;
490 #size-cells = <0>;
491 };
492
248bd1e2
OS		 493 ahci: sata@01c18000 {
494 compatible = "allwinner,sun4i-a10-ahci";
495 reg = <0x01c18000 0x1000>;
496 interrupts = <56>;
497 clocks = <&pll6 0>, <&ahb_gates 25>;
498 status = "disabled";
499 };
500
6ab1ce24
RB		 501 ehci1: usb@01c1c000 {
502 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
503 reg = <0x01c1c000 0x100>;
504 interrupts = <40>;
505 clocks = <&ahb_gates 3>;
506 phys = <&usbphy 2>;
507 phy-names = "usb";
508 status = "disabled";
509 };
510
511 ohci1: usb@01c1c400 {
512 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
513 reg = <0x01c1c400 0x100>;
514 interrupts = <65>;
515 clocks = <&usb_clk 7>, <&ahb_gates 4>;
516 phys = <&usbphy 2>;
517 phy-names = "usb";
518 status = "disabled";
519 };
520
65918e26
MR		 521 spi3: spi@01c1f000 {
522 compatible = "allwinner,sun4i-a10-spi";
523 reg = <0x01c1f000 0x1000>;
524 interrupts = <50>;
525 clocks = <&ahb_gates 23>, <&spi3_clk>;
526 clock-names = "ahb", "mod";
1f9f6a78
MR		 527 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
528 <&dma SUN4I_DMA_DEDICATED 30>;
4192ff81 529 dma-names = "rx", "tx";
65918e26
MR		 530 status = "disabled";
531 #address-cells = <1>;
532 #size-cells = <0>;
533 };
534
69144e3b 535 intc: interrupt-controller@01c20400 {
09504a7d 536 compatible = "allwinner,sun4i-a10-ic";
69144e3b
MR		 537 reg = <0x01c20400 0x400>;
538 interrupt-controller;
539 #interrupt-cells = <1>;
540 };
541
e10911e1 542 pio: pinctrl@01c20800 {
874b4e45
MR		 543 compatible = "allwinner,sun4i-a10-pinctrl";
544 reg = <0x01c20800 0x400>;
39138bc6 545 interrupts = <28>;
36386d6e 546 clocks = <&apb0_gates 5>;
e10911e1 547 gpio-controller;
39138bc6 548 interrupt-controller;
7d4ff96d 549 #interrupt-cells = <2>;
874b4e45 550 #size-cells = <0>;
e10911e1 551 #gpio-cells = <3>;
581981be 552
1d5726e9
AB		 553 pwm0_pins_a: pwm0@0 {
554 allwinner,pins = "PB2";
555 allwinner,function = "pwm";
092a0c3b
MR		 556 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
557 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1d5726e9
AB		 558 };
559
560 pwm1_pins_a: pwm1@0 {
561 allwinner,pins = "PI3";
562 allwinner,function = "pwm";
092a0c3b
MR		 563 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
564 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1d5726e9
AB		 565 };
566
581981be
MR		 567 uart0_pins_a: uart0@0 {
568 allwinner,pins = "PB22", "PB23";
569 allwinner,function = "uart0";
092a0c3b
MR		 570 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
571 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
581981be
MR		 572 };
573
574 uart0_pins_b: uart0@1 {
575 allwinner,pins = "PF2", "PF4";
576 allwinner,function = "uart0";
092a0c3b
MR		 577 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
578 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
581981be
MR		 579 };
580
581 uart1_pins_a: uart1@0 {
582 allwinner,pins = "PA10", "PA11";
583 allwinner,function = "uart1";
092a0c3b
MR		 584 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
585 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
581981be 586 };
27cce4ff
MR		 587
588 i2c0_pins_a: i2c0@0 {
589 allwinner,pins = "PB0", "PB1";
590 allwinner,function = "i2c0";
092a0c3b
MR		 591 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
592 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
27cce4ff
MR		 593 };
594
595 i2c1_pins_a: i2c1@0 {
596 allwinner,pins = "PB18", "PB19";
597 allwinner,function = "i2c1";
092a0c3b
MR		 598 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
599 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
27cce4ff
MR		 600 };
601
602 i2c2_pins_a: i2c2@0 {
603 allwinner,pins = "PB20", "PB21";
604 allwinner,function = "i2c2";
092a0c3b
MR		 605 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
606 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
27cce4ff 607 };
496322bc 608
b21da664
MR		 609 emac_pins_a: emac0@0 {
610 allwinner,pins = "PA0", "PA1", "PA2",
611 "PA3", "PA4", "PA5", "PA6",
612 "PA7", "PA8", "PA9", "PA10",
613 "PA11", "PA12", "PA13", "PA14",
614 "PA15", "PA16";
615 allwinner,function = "emac";
092a0c3b
MR		 616 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
617 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
b21da664 618 };
b5f86a3a
HG		 619
620 mmc0_pins_a: mmc0@0 {
621 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
622 allwinner,function = "mmc0";
092a0c3b
MR		 623 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
624 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
b5f86a3a
HG		 625 };
626
627 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
628 allwinner,pins = "PH1";
629 allwinner,function = "gpio_in";
092a0c3b
MR		 630 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
631 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
b5f86a3a 632 };
a4e1099a
HG		 633
634 ir0_pins_a: ir0@0 {
635 allwinner,pins = "PB3","PB4";
636 allwinner,function = "ir0";
092a0c3b
MR		 637 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
638 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
a4e1099a
HG		 639 };
640
641 ir1_pins_a: ir1@0 {
642 allwinner,pins = "PB22","PB23";
643 allwinner,function = "ir1";
092a0c3b
MR		 644 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
645 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
a4e1099a 646 };
ec66d0bb
AG		 647
648 spi0_pins_a: spi0@0 {
649 allwinner,pins = "PI10", "PI11", "PI12", "PI13";
650 allwinner,function = "spi0";
092a0c3b
MR		 651 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
652 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
ec66d0bb
AG		 653 };
654
655 spi1_pins_a: spi1@0 {
656 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
657 allwinner,function = "spi1";
092a0c3b
MR		 658 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
659 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
ec66d0bb
AG		 660 };
661
662 spi2_pins_a: spi2@0 {
663 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
664 allwinner,function = "spi2";
092a0c3b
MR		 665 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
666 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
ec66d0bb
AG		 667 };
668
669 spi2_pins_b: spi2@1 {
670 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
671 allwinner,function = "spi2";
092a0c3b
MR		 672 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
673 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
ec66d0bb 674 };
874b4e45 675 };
89b3c99f 676
69144e3b 677 timer@01c20c00 {
b4f26440 678 compatible = "allwinner,sun4i-a10-timer";
69144e3b
MR		 679 reg = <0x01c20c00 0x90>;
680 interrupts = <22>;
681 clocks = <&osc24M>;
682 };
683
684 wdt: watchdog@01c20c90 {
ca5d04d9 685 compatible = "allwinner,sun4i-a10-wdt";
69144e3b
MR		 686 reg = <0x01c20c90 0x10>;
687 };
688
b5d905c7 689 rtc: rtc@01c20d00 {
5fc4bc89 690 compatible = "allwinner,sun4i-a10-rtc";
b5d905c7
CC		 691 reg = <0x01c20d00 0x20>;
692 interrupts = <24>;
693 };
694
4b57a395
AB		 695 pwm: pwm@01c20e00 {
696 compatible = "allwinner,sun4i-a10-pwm";
697 reg = <0x01c20e00 0xc>;
698 clocks = <&osc24M>;
699 #pwm-cells = <3>;
700 status = "disabled";
701 };
702
a4e1099a
HG		 703 ir0: ir@01c21800 {
704 compatible = "allwinner,sun4i-a10-ir";
705 clocks = <&apb0_gates 6>, <&ir0_clk>;
706 clock-names = "apb", "ir";
707 interrupts = <5>;
708 reg = <0x01c21800 0x40>;
709 status = "disabled";
710 };
711
712 ir1: ir@01c21c00 {
713 compatible = "allwinner,sun4i-a10-ir";
714 clocks = <&apb0_gates 7>, <&ir1_clk>;
715 clock-names = "apb", "ir";
716 interrupts = <6>;
717 reg = <0x01c21c00 0x40>;
718 status = "disabled";
719 };
720
b0512e15
HG		 721 lradc: lradc@01c22800 {
722 compatible = "allwinner,sun4i-a10-lradc-keys";
723 reg = <0x01c22800 0x100>;
724 interrupts = <31>;
725 status = "disabled";
726 };
727
2bad969f 728 sid: eeprom@01c23800 {
043d56ee 729 compatible = "allwinner,sun4i-a10-sid";
2bad969f
OS		 730 reg = <0x01c23800 0x10>;
731 };
732
57c8839c 733 rtp: rtp@01c25000 {
40dd8f3b 734 compatible = "allwinner,sun4i-a10-ts";
57c8839c
HG		 735 reg = <0x01c25000 0x100>;
736 interrupts = <29>;
737 };
738
89b3c99f
MR		 739 uart0: serial@01c28000 {
740 compatible = "snps,dw-apb-uart";
741 reg = <0x01c28000 0x400>;
742 interrupts = <1>;
743 reg-shift = <2>;
744 reg-io-width = <4>;
9ff49ec7 745 clocks = <&apb1_gates 16>;
89b3c99f
MR		 746 status = "disabled";
747 };
76f14d0a 748
69144e3b
MR		 749 uart1: serial@01c28400 {
750 compatible = "snps,dw-apb-uart";
751 reg = <0x01c28400 0x400>;
752 interrupts = <2>;
753 reg-shift = <2>;
754 reg-io-width = <4>;
755 clocks = <&apb1_gates 17>;
756 status = "disabled";
757 };
758
76f14d0a
MR		 759 uart2: serial@01c28800 {
760 compatible = "snps,dw-apb-uart";
761 reg = <0x01c28800 0x400>;
762 interrupts = <3>;
763 reg-shift = <2>;
764 reg-io-width = <4>;
9ff49ec7 765 clocks = <&apb1_gates 18>;
76f14d0a
MR		 766 status = "disabled";
767 };
768
69144e3b
MR		 769 uart3: serial@01c28c00 {
770 compatible = "snps,dw-apb-uart";
771 reg = <0x01c28c00 0x400>;
772 interrupts = <4>;
773 reg-shift = <2>;
774 reg-io-width = <4>;
775 clocks = <&apb1_gates 19>;
776 status = "disabled";
777 };
778
76f14d0a
MR		 779 uart4: serial@01c29000 {
780 compatible = "snps,dw-apb-uart";
781 reg = <0x01c29000 0x400>;
782 interrupts = <17>;
783 reg-shift = <2>;
784 reg-io-width = <4>;
9ff49ec7 785 clocks = <&apb1_gates 20>;
76f14d0a
MR		 786 status = "disabled";
787 };
788
789 uart5: serial@01c29400 {
790 compatible = "snps,dw-apb-uart";
791 reg = <0x01c29400 0x400>;
792 interrupts = <18>;
793 reg-shift = <2>;
794 reg-io-width = <4>;
9ff49ec7 795 clocks = <&apb1_gates 21>;
76f14d0a
MR		 796 status = "disabled";
797 };
798
799 uart6: serial@01c29800 {
800 compatible = "snps,dw-apb-uart";
801 reg = <0x01c29800 0x400>;
802 interrupts = <19>;
803 reg-shift = <2>;
804 reg-io-width = <4>;
9ff49ec7 805 clocks = <&apb1_gates 22>;
76f14d0a
MR		 806 status = "disabled";
807 };
808
809 uart7: serial@01c29c00 {
810 compatible = "snps,dw-apb-uart";
811 reg = <0x01c29c00 0x400>;
812 interrupts = <20>;
813 reg-shift = <2>;
814 reg-io-width = <4>;
9ff49ec7 815 clocks = <&apb1_gates 23>;
76f14d0a
MR		 816 status = "disabled";
817 };
f1741fda
MR		 818
819 i2c0: i2c@01c2ac00 {
d275545e 820 compatible = "allwinner,sun4i-a10-i2c";
f1741fda
MR		 821 reg = <0x01c2ac00 0x400>;
822 interrupts = <7>;
823 clocks = <&apb1_gates 0>;
f1741fda 824 status = "disabled";
60bbe316
HG		 825 #address-cells = <1>;
826 #size-cells = <0>;
f1741fda
MR		 827 };
828
829 i2c1: i2c@01c2b000 {
d275545e 830 compatible = "allwinner,sun4i-a10-i2c";
f1741fda
MR		 831 reg = <0x01c2b000 0x400>;
832 interrupts = <8>;
833 clocks = <&apb1_gates 1>;
f1741fda 834 status = "disabled";
60bbe316
HG		 835 #address-cells = <1>;
836 #size-cells = <0>;
f1741fda
MR		 837 };
838
839 i2c2: i2c@01c2b400 {
d275545e 840 compatible = "allwinner,sun4i-a10-i2c";
f1741fda
MR		 841 reg = <0x01c2b400 0x400>;
842 interrupts = <9>;
843 clocks = <&apb1_gates 2>;
f1741fda 844 status = "disabled";
60bbe316
HG		 845 #address-cells = <1>;
846 #size-cells = <0>;
f1741fda 847 };
874b4e45 848 };
7423d2d8 849};
Ubuntu Eoan Linux kernel mirror