[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / sun4i-a10.dtsi

/*
 * Copyright 2012 Stefan Roese
 * Stefan Roese <sr@denx.de>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "skeleton.dtsi"

/ {
	interrupt-parent = <&intc>;

	cpus {
		cpu@0 {
			compatible = "arm,cortex-a8";
		};
	};

	memory {
		reg = <0x40000000 0x80000000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/*
		 * This is a dummy clock, to be used as placeholder on
		 * other mux clocks when a specific parent clock is not
		 * yet implemented. It should be dropped when the driver
		 * is complete.
		 */
		dummy: dummy {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		osc24M_fixed: osc24M_fixed {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};

		osc24M: osc24M@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-osc-clk";
			reg = <0x01c20050 0x4>;
			clocks = <&osc24M_fixed>;
		};

		osc32k: osc32k {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		pll1: pll1@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
		};

		/* dummy is 200M */
		cpu: cpu@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-cpu-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
		};

		axi: axi@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-axi-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&cpu>;
		};

		axi_gates: axi_gates@01c2005c {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-axi-gates-clk";
			reg = <0x01c2005c 0x4>;
			clocks = <&axi>;
			clock-output-names = "axi_dram";
		};

		ahb: ahb@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-ahb-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&axi>;
		};

		ahb_gates: ahb_gates@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-ahb-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb>;
			clock-output-names = "ahb_usb0", "ahb_ehci0",
				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
				"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
				"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
				"ahb_sdram", "ahb_ace",	"ahb_emac", "ahb_ts",
				"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
				"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
				"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
				"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
				"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
				"ahb_de_fe1", "ahb_mp", "ahb_mali400";
		};

		apb0: apb0@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb>;
		};

		apb0_gates: apb0_gates@01c20068 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-apb0-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb0>;
			clock-output-names = "apb0_codec", "apb0_spdif",
				"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
				"apb0_ir1", "apb0_keypad";
		};

		/* dummy is pll62 */
		apb1_mux: apb1_mux@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb1-mux-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc24M>, <&dummy>, <&osc32k>;
		};

		apb1: apb1@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb1-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&apb1_mux>;
		};

		apb1_gates: apb1_gates@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-apb1-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb1>;
			clock-output-names = "apb1_i2c0", "apb1_i2c1",
				"apb1_i2c2", "apb1_can", "apb1_scr",
				"apb1_ps20", "apb1_ps21", "apb1_uart0",
				"apb1_uart1", "apb1_uart2", "apb1_uart3",
				"apb1_uart4", "apb1_uart5", "apb1_uart6",
				"apb1_uart7";
		};
	};

	soc@01c20000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x01c20000 0x300000>;
		ranges;

		intc: interrupt-controller@01c20400 {
			compatible = "allwinner,sunxi-ic";
			reg = <0x01c20400 0x400>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun4i-a10-pinctrl";
			reg = <0x01c20800 0x400>;
			clocks = <&apb0_gates 5>;
			gpio-controller;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PB22", "PB23";
				allwinner,function = "uart0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			uart0_pins_b: uart0@1 {
				allwinner,pins = "PF2", "PF4";
				allwinner,function = "uart0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			uart1_pins_a: uart1@0 {
				allwinner,pins = "PA10", "PA11";
				allwinner,function = "uart1";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-timer";
			reg = <0x01c20c00 0x90>;
			interrupts = <22>;
			clocks = <&osc24M>;
		};

		wdt: watchdog@01c20c90 {
			compatible = "allwinner,sunxi-wdt";
			reg = <0x01c20c90 0x10>;
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 16>;
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <2>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 17>;
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <3>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 18>;
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 19>;
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <17>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 20>;
			status = "disabled";
		};

		uart5: serial@01c29400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29400 0x400>;
			interrupts = <18>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 21>;
			status = "disabled";
		};

		uart6: serial@01c29800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29800 0x400>;
			interrupts = <19>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 22>;
			status = "disabled";
		};

		uart7: serial@01c29c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29c00 0x400>;
			interrupts = <20>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 23>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
7423d2d8 SR	1	/*
	2	* Copyright 2012 Stefan Roese
	3	* Stefan Roese <sr@denx.de>
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
69144e3b	13	/include/ "skeleton.dtsi"
7423d2d8 SR	14
7423d2d8 SR	15	/ {
69144e3b MR	16	interrupt-parent = <&intc>;
	17
	18	cpus {
	19	cpu@0 {
	20	compatible = "arm,cortex-a8";
	21	};
	22	};
	23
7423d2d8 SR	24	memory {
	25	reg = <0x40000000 0x80000000>;
	26	};
874b4e45	27
69144e3b MR	28	clocks {
	29	#address-cells = <1>;
	30	#size-cells = <1>;
	31	ranges;
	32
	33	/*
	34	* This is a dummy clock, to be used as placeholder on
	35	* other mux clocks when a specific parent clock is not
	36	* yet implemented. It should be dropped when the driver
	37	* is complete.
	38	*/
	39	dummy: dummy {
	40	#clock-cells = <0>;
	41	compatible = "fixed-clock";
	42	clock-frequency = <0>;
	43	};
	44
	45	osc24M_fixed: osc24M_fixed {
	46	#clock-cells = <0>;
	47	compatible = "fixed-clock";
	48	clock-frequency = <24000000>;
	49	};
	50
	51	osc24M: osc24M@01c20050 {
	52	#clock-cells = <0>;
	53	compatible = "allwinner,sun4i-osc-clk";
	54	reg = <0x01c20050 0x4>;
	55	clocks = <&osc24M_fixed>;
	56	};
	57
	58	osc32k: osc32k {
	59	#clock-cells = <0>;
	60	compatible = "fixed-clock";
	61	clock-frequency = <32768>;
	62	};
	63
	64	pll1: pll1@01c20000 {
	65	#clock-cells = <0>;
	66	compatible = "allwinner,sun4i-pll1-clk";
	67	reg = <0x01c20000 0x4>;
	68	clocks = <&osc24M>;
	69	};
	70
	71	/* dummy is 200M */
	72	cpu: cpu@01c20054 {
	73	#clock-cells = <0>;
	74	compatible = "allwinner,sun4i-cpu-clk";
	75	reg = <0x01c20054 0x4>;
	76	clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
	77	};
	78
	79	axi: axi@01c20054 {
	80	#clock-cells = <0>;
	81	compatible = "allwinner,sun4i-axi-clk";
	82	reg = <0x01c20054 0x4>;
	83	clocks = <&cpu>;
	84	};
	85
	86	axi_gates: axi_gates@01c2005c {
	87	#clock-cells = <1>;
	88	compatible = "allwinner,sun4i-axi-gates-clk";
	89	reg = <0x01c2005c 0x4>;
	90	clocks = <&axi>;
	91	clock-output-names = "axi_dram";
92	};
93
94	ahb: ahb@01c20054 {
95	#clock-cells = <0>;
96	compatible = "allwinner,sun4i-ahb-clk";
97	reg = <0x01c20054 0x4>;
98	clocks = <&axi>;
99	};
100
101	ahb_gates: ahb_gates@01c20060 {
102	#clock-cells = <1>;
103	compatible = "allwinner,sun4i-ahb-gates-clk";
104	reg = <0x01c20060 0x8>;
105	clocks = <&ahb>;
106	clock-output-names = "ahb_usb0", "ahb_ehci0",
107	"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
108	"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
109	"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
110	"ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
111	"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
112	"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
113	"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
114	"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
115	"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
116	"ahb_de_fe1", "ahb_mp", "ahb_mali400";
117	};
118
119	apb0: apb0@01c20054 {
120	#clock-cells = <0>;
121	compatible = "allwinner,sun4i-apb0-clk";
122	reg = <0x01c20054 0x4>;
123	clocks = <&ahb>;
124	};
125
126	apb0_gates: apb0_gates@01c20068 {
127	#clock-cells = <1>;
128	compatible = "allwinner,sun4i-apb0-gates-clk";
129	reg = <0x01c20068 0x4>;
130	clocks = <&apb0>;
131	clock-output-names = "apb0_codec", "apb0_spdif",
132	"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
133	"apb0_ir1", "apb0_keypad";
134	};
135
136	/* dummy is pll62 */
137	apb1_mux: apb1_mux@01c20058 {
138	#clock-cells = <0>;
139	compatible = "allwinner,sun4i-apb1-mux-clk";
140	reg = <0x01c20058 0x4>;
141	clocks = <&osc24M>, <&dummy>, <&osc32k>;
142	};
143
144	apb1: apb1@01c20058 {
145	#clock-cells = <0>;
146	compatible = "allwinner,sun4i-apb1-clk";
147	reg = <0x01c20058 0x4>;
148	clocks = <&apb1_mux>;
149	};
150
151	apb1_gates: apb1_gates@01c2006c {
152	#clock-cells = <1>;
153	compatible = "allwinner,sun4i-apb1-gates-clk";
154	reg = <0x01c2006c 0x4>;
155	clocks = <&apb1>;
156	clock-output-names = "apb1_i2c0", "apb1_i2c1",
157	"apb1_i2c2", "apb1_can", "apb1_scr",
158	"apb1_ps20", "apb1_ps21", "apb1_uart0",
159	"apb1_uart1", "apb1_uart2", "apb1_uart3",
160	"apb1_uart4", "apb1_uart5", "apb1_uart6",
161	"apb1_uart7";
162	};
163	};
164
165	soc@01c20000 {
166	compatible = "simple-bus";
167	#address-cells = <1>;
168	#size-cells = <1>;
169	reg = <0x01c20000 0x300000>;
170	ranges;
171
172	intc: interrupt-controller@01c20400 {
173	compatible = "allwinner,sunxi-ic";
174	reg = <0x01c20400 0x400>;
175	interrupt-controller;
176	#interrupt-cells = <1>;
177	};
178
e10911e1	179	pio: pinctrl@01c20800 {
874b4e45 MR	180	compatible = "allwinner,sun4i-a10-pinctrl";
874b4e45 MR	181	reg = <0x01c20800 0x400>;
36386d6e	182	clocks = <&apb0_gates 5>;
e10911e1	183	gpio-controller;
874b4e45 MR	184	#address-cells = <1>;
874b4e45 MR	185	#size-cells = <0>;
e10911e1	186	#gpio-cells = <3>;
581981be MR	187
	188	uart0_pins_a: uart0@0 {
	189	allwinner,pins = "PB22", "PB23";
	190	allwinner,function = "uart0";
	191	allwinner,drive = <0>;
	192	allwinner,pull = <0>;
	193	};
	194
	195	uart0_pins_b: uart0@1 {
	196	allwinner,pins = "PF2", "PF4";
	197	allwinner,function = "uart0";
	198	allwinner,drive = <0>;
	199	allwinner,pull = <0>;
	200	};
	201
	202	uart1_pins_a: uart1@0 {
	203	allwinner,pins = "PA10", "PA11";
	204	allwinner,function = "uart1";
	205	allwinner,drive = <0>;
	206	allwinner,pull = <0>;
	207	};
874b4e45	208	};
89b3c99f	209
69144e3b	210	timer@01c20c00 {
b6e1a53b	211	compatible = "allwinner,sun4i-timer";
69144e3b MR	212	reg = <0x01c20c00 0x90>;
	213	interrupts = <22>;
	214	clocks = <&osc24M>;
	215	};
	216
	217	wdt: watchdog@01c20c90 {
	218	compatible = "allwinner,sunxi-wdt";
	219	reg = <0x01c20c90 0x10>;
	220	};
	221
89b3c99f MR	222	uart0: serial@01c28000 {
	223	compatible = "snps,dw-apb-uart";
	224	reg = <0x01c28000 0x400>;
	225	interrupts = <1>;
	226	reg-shift = <2>;
	227	reg-io-width = <4>;
9ff49ec7	228	clocks = <&apb1_gates 16>;
89b3c99f MR	229	status = "disabled";
89b3c99f MR	230	};
76f14d0a	231
69144e3b MR	232	uart1: serial@01c28400 {
	233	compatible = "snps,dw-apb-uart";
	234	reg = <0x01c28400 0x400>;
	235	interrupts = <2>;
	236	reg-shift = <2>;
	237	reg-io-width = <4>;
	238	clocks = <&apb1_gates 17>;
	239	status = "disabled";
	240	};
	241
76f14d0a MR	242	uart2: serial@01c28800 {
	243	compatible = "snps,dw-apb-uart";
	244	reg = <0x01c28800 0x400>;
	245	interrupts = <3>;
	246	reg-shift = <2>;
	247	reg-io-width = <4>;
9ff49ec7	248	clocks = <&apb1_gates 18>;
76f14d0a MR	249	status = "disabled";
	250	};
	251
69144e3b MR	252	uart3: serial@01c28c00 {
	253	compatible = "snps,dw-apb-uart";
	254	reg = <0x01c28c00 0x400>;
	255	interrupts = <4>;
	256	reg-shift = <2>;
	257	reg-io-width = <4>;
	258	clocks = <&apb1_gates 19>;
	259	status = "disabled";
	260	};
	261
76f14d0a MR	262	uart4: serial@01c29000 {
	263	compatible = "snps,dw-apb-uart";
	264	reg = <0x01c29000 0x400>;
	265	interrupts = <17>;
	266	reg-shift = <2>;
	267	reg-io-width = <4>;
9ff49ec7	268	clocks = <&apb1_gates 20>;
76f14d0a MR	269	status = "disabled";
	270	};
	271
	272	uart5: serial@01c29400 {
	273	compatible = "snps,dw-apb-uart";
	274	reg = <0x01c29400 0x400>;
	275	interrupts = <18>;
	276	reg-shift = <2>;
	277	reg-io-width = <4>;
9ff49ec7	278	clocks = <&apb1_gates 21>;
76f14d0a MR	279	status = "disabled";
	280	};
	281
	282	uart6: serial@01c29800 {
	283	compatible = "snps,dw-apb-uart";
	284	reg = <0x01c29800 0x400>;
	285	interrupts = <19>;
	286	reg-shift = <2>;
	287	reg-io-width = <4>;
9ff49ec7	288	clocks = <&apb1_gates 22>;
76f14d0a MR	289	status = "disabled";
	290	};
	291
	292	uart7: serial@01c29c00 {
	293	compatible = "snps,dw-apb-uart";
	294	reg = <0x01c29c00 0x400>;
	295	interrupts = <20>;
	296	reg-shift = <2>;
	297	reg-io-width = <4>;
9ff49ec7	298	clocks = <&apb1_gates 23>;
76f14d0a MR	299	status = "disabled";
76f14d0a MR	300	};
874b4e45	301	};
7423d2d8	302	};