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Commit | Line | Data |
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7423d2d8 SR |
1 | /* |
2 | * Copyright 2012 Stefan Roese | |
3 | * Stefan Roese <sr@denx.de> | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
71455701 | 13 | #include "skeleton.dtsi" |
7423d2d8 SR |
14 | |
15 | / { | |
69144e3b MR |
16 | interrupt-parent = <&intc>; |
17 | ||
e751cce9 EL |
18 | aliases { |
19 | ethernet0 = &emac; | |
10b302a2 MR |
20 | serial0 = &uart0; |
21 | serial1 = &uart1; | |
143b13d6 MR |
22 | serial2 = &uart2; |
23 | serial3 = &uart3; | |
24 | serial4 = &uart4; | |
25 | serial5 = &uart5; | |
26 | serial6 = &uart6; | |
27 | serial7 = &uart7; | |
e751cce9 EL |
28 | }; |
29 | ||
5790d4ee HG |
30 | chosen { |
31 | #address-cells = <1>; | |
32 | #size-cells = <1>; | |
33 | ranges; | |
34 | ||
a9f8cda3 HG |
35 | framebuffer@0 { |
36 | compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; | |
37 | allwinner,pipeline = "de_be0-lcd0-hdmi"; | |
678e75d3 HG |
38 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, |
39 | <&ahb_gates 44>; | |
5790d4ee HG |
40 | status = "disabled"; |
41 | }; | |
8cedd662 HG |
42 | |
43 | framebuffer@1 { | |
44 | compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; | |
45 | allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; | |
46 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, | |
47 | <&ahb_gates 44>, <&ahb_gates 46>; | |
48 | status = "disabled"; | |
49 | }; | |
5790d4ee HG |
50 | }; |
51 | ||
69144e3b | 52 | cpus { |
8b2efa89 AB |
53 | #address-cells = <1>; |
54 | #size-cells = <0>; | |
69144e3b | 55 | cpu@0 { |
14c44aa5 | 56 | device_type = "cpu"; |
69144e3b | 57 | compatible = "arm,cortex-a8"; |
14c44aa5 | 58 | reg = <0x0>; |
69144e3b MR |
59 | }; |
60 | }; | |
61 | ||
7423d2d8 SR |
62 | memory { |
63 | reg = <0x40000000 0x80000000>; | |
64 | }; | |
874b4e45 | 65 | |
69144e3b MR |
66 | clocks { |
67 | #address-cells = <1>; | |
68 | #size-cells = <1>; | |
69 | ranges; | |
70 | ||
71 | /* | |
72 | * This is a dummy clock, to be used as placeholder on | |
73 | * other mux clocks when a specific parent clock is not | |
74 | * yet implemented. It should be dropped when the driver | |
75 | * is complete. | |
76 | */ | |
77 | dummy: dummy { | |
78 | #clock-cells = <0>; | |
79 | compatible = "fixed-clock"; | |
80 | clock-frequency = <0>; | |
81 | }; | |
82 | ||
dfb12c0c | 83 | osc24M: clk@01c20050 { |
69144e3b | 84 | #clock-cells = <0>; |
bf6534a1 | 85 | compatible = "allwinner,sun4i-a10-osc-clk"; |
69144e3b | 86 | reg = <0x01c20050 0x4>; |
92fd6e06 | 87 | clock-frequency = <24000000>; |
dfb12c0c | 88 | clock-output-names = "osc24M"; |
69144e3b MR |
89 | }; |
90 | ||
dfb12c0c | 91 | osc32k: clk@0 { |
69144e3b MR |
92 | #clock-cells = <0>; |
93 | compatible = "fixed-clock"; | |
94 | clock-frequency = <32768>; | |
dfb12c0c | 95 | clock-output-names = "osc32k"; |
69144e3b MR |
96 | }; |
97 | ||
dfb12c0c | 98 | pll1: clk@01c20000 { |
69144e3b | 99 | #clock-cells = <0>; |
bf6534a1 | 100 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
69144e3b MR |
101 | reg = <0x01c20000 0x4>; |
102 | clocks = <&osc24M>; | |
dfb12c0c | 103 | clock-output-names = "pll1"; |
69144e3b MR |
104 | }; |
105 | ||
dfb12c0c | 106 | pll4: clk@01c20018 { |
ec5589f7 | 107 | #clock-cells = <0>; |
bf6534a1 | 108 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
ec5589f7 EL |
109 | reg = <0x01c20018 0x4>; |
110 | clocks = <&osc24M>; | |
dfb12c0c | 111 | clock-output-names = "pll4"; |
ec5589f7 EL |
112 | }; |
113 | ||
dfb12c0c | 114 | pll5: clk@01c20020 { |
c3e5e66b | 115 | #clock-cells = <1>; |
bf6534a1 | 116 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
c3e5e66b EL |
117 | reg = <0x01c20020 0x4>; |
118 | clocks = <&osc24M>; | |
119 | clock-output-names = "pll5_ddr", "pll5_other"; | |
120 | }; | |
121 | ||
dfb12c0c | 122 | pll6: clk@01c20028 { |
c3e5e66b | 123 | #clock-cells = <1>; |
bf6534a1 | 124 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
c3e5e66b EL |
125 | reg = <0x01c20028 0x4>; |
126 | clocks = <&osc24M>; | |
127 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
128 | }; | |
129 | ||
69144e3b MR |
130 | /* dummy is 200M */ |
131 | cpu: cpu@01c20054 { | |
132 | #clock-cells = <0>; | |
bf6534a1 | 133 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
69144e3b MR |
134 | reg = <0x01c20054 0x4>; |
135 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
dfb12c0c | 136 | clock-output-names = "cpu"; |
69144e3b MR |
137 | }; |
138 | ||
139 | axi: axi@01c20054 { | |
140 | #clock-cells = <0>; | |
bf6534a1 | 141 | compatible = "allwinner,sun4i-a10-axi-clk"; |
69144e3b MR |
142 | reg = <0x01c20054 0x4>; |
143 | clocks = <&cpu>; | |
dfb12c0c | 144 | clock-output-names = "axi"; |
69144e3b MR |
145 | }; |
146 | ||
dfb12c0c | 147 | axi_gates: clk@01c2005c { |
69144e3b | 148 | #clock-cells = <1>; |
bf6534a1 | 149 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
69144e3b MR |
150 | reg = <0x01c2005c 0x4>; |
151 | clocks = <&axi>; | |
152 | clock-output-names = "axi_dram"; | |
153 | }; | |
154 | ||
155 | ahb: ahb@01c20054 { | |
156 | #clock-cells = <0>; | |
bf6534a1 | 157 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
69144e3b MR |
158 | reg = <0x01c20054 0x4>; |
159 | clocks = <&axi>; | |
dfb12c0c | 160 | clock-output-names = "ahb"; |
69144e3b MR |
161 | }; |
162 | ||
dfb12c0c | 163 | ahb_gates: clk@01c20060 { |
69144e3b | 164 | #clock-cells = <1>; |
bf6534a1 | 165 | compatible = "allwinner,sun4i-a10-ahb-gates-clk"; |
69144e3b MR |
166 | reg = <0x01c20060 0x8>; |
167 | clocks = <&ahb>; | |
168 | clock-output-names = "ahb_usb0", "ahb_ehci0", | |
169 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", | |
170 | "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", | |
171 | "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", | |
172 | "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", | |
173 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", | |
174 | "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", | |
175 | "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", | |
176 | "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", | |
177 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
178 | "ahb_de_fe1", "ahb_mp", "ahb_mali400"; | |
179 | }; | |
180 | ||
181 | apb0: apb0@01c20054 { | |
182 | #clock-cells = <0>; | |
bf6534a1 | 183 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
69144e3b MR |
184 | reg = <0x01c20054 0x4>; |
185 | clocks = <&ahb>; | |
dfb12c0c | 186 | clock-output-names = "apb0"; |
69144e3b MR |
187 | }; |
188 | ||
dfb12c0c | 189 | apb0_gates: clk@01c20068 { |
69144e3b | 190 | #clock-cells = <1>; |
bf6534a1 | 191 | compatible = "allwinner,sun4i-a10-apb0-gates-clk"; |
69144e3b MR |
192 | reg = <0x01c20068 0x4>; |
193 | clocks = <&apb0>; | |
194 | clock-output-names = "apb0_codec", "apb0_spdif", | |
195 | "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", | |
196 | "apb0_ir1", "apb0_keypad"; | |
197 | }; | |
198 | ||
acbcc0f0 | 199 | apb1: clk@01c20058 { |
69144e3b | 200 | #clock-cells = <0>; |
bf6534a1 | 201 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
69144e3b | 202 | reg = <0x01c20058 0x4>; |
acbcc0f0 | 203 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
dfb12c0c | 204 | clock-output-names = "apb1"; |
69144e3b MR |
205 | }; |
206 | ||
dfb12c0c | 207 | apb1_gates: clk@01c2006c { |
69144e3b | 208 | #clock-cells = <1>; |
bf6534a1 | 209 | compatible = "allwinner,sun4i-a10-apb1-gates-clk"; |
69144e3b MR |
210 | reg = <0x01c2006c 0x4>; |
211 | clocks = <&apb1>; | |
212 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
213 | "apb1_i2c2", "apb1_can", "apb1_scr", | |
214 | "apb1_ps20", "apb1_ps21", "apb1_uart0", | |
215 | "apb1_uart1", "apb1_uart2", "apb1_uart3", | |
216 | "apb1_uart4", "apb1_uart5", "apb1_uart6", | |
217 | "apb1_uart7"; | |
218 | }; | |
4b756ffb EL |
219 | |
220 | nand_clk: clk@01c20080 { | |
221 | #clock-cells = <0>; | |
bf6534a1 | 222 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
223 | reg = <0x01c20080 0x4>; |
224 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
225 | clock-output-names = "nand"; | |
226 | }; | |
227 | ||
228 | ms_clk: clk@01c20084 { | |
229 | #clock-cells = <0>; | |
bf6534a1 | 230 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
231 | reg = <0x01c20084 0x4>; |
232 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
233 | clock-output-names = "ms"; | |
234 | }; | |
235 | ||
236 | mmc0_clk: clk@01c20088 { | |
237 | #clock-cells = <0>; | |
bf6534a1 | 238 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
239 | reg = <0x01c20088 0x4>; |
240 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
241 | clock-output-names = "mmc0"; | |
242 | }; | |
243 | ||
244 | mmc1_clk: clk@01c2008c { | |
245 | #clock-cells = <0>; | |
bf6534a1 | 246 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
247 | reg = <0x01c2008c 0x4>; |
248 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
249 | clock-output-names = "mmc1"; | |
250 | }; | |
251 | ||
252 | mmc2_clk: clk@01c20090 { | |
253 | #clock-cells = <0>; | |
bf6534a1 | 254 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
255 | reg = <0x01c20090 0x4>; |
256 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
257 | clock-output-names = "mmc2"; | |
258 | }; | |
259 | ||
260 | mmc3_clk: clk@01c20094 { | |
261 | #clock-cells = <0>; | |
bf6534a1 | 262 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
263 | reg = <0x01c20094 0x4>; |
264 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
265 | clock-output-names = "mmc3"; | |
266 | }; | |
267 | ||
268 | ts_clk: clk@01c20098 { | |
269 | #clock-cells = <0>; | |
bf6534a1 | 270 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
271 | reg = <0x01c20098 0x4>; |
272 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
273 | clock-output-names = "ts"; | |
274 | }; | |
275 | ||
276 | ss_clk: clk@01c2009c { | |
277 | #clock-cells = <0>; | |
bf6534a1 | 278 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
279 | reg = <0x01c2009c 0x4>; |
280 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
281 | clock-output-names = "ss"; | |
282 | }; | |
283 | ||
284 | spi0_clk: clk@01c200a0 { | |
285 | #clock-cells = <0>; | |
bf6534a1 | 286 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
287 | reg = <0x01c200a0 0x4>; |
288 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
289 | clock-output-names = "spi0"; | |
290 | }; | |
291 | ||
292 | spi1_clk: clk@01c200a4 { | |
293 | #clock-cells = <0>; | |
bf6534a1 | 294 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
295 | reg = <0x01c200a4 0x4>; |
296 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
297 | clock-output-names = "spi1"; | |
298 | }; | |
299 | ||
300 | spi2_clk: clk@01c200a8 { | |
301 | #clock-cells = <0>; | |
bf6534a1 | 302 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
303 | reg = <0x01c200a8 0x4>; |
304 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
305 | clock-output-names = "spi2"; | |
306 | }; | |
307 | ||
308 | pata_clk: clk@01c200ac { | |
309 | #clock-cells = <0>; | |
bf6534a1 | 310 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
311 | reg = <0x01c200ac 0x4>; |
312 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
313 | clock-output-names = "pata"; | |
314 | }; | |
315 | ||
316 | ir0_clk: clk@01c200b0 { | |
317 | #clock-cells = <0>; | |
bf6534a1 | 318 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
319 | reg = <0x01c200b0 0x4>; |
320 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
321 | clock-output-names = "ir0"; | |
322 | }; | |
323 | ||
324 | ir1_clk: clk@01c200b4 { | |
325 | #clock-cells = <0>; | |
bf6534a1 | 326 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
327 | reg = <0x01c200b4 0x4>; |
328 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
329 | clock-output-names = "ir1"; | |
330 | }; | |
331 | ||
0076c8bd RB |
332 | usb_clk: clk@01c200cc { |
333 | #clock-cells = <1>; | |
334 | #reset-cells = <1>; | |
335 | compatible = "allwinner,sun4i-a10-usb-clk"; | |
336 | reg = <0x01c200cc 0x4>; | |
337 | clocks = <&pll6 1>; | |
338 | clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; | |
339 | }; | |
340 | ||
4b756ffb EL |
341 | spi3_clk: clk@01c200d4 { |
342 | #clock-cells = <0>; | |
bf6534a1 | 343 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
344 | reg = <0x01c200d4 0x4>; |
345 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
346 | clock-output-names = "spi3"; | |
347 | }; | |
69144e3b MR |
348 | }; |
349 | ||
b74aec1a | 350 | soc@01c00000 { |
69144e3b MR |
351 | compatible = "simple-bus"; |
352 | #address-cells = <1>; | |
353 | #size-cells = <1>; | |
69144e3b MR |
354 | ranges; |
355 | ||
1324f532 EL |
356 | dma: dma-controller@01c02000 { |
357 | compatible = "allwinner,sun4i-a10-dma"; | |
358 | reg = <0x01c02000 0x1000>; | |
359 | interrupts = <27>; | |
360 | clocks = <&ahb_gates 6>; | |
361 | #dma-cells = <2>; | |
362 | }; | |
363 | ||
65918e26 MR |
364 | spi0: spi@01c05000 { |
365 | compatible = "allwinner,sun4i-a10-spi"; | |
366 | reg = <0x01c05000 0x1000>; | |
367 | interrupts = <10>; | |
368 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
369 | clock-names = "ahb", "mod"; | |
4192ff81 EL |
370 | dmas = <&dma 1 27>, <&dma 1 26>; |
371 | dma-names = "rx", "tx"; | |
65918e26 MR |
372 | status = "disabled"; |
373 | #address-cells = <1>; | |
374 | #size-cells = <0>; | |
375 | }; | |
376 | ||
377 | spi1: spi@01c06000 { | |
378 | compatible = "allwinner,sun4i-a10-spi"; | |
379 | reg = <0x01c06000 0x1000>; | |
380 | interrupts = <11>; | |
381 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
382 | clock-names = "ahb", "mod"; | |
4192ff81 EL |
383 | dmas = <&dma 1 9>, <&dma 1 8>; |
384 | dma-names = "rx", "tx"; | |
65918e26 MR |
385 | status = "disabled"; |
386 | #address-cells = <1>; | |
387 | #size-cells = <0>; | |
388 | }; | |
389 | ||
e38afcb3 | 390 | emac: ethernet@01c0b000 { |
1c70e099 | 391 | compatible = "allwinner,sun4i-a10-emac"; |
e38afcb3 MR |
392 | reg = <0x01c0b000 0x1000>; |
393 | interrupts = <55>; | |
394 | clocks = <&ahb_gates 17>; | |
395 | status = "disabled"; | |
396 | }; | |
397 | ||
398 | mdio@01c0b080 { | |
1c70e099 | 399 | compatible = "allwinner,sun4i-a10-mdio"; |
e38afcb3 MR |
400 | reg = <0x01c0b080 0x14>; |
401 | status = "disabled"; | |
402 | #address-cells = <1>; | |
403 | #size-cells = <0>; | |
404 | }; | |
405 | ||
b258b369 DL |
406 | mmc0: mmc@01c0f000 { |
407 | compatible = "allwinner,sun4i-a10-mmc"; | |
408 | reg = <0x01c0f000 0x1000>; | |
409 | clocks = <&ahb_gates 8>, <&mmc0_clk>; | |
410 | clock-names = "ahb", "mmc"; | |
411 | interrupts = <32>; | |
412 | status = "disabled"; | |
413 | }; | |
414 | ||
415 | mmc1: mmc@01c10000 { | |
416 | compatible = "allwinner,sun4i-a10-mmc"; | |
417 | reg = <0x01c10000 0x1000>; | |
418 | clocks = <&ahb_gates 9>, <&mmc1_clk>; | |
419 | clock-names = "ahb", "mmc"; | |
420 | interrupts = <33>; | |
421 | status = "disabled"; | |
422 | }; | |
423 | ||
424 | mmc2: mmc@01c11000 { | |
425 | compatible = "allwinner,sun4i-a10-mmc"; | |
426 | reg = <0x01c11000 0x1000>; | |
427 | clocks = <&ahb_gates 10>, <&mmc2_clk>; | |
428 | clock-names = "ahb", "mmc"; | |
429 | interrupts = <34>; | |
430 | status = "disabled"; | |
431 | }; | |
432 | ||
433 | mmc3: mmc@01c12000 { | |
434 | compatible = "allwinner,sun4i-a10-mmc"; | |
435 | reg = <0x01c12000 0x1000>; | |
436 | clocks = <&ahb_gates 11>, <&mmc3_clk>; | |
437 | clock-names = "ahb", "mmc"; | |
438 | interrupts = <35>; | |
439 | status = "disabled"; | |
440 | }; | |
441 | ||
6ab1ce24 RB |
442 | usbphy: phy@01c13400 { |
443 | #phy-cells = <1>; | |
444 | compatible = "allwinner,sun4i-a10-usb-phy"; | |
445 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
446 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
447 | clocks = <&usb_clk 8>; | |
448 | clock-names = "usb_phy"; | |
4dba4185 CYT |
449 | resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; |
450 | reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; | |
6ab1ce24 RB |
451 | status = "disabled"; |
452 | }; | |
453 | ||
454 | ehci0: usb@01c14000 { | |
455 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
456 | reg = <0x01c14000 0x100>; | |
457 | interrupts = <39>; | |
458 | clocks = <&ahb_gates 1>; | |
459 | phys = <&usbphy 1>; | |
460 | phy-names = "usb"; | |
461 | status = "disabled"; | |
462 | }; | |
463 | ||
464 | ohci0: usb@01c14400 { | |
465 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
466 | reg = <0x01c14400 0x100>; | |
467 | interrupts = <64>; | |
468 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
469 | phys = <&usbphy 1>; | |
470 | phy-names = "usb"; | |
471 | status = "disabled"; | |
472 | }; | |
473 | ||
65918e26 MR |
474 | spi2: spi@01c17000 { |
475 | compatible = "allwinner,sun4i-a10-spi"; | |
476 | reg = <0x01c17000 0x1000>; | |
477 | interrupts = <12>; | |
478 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
479 | clock-names = "ahb", "mod"; | |
4192ff81 EL |
480 | dmas = <&dma 1 29>, <&dma 1 28>; |
481 | dma-names = "rx", "tx"; | |
65918e26 MR |
482 | status = "disabled"; |
483 | #address-cells = <1>; | |
484 | #size-cells = <0>; | |
485 | }; | |
486 | ||
248bd1e2 OS |
487 | ahci: sata@01c18000 { |
488 | compatible = "allwinner,sun4i-a10-ahci"; | |
489 | reg = <0x01c18000 0x1000>; | |
490 | interrupts = <56>; | |
491 | clocks = <&pll6 0>, <&ahb_gates 25>; | |
492 | status = "disabled"; | |
493 | }; | |
494 | ||
6ab1ce24 RB |
495 | ehci1: usb@01c1c000 { |
496 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
497 | reg = <0x01c1c000 0x100>; | |
498 | interrupts = <40>; | |
499 | clocks = <&ahb_gates 3>; | |
500 | phys = <&usbphy 2>; | |
501 | phy-names = "usb"; | |
502 | status = "disabled"; | |
503 | }; | |
504 | ||
505 | ohci1: usb@01c1c400 { | |
506 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
507 | reg = <0x01c1c400 0x100>; | |
508 | interrupts = <65>; | |
509 | clocks = <&usb_clk 7>, <&ahb_gates 4>; | |
510 | phys = <&usbphy 2>; | |
511 | phy-names = "usb"; | |
512 | status = "disabled"; | |
513 | }; | |
514 | ||
65918e26 MR |
515 | spi3: spi@01c1f000 { |
516 | compatible = "allwinner,sun4i-a10-spi"; | |
517 | reg = <0x01c1f000 0x1000>; | |
518 | interrupts = <50>; | |
519 | clocks = <&ahb_gates 23>, <&spi3_clk>; | |
520 | clock-names = "ahb", "mod"; | |
4192ff81 EL |
521 | dmas = <&dma 1 31>, <&dma 1 30>; |
522 | dma-names = "rx", "tx"; | |
65918e26 MR |
523 | status = "disabled"; |
524 | #address-cells = <1>; | |
525 | #size-cells = <0>; | |
526 | }; | |
527 | ||
69144e3b | 528 | intc: interrupt-controller@01c20400 { |
09504a7d | 529 | compatible = "allwinner,sun4i-a10-ic"; |
69144e3b MR |
530 | reg = <0x01c20400 0x400>; |
531 | interrupt-controller; | |
532 | #interrupt-cells = <1>; | |
533 | }; | |
534 | ||
e10911e1 | 535 | pio: pinctrl@01c20800 { |
874b4e45 MR |
536 | compatible = "allwinner,sun4i-a10-pinctrl"; |
537 | reg = <0x01c20800 0x400>; | |
39138bc6 | 538 | interrupts = <28>; |
36386d6e | 539 | clocks = <&apb0_gates 5>; |
e10911e1 | 540 | gpio-controller; |
39138bc6 | 541 | interrupt-controller; |
7d4ff96d | 542 | #interrupt-cells = <2>; |
874b4e45 | 543 | #size-cells = <0>; |
e10911e1 | 544 | #gpio-cells = <3>; |
581981be | 545 | |
1d5726e9 AB |
546 | pwm0_pins_a: pwm0@0 { |
547 | allwinner,pins = "PB2"; | |
548 | allwinner,function = "pwm"; | |
549 | allwinner,drive = <0>; | |
550 | allwinner,pull = <0>; | |
551 | }; | |
552 | ||
553 | pwm1_pins_a: pwm1@0 { | |
554 | allwinner,pins = "PI3"; | |
555 | allwinner,function = "pwm"; | |
556 | allwinner,drive = <0>; | |
557 | allwinner,pull = <0>; | |
558 | }; | |
559 | ||
581981be MR |
560 | uart0_pins_a: uart0@0 { |
561 | allwinner,pins = "PB22", "PB23"; | |
562 | allwinner,function = "uart0"; | |
563 | allwinner,drive = <0>; | |
564 | allwinner,pull = <0>; | |
565 | }; | |
566 | ||
567 | uart0_pins_b: uart0@1 { | |
568 | allwinner,pins = "PF2", "PF4"; | |
569 | allwinner,function = "uart0"; | |
570 | allwinner,drive = <0>; | |
571 | allwinner,pull = <0>; | |
572 | }; | |
573 | ||
574 | uart1_pins_a: uart1@0 { | |
575 | allwinner,pins = "PA10", "PA11"; | |
576 | allwinner,function = "uart1"; | |
577 | allwinner,drive = <0>; | |
578 | allwinner,pull = <0>; | |
579 | }; | |
27cce4ff MR |
580 | |
581 | i2c0_pins_a: i2c0@0 { | |
582 | allwinner,pins = "PB0", "PB1"; | |
583 | allwinner,function = "i2c0"; | |
584 | allwinner,drive = <0>; | |
585 | allwinner,pull = <0>; | |
586 | }; | |
587 | ||
588 | i2c1_pins_a: i2c1@0 { | |
589 | allwinner,pins = "PB18", "PB19"; | |
590 | allwinner,function = "i2c1"; | |
591 | allwinner,drive = <0>; | |
592 | allwinner,pull = <0>; | |
593 | }; | |
594 | ||
595 | i2c2_pins_a: i2c2@0 { | |
596 | allwinner,pins = "PB20", "PB21"; | |
597 | allwinner,function = "i2c2"; | |
598 | allwinner,drive = <0>; | |
599 | allwinner,pull = <0>; | |
600 | }; | |
496322bc | 601 | |
b21da664 MR |
602 | emac_pins_a: emac0@0 { |
603 | allwinner,pins = "PA0", "PA1", "PA2", | |
604 | "PA3", "PA4", "PA5", "PA6", | |
605 | "PA7", "PA8", "PA9", "PA10", | |
606 | "PA11", "PA12", "PA13", "PA14", | |
607 | "PA15", "PA16"; | |
608 | allwinner,function = "emac"; | |
609 | allwinner,drive = <0>; | |
610 | allwinner,pull = <0>; | |
611 | }; | |
b5f86a3a HG |
612 | |
613 | mmc0_pins_a: mmc0@0 { | |
614 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | |
615 | allwinner,function = "mmc0"; | |
616 | allwinner,drive = <2>; | |
617 | allwinner,pull = <0>; | |
618 | }; | |
619 | ||
620 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { | |
621 | allwinner,pins = "PH1"; | |
622 | allwinner,function = "gpio_in"; | |
623 | allwinner,drive = <0>; | |
624 | allwinner,pull = <1>; | |
625 | }; | |
a4e1099a HG |
626 | |
627 | ir0_pins_a: ir0@0 { | |
628 | allwinner,pins = "PB3","PB4"; | |
629 | allwinner,function = "ir0"; | |
630 | allwinner,drive = <0>; | |
631 | allwinner,pull = <0>; | |
632 | }; | |
633 | ||
634 | ir1_pins_a: ir1@0 { | |
635 | allwinner,pins = "PB22","PB23"; | |
636 | allwinner,function = "ir1"; | |
637 | allwinner,drive = <0>; | |
638 | allwinner,pull = <0>; | |
639 | }; | |
ec66d0bb AG |
640 | |
641 | spi0_pins_a: spi0@0 { | |
642 | allwinner,pins = "PI10", "PI11", "PI12", "PI13"; | |
643 | allwinner,function = "spi0"; | |
644 | allwinner,drive = <0>; | |
645 | allwinner,pull = <0>; | |
646 | }; | |
647 | ||
648 | spi1_pins_a: spi1@0 { | |
649 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; | |
650 | allwinner,function = "spi1"; | |
651 | allwinner,drive = <0>; | |
652 | allwinner,pull = <0>; | |
653 | }; | |
654 | ||
655 | spi2_pins_a: spi2@0 { | |
656 | allwinner,pins = "PB14", "PB15", "PB16", "PB17"; | |
657 | allwinner,function = "spi2"; | |
658 | allwinner,drive = <0>; | |
659 | allwinner,pull = <0>; | |
660 | }; | |
661 | ||
662 | spi2_pins_b: spi2@1 { | |
663 | allwinner,pins = "PC19", "PC20", "PC21", "PC22"; | |
664 | allwinner,function = "spi2"; | |
665 | allwinner,drive = <0>; | |
666 | allwinner,pull = <0>; | |
667 | }; | |
874b4e45 | 668 | }; |
89b3c99f | 669 | |
69144e3b | 670 | timer@01c20c00 { |
b4f26440 | 671 | compatible = "allwinner,sun4i-a10-timer"; |
69144e3b MR |
672 | reg = <0x01c20c00 0x90>; |
673 | interrupts = <22>; | |
674 | clocks = <&osc24M>; | |
675 | }; | |
676 | ||
677 | wdt: watchdog@01c20c90 { | |
ca5d04d9 | 678 | compatible = "allwinner,sun4i-a10-wdt"; |
69144e3b MR |
679 | reg = <0x01c20c90 0x10>; |
680 | }; | |
681 | ||
b5d905c7 | 682 | rtc: rtc@01c20d00 { |
5fc4bc89 | 683 | compatible = "allwinner,sun4i-a10-rtc"; |
b5d905c7 CC |
684 | reg = <0x01c20d00 0x20>; |
685 | interrupts = <24>; | |
686 | }; | |
687 | ||
4b57a395 AB |
688 | pwm: pwm@01c20e00 { |
689 | compatible = "allwinner,sun4i-a10-pwm"; | |
690 | reg = <0x01c20e00 0xc>; | |
691 | clocks = <&osc24M>; | |
692 | #pwm-cells = <3>; | |
693 | status = "disabled"; | |
694 | }; | |
695 | ||
a4e1099a HG |
696 | ir0: ir@01c21800 { |
697 | compatible = "allwinner,sun4i-a10-ir"; | |
698 | clocks = <&apb0_gates 6>, <&ir0_clk>; | |
699 | clock-names = "apb", "ir"; | |
700 | interrupts = <5>; | |
701 | reg = <0x01c21800 0x40>; | |
702 | status = "disabled"; | |
703 | }; | |
704 | ||
705 | ir1: ir@01c21c00 { | |
706 | compatible = "allwinner,sun4i-a10-ir"; | |
707 | clocks = <&apb0_gates 7>, <&ir1_clk>; | |
708 | clock-names = "apb", "ir"; | |
709 | interrupts = <6>; | |
710 | reg = <0x01c21c00 0x40>; | |
711 | status = "disabled"; | |
712 | }; | |
713 | ||
b0512e15 HG |
714 | lradc: lradc@01c22800 { |
715 | compatible = "allwinner,sun4i-a10-lradc-keys"; | |
716 | reg = <0x01c22800 0x100>; | |
717 | interrupts = <31>; | |
718 | status = "disabled"; | |
719 | }; | |
720 | ||
2bad969f | 721 | sid: eeprom@01c23800 { |
043d56ee | 722 | compatible = "allwinner,sun4i-a10-sid"; |
2bad969f OS |
723 | reg = <0x01c23800 0x10>; |
724 | }; | |
725 | ||
57c8839c | 726 | rtp: rtp@01c25000 { |
40dd8f3b | 727 | compatible = "allwinner,sun4i-a10-ts"; |
57c8839c HG |
728 | reg = <0x01c25000 0x100>; |
729 | interrupts = <29>; | |
730 | }; | |
731 | ||
89b3c99f MR |
732 | uart0: serial@01c28000 { |
733 | compatible = "snps,dw-apb-uart"; | |
734 | reg = <0x01c28000 0x400>; | |
735 | interrupts = <1>; | |
736 | reg-shift = <2>; | |
737 | reg-io-width = <4>; | |
9ff49ec7 | 738 | clocks = <&apb1_gates 16>; |
89b3c99f MR |
739 | status = "disabled"; |
740 | }; | |
76f14d0a | 741 | |
69144e3b MR |
742 | uart1: serial@01c28400 { |
743 | compatible = "snps,dw-apb-uart"; | |
744 | reg = <0x01c28400 0x400>; | |
745 | interrupts = <2>; | |
746 | reg-shift = <2>; | |
747 | reg-io-width = <4>; | |
748 | clocks = <&apb1_gates 17>; | |
749 | status = "disabled"; | |
750 | }; | |
751 | ||
76f14d0a MR |
752 | uart2: serial@01c28800 { |
753 | compatible = "snps,dw-apb-uart"; | |
754 | reg = <0x01c28800 0x400>; | |
755 | interrupts = <3>; | |
756 | reg-shift = <2>; | |
757 | reg-io-width = <4>; | |
9ff49ec7 | 758 | clocks = <&apb1_gates 18>; |
76f14d0a MR |
759 | status = "disabled"; |
760 | }; | |
761 | ||
69144e3b MR |
762 | uart3: serial@01c28c00 { |
763 | compatible = "snps,dw-apb-uart"; | |
764 | reg = <0x01c28c00 0x400>; | |
765 | interrupts = <4>; | |
766 | reg-shift = <2>; | |
767 | reg-io-width = <4>; | |
768 | clocks = <&apb1_gates 19>; | |
769 | status = "disabled"; | |
770 | }; | |
771 | ||
76f14d0a MR |
772 | uart4: serial@01c29000 { |
773 | compatible = "snps,dw-apb-uart"; | |
774 | reg = <0x01c29000 0x400>; | |
775 | interrupts = <17>; | |
776 | reg-shift = <2>; | |
777 | reg-io-width = <4>; | |
9ff49ec7 | 778 | clocks = <&apb1_gates 20>; |
76f14d0a MR |
779 | status = "disabled"; |
780 | }; | |
781 | ||
782 | uart5: serial@01c29400 { | |
783 | compatible = "snps,dw-apb-uart"; | |
784 | reg = <0x01c29400 0x400>; | |
785 | interrupts = <18>; | |
786 | reg-shift = <2>; | |
787 | reg-io-width = <4>; | |
9ff49ec7 | 788 | clocks = <&apb1_gates 21>; |
76f14d0a MR |
789 | status = "disabled"; |
790 | }; | |
791 | ||
792 | uart6: serial@01c29800 { | |
793 | compatible = "snps,dw-apb-uart"; | |
794 | reg = <0x01c29800 0x400>; | |
795 | interrupts = <19>; | |
796 | reg-shift = <2>; | |
797 | reg-io-width = <4>; | |
9ff49ec7 | 798 | clocks = <&apb1_gates 22>; |
76f14d0a MR |
799 | status = "disabled"; |
800 | }; | |
801 | ||
802 | uart7: serial@01c29c00 { | |
803 | compatible = "snps,dw-apb-uart"; | |
804 | reg = <0x01c29c00 0x400>; | |
805 | interrupts = <20>; | |
806 | reg-shift = <2>; | |
807 | reg-io-width = <4>; | |
9ff49ec7 | 808 | clocks = <&apb1_gates 23>; |
76f14d0a MR |
809 | status = "disabled"; |
810 | }; | |
f1741fda MR |
811 | |
812 | i2c0: i2c@01c2ac00 { | |
d275545e | 813 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
814 | reg = <0x01c2ac00 0x400>; |
815 | interrupts = <7>; | |
816 | clocks = <&apb1_gates 0>; | |
f1741fda | 817 | status = "disabled"; |
60bbe316 HG |
818 | #address-cells = <1>; |
819 | #size-cells = <0>; | |
f1741fda MR |
820 | }; |
821 | ||
822 | i2c1: i2c@01c2b000 { | |
d275545e | 823 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
824 | reg = <0x01c2b000 0x400>; |
825 | interrupts = <8>; | |
826 | clocks = <&apb1_gates 1>; | |
f1741fda | 827 | status = "disabled"; |
60bbe316 HG |
828 | #address-cells = <1>; |
829 | #size-cells = <0>; | |
f1741fda MR |
830 | }; |
831 | ||
832 | i2c2: i2c@01c2b400 { | |
d275545e | 833 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
834 | reg = <0x01c2b400 0x400>; |
835 | interrupts = <9>; | |
836 | clocks = <&apb1_gates 2>; | |
f1741fda | 837 | status = "disabled"; |
60bbe316 HG |
838 | #address-cells = <1>; |
839 | #size-cells = <0>; | |
f1741fda | 840 | }; |
874b4e45 | 841 | }; |
7423d2d8 | 842 | }; |