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Commit | Line | Data |
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7423d2d8 SR |
1 | /* |
2 | * Copyright 2012 Stefan Roese | |
3 | * Stefan Roese <sr@denx.de> | |
4 | * | |
033ba3d7 MR |
5 | * This file is dual-licensed: you can use it either under the terms |
6 | * of the GPL or the X11 license, at your option. Note that this dual | |
7 | * licensing only applies to this file, and not this project as a | |
8 | * whole. | |
7423d2d8 | 9 | * |
033ba3d7 MR |
10 | * a) This library is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of the | |
13 | * License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
033ba3d7 MR |
20 | * Or, alternatively, |
21 | * | |
22 | * b) Permission is hereby granted, free of charge, to any person | |
23 | * obtaining a copy of this software and associated documentation | |
24 | * files (the "Software"), to deal in the Software without | |
25 | * restriction, including without limitation the rights to use, | |
26 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
27 | * sell copies of the Software, and to permit persons to whom the | |
28 | * Software is furnished to do so, subject to the following | |
29 | * conditions: | |
30 | * | |
31 | * The above copyright notice and this permission notice shall be | |
32 | * included in all copies or substantial portions of the Software. | |
33 | * | |
34 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
35 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
36 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
37 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
38 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
39 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
40 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
41 | * OTHER DEALINGS IN THE SOFTWARE. | |
7423d2d8 SR |
42 | */ |
43 | ||
71455701 | 44 | #include "skeleton.dtsi" |
7423d2d8 | 45 | |
541ce2ca CYT |
46 | #include <dt-bindings/thermal/thermal.h> |
47 | ||
1f9f6a78 | 48 | #include <dt-bindings/dma/sun4i-a10.h> |
092a0c3b | 49 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
7423d2d8 SR |
50 | |
51 | / { | |
69144e3b MR |
52 | interrupt-parent = <&intc>; |
53 | ||
e751cce9 EL |
54 | aliases { |
55 | ethernet0 = &emac; | |
56 | }; | |
57 | ||
5790d4ee HG |
58 | chosen { |
59 | #address-cells = <1>; | |
60 | #size-cells = <1>; | |
61 | ranges; | |
62 | ||
a9f8cda3 HG |
63 | framebuffer@0 { |
64 | compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; | |
65 | allwinner,pipeline = "de_be0-lcd0-hdmi"; | |
678e75d3 HG |
66 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, |
67 | <&ahb_gates 44>; | |
5790d4ee HG |
68 | status = "disabled"; |
69 | }; | |
8cedd662 HG |
70 | |
71 | framebuffer@1 { | |
72 | compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; | |
73 | allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; | |
74 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, | |
75 | <&ahb_gates 44>, <&ahb_gates 46>; | |
76 | status = "disabled"; | |
77 | }; | |
fd18c7ea HG |
78 | |
79 | framebuffer@2 { | |
80 | compatible = "allwinner,simple-framebuffer", | |
81 | "simple-framebuffer"; | |
82 | allwinner,pipeline = "de_fe0-de_be0-lcd0"; | |
83 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, | |
84 | <&ahb_gates 46>; | |
85 | status = "disabled"; | |
86 | }; | |
87 | ||
88 | framebuffer@3 { | |
89 | compatible = "allwinner,simple-framebuffer", | |
90 | "simple-framebuffer"; | |
91 | allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; | |
92 | clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, | |
93 | <&ahb_gates 44>, <&ahb_gates 46>; | |
94 | status = "disabled"; | |
95 | }; | |
5790d4ee HG |
96 | }; |
97 | ||
69144e3b | 98 | cpus { |
8b2efa89 AB |
99 | #address-cells = <1>; |
100 | #size-cells = <0>; | |
7294be5d | 101 | cpu0: cpu@0 { |
14c44aa5 | 102 | device_type = "cpu"; |
69144e3b | 103 | compatible = "arm,cortex-a8"; |
14c44aa5 | 104 | reg = <0x0>; |
7294be5d CYT |
105 | clocks = <&cpu>; |
106 | clock-latency = <244144>; /* 8 32k periods */ | |
107 | operating-points = < | |
108 | /* kHz uV */ | |
7294be5d CYT |
109 | 1008000 1400000 |
110 | 912000 1350000 | |
111 | 864000 1300000 | |
112 | 624000 1250000 | |
113 | >; | |
114 | #cooling-cells = <2>; | |
115 | cooling-min-level = <0>; | |
370a9b5f | 116 | cooling-max-level = <3>; |
69144e3b MR |
117 | }; |
118 | }; | |
119 | ||
541ce2ca CYT |
120 | thermal-zones { |
121 | cpu_thermal { | |
122 | /* milliseconds */ | |
123 | polling-delay-passive = <250>; | |
124 | polling-delay = <1000>; | |
125 | thermal-sensors = <&rtp>; | |
126 | ||
127 | cooling-maps { | |
128 | map0 { | |
129 | trip = <&cpu_alert0>; | |
130 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
131 | }; | |
132 | }; | |
133 | ||
134 | trips { | |
135 | cpu_alert0: cpu_alert0 { | |
136 | /* milliCelsius */ | |
137 | temperature = <850000>; | |
138 | hysteresis = <2000>; | |
139 | type = "passive"; | |
140 | }; | |
141 | ||
142 | cpu_crit: cpu_crit { | |
143 | /* milliCelsius */ | |
144 | temperature = <100000>; | |
145 | hysteresis = <2000>; | |
146 | type = "critical"; | |
147 | }; | |
148 | }; | |
69144e3b MR |
149 | }; |
150 | }; | |
151 | ||
7423d2d8 SR |
152 | memory { |
153 | reg = <0x40000000 0x80000000>; | |
154 | }; | |
874b4e45 | 155 | |
69144e3b MR |
156 | clocks { |
157 | #address-cells = <1>; | |
158 | #size-cells = <1>; | |
159 | ranges; | |
160 | ||
161 | /* | |
162 | * This is a dummy clock, to be used as placeholder on | |
163 | * other mux clocks when a specific parent clock is not | |
164 | * yet implemented. It should be dropped when the driver | |
165 | * is complete. | |
166 | */ | |
167 | dummy: dummy { | |
168 | #clock-cells = <0>; | |
169 | compatible = "fixed-clock"; | |
170 | clock-frequency = <0>; | |
171 | }; | |
172 | ||
dfb12c0c | 173 | osc24M: clk@01c20050 { |
69144e3b | 174 | #clock-cells = <0>; |
bf6534a1 | 175 | compatible = "allwinner,sun4i-a10-osc-clk"; |
69144e3b | 176 | reg = <0x01c20050 0x4>; |
92fd6e06 | 177 | clock-frequency = <24000000>; |
dfb12c0c | 178 | clock-output-names = "osc24M"; |
69144e3b MR |
179 | }; |
180 | ||
dfb12c0c | 181 | osc32k: clk@0 { |
69144e3b MR |
182 | #clock-cells = <0>; |
183 | compatible = "fixed-clock"; | |
184 | clock-frequency = <32768>; | |
dfb12c0c | 185 | clock-output-names = "osc32k"; |
69144e3b MR |
186 | }; |
187 | ||
dfb12c0c | 188 | pll1: clk@01c20000 { |
69144e3b | 189 | #clock-cells = <0>; |
bf6534a1 | 190 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
69144e3b MR |
191 | reg = <0x01c20000 0x4>; |
192 | clocks = <&osc24M>; | |
dfb12c0c | 193 | clock-output-names = "pll1"; |
69144e3b MR |
194 | }; |
195 | ||
dfb12c0c | 196 | pll4: clk@01c20018 { |
ec5589f7 | 197 | #clock-cells = <0>; |
bf6534a1 | 198 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
ec5589f7 EL |
199 | reg = <0x01c20018 0x4>; |
200 | clocks = <&osc24M>; | |
dfb12c0c | 201 | clock-output-names = "pll4"; |
ec5589f7 EL |
202 | }; |
203 | ||
dfb12c0c | 204 | pll5: clk@01c20020 { |
c3e5e66b | 205 | #clock-cells = <1>; |
bf6534a1 | 206 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
c3e5e66b EL |
207 | reg = <0x01c20020 0x4>; |
208 | clocks = <&osc24M>; | |
209 | clock-output-names = "pll5_ddr", "pll5_other"; | |
210 | }; | |
211 | ||
dfb12c0c | 212 | pll6: clk@01c20028 { |
c3e5e66b | 213 | #clock-cells = <1>; |
bf6534a1 | 214 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
c3e5e66b EL |
215 | reg = <0x01c20028 0x4>; |
216 | clocks = <&osc24M>; | |
217 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
218 | }; | |
219 | ||
69144e3b MR |
220 | /* dummy is 200M */ |
221 | cpu: cpu@01c20054 { | |
222 | #clock-cells = <0>; | |
bf6534a1 | 223 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
69144e3b MR |
224 | reg = <0x01c20054 0x4>; |
225 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
dfb12c0c | 226 | clock-output-names = "cpu"; |
69144e3b MR |
227 | }; |
228 | ||
229 | axi: axi@01c20054 { | |
230 | #clock-cells = <0>; | |
bf6534a1 | 231 | compatible = "allwinner,sun4i-a10-axi-clk"; |
69144e3b MR |
232 | reg = <0x01c20054 0x4>; |
233 | clocks = <&cpu>; | |
dfb12c0c | 234 | clock-output-names = "axi"; |
69144e3b MR |
235 | }; |
236 | ||
dfb12c0c | 237 | axi_gates: clk@01c2005c { |
69144e3b | 238 | #clock-cells = <1>; |
bf6534a1 | 239 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
69144e3b MR |
240 | reg = <0x01c2005c 0x4>; |
241 | clocks = <&axi>; | |
242 | clock-output-names = "axi_dram"; | |
243 | }; | |
244 | ||
245 | ahb: ahb@01c20054 { | |
246 | #clock-cells = <0>; | |
bf6534a1 | 247 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
69144e3b MR |
248 | reg = <0x01c20054 0x4>; |
249 | clocks = <&axi>; | |
dfb12c0c | 250 | clock-output-names = "ahb"; |
69144e3b MR |
251 | }; |
252 | ||
dfb12c0c | 253 | ahb_gates: clk@01c20060 { |
69144e3b | 254 | #clock-cells = <1>; |
bf6534a1 | 255 | compatible = "allwinner,sun4i-a10-ahb-gates-clk"; |
69144e3b MR |
256 | reg = <0x01c20060 0x8>; |
257 | clocks = <&ahb>; | |
258 | clock-output-names = "ahb_usb0", "ahb_ehci0", | |
259 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", | |
260 | "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", | |
261 | "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", | |
262 | "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", | |
263 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", | |
264 | "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", | |
265 | "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", | |
266 | "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", | |
267 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
268 | "ahb_de_fe1", "ahb_mp", "ahb_mali400"; | |
269 | }; | |
270 | ||
271 | apb0: apb0@01c20054 { | |
272 | #clock-cells = <0>; | |
bf6534a1 | 273 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
69144e3b MR |
274 | reg = <0x01c20054 0x4>; |
275 | clocks = <&ahb>; | |
dfb12c0c | 276 | clock-output-names = "apb0"; |
69144e3b MR |
277 | }; |
278 | ||
dfb12c0c | 279 | apb0_gates: clk@01c20068 { |
69144e3b | 280 | #clock-cells = <1>; |
bf6534a1 | 281 | compatible = "allwinner,sun4i-a10-apb0-gates-clk"; |
69144e3b MR |
282 | reg = <0x01c20068 0x4>; |
283 | clocks = <&apb0>; | |
284 | clock-output-names = "apb0_codec", "apb0_spdif", | |
285 | "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", | |
286 | "apb0_ir1", "apb0_keypad"; | |
287 | }; | |
288 | ||
acbcc0f0 | 289 | apb1: clk@01c20058 { |
69144e3b | 290 | #clock-cells = <0>; |
bf6534a1 | 291 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
69144e3b | 292 | reg = <0x01c20058 0x4>; |
acbcc0f0 | 293 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
dfb12c0c | 294 | clock-output-names = "apb1"; |
69144e3b MR |
295 | }; |
296 | ||
dfb12c0c | 297 | apb1_gates: clk@01c2006c { |
69144e3b | 298 | #clock-cells = <1>; |
bf6534a1 | 299 | compatible = "allwinner,sun4i-a10-apb1-gates-clk"; |
69144e3b MR |
300 | reg = <0x01c2006c 0x4>; |
301 | clocks = <&apb1>; | |
302 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
303 | "apb1_i2c2", "apb1_can", "apb1_scr", | |
304 | "apb1_ps20", "apb1_ps21", "apb1_uart0", | |
305 | "apb1_uart1", "apb1_uart2", "apb1_uart3", | |
306 | "apb1_uart4", "apb1_uart5", "apb1_uart6", | |
307 | "apb1_uart7"; | |
308 | }; | |
4b756ffb EL |
309 | |
310 | nand_clk: clk@01c20080 { | |
311 | #clock-cells = <0>; | |
bf6534a1 | 312 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
313 | reg = <0x01c20080 0x4>; |
314 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
315 | clock-output-names = "nand"; | |
316 | }; | |
317 | ||
318 | ms_clk: clk@01c20084 { | |
319 | #clock-cells = <0>; | |
bf6534a1 | 320 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
321 | reg = <0x01c20084 0x4>; |
322 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
323 | clock-output-names = "ms"; | |
324 | }; | |
325 | ||
326 | mmc0_clk: clk@01c20088 { | |
d8c3a392 MR |
327 | #clock-cells = <1>; |
328 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
329 | reg = <0x01c20088 0x4>; |
330 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
331 | clock-output-names = "mmc0", |
332 | "mmc0_output", | |
333 | "mmc0_sample"; | |
4b756ffb EL |
334 | }; |
335 | ||
336 | mmc1_clk: clk@01c2008c { | |
d8c3a392 MR |
337 | #clock-cells = <1>; |
338 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
339 | reg = <0x01c2008c 0x4>; |
340 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
341 | clock-output-names = "mmc1", |
342 | "mmc1_output", | |
343 | "mmc1_sample"; | |
4b756ffb EL |
344 | }; |
345 | ||
346 | mmc2_clk: clk@01c20090 { | |
d8c3a392 MR |
347 | #clock-cells = <1>; |
348 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
349 | reg = <0x01c20090 0x4>; |
350 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
351 | clock-output-names = "mmc2", |
352 | "mmc2_output", | |
353 | "mmc2_sample"; | |
4b756ffb EL |
354 | }; |
355 | ||
356 | mmc3_clk: clk@01c20094 { | |
d8c3a392 MR |
357 | #clock-cells = <1>; |
358 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
359 | reg = <0x01c20094 0x4>; |
360 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
361 | clock-output-names = "mmc3", |
362 | "mmc3_output", | |
363 | "mmc3_sample"; | |
4b756ffb EL |
364 | }; |
365 | ||
366 | ts_clk: clk@01c20098 { | |
367 | #clock-cells = <0>; | |
bf6534a1 | 368 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
369 | reg = <0x01c20098 0x4>; |
370 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
371 | clock-output-names = "ts"; | |
372 | }; | |
373 | ||
374 | ss_clk: clk@01c2009c { | |
375 | #clock-cells = <0>; | |
bf6534a1 | 376 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
377 | reg = <0x01c2009c 0x4>; |
378 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
379 | clock-output-names = "ss"; | |
380 | }; | |
381 | ||
382 | spi0_clk: clk@01c200a0 { | |
383 | #clock-cells = <0>; | |
bf6534a1 | 384 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
385 | reg = <0x01c200a0 0x4>; |
386 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
387 | clock-output-names = "spi0"; | |
388 | }; | |
389 | ||
390 | spi1_clk: clk@01c200a4 { | |
391 | #clock-cells = <0>; | |
bf6534a1 | 392 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
393 | reg = <0x01c200a4 0x4>; |
394 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
395 | clock-output-names = "spi1"; | |
396 | }; | |
397 | ||
398 | spi2_clk: clk@01c200a8 { | |
399 | #clock-cells = <0>; | |
bf6534a1 | 400 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
401 | reg = <0x01c200a8 0x4>; |
402 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
403 | clock-output-names = "spi2"; | |
404 | }; | |
405 | ||
406 | pata_clk: clk@01c200ac { | |
407 | #clock-cells = <0>; | |
bf6534a1 | 408 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
409 | reg = <0x01c200ac 0x4>; |
410 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
411 | clock-output-names = "pata"; | |
412 | }; | |
413 | ||
414 | ir0_clk: clk@01c200b0 { | |
415 | #clock-cells = <0>; | |
bf6534a1 | 416 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
417 | reg = <0x01c200b0 0x4>; |
418 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
419 | clock-output-names = "ir0"; | |
420 | }; | |
421 | ||
422 | ir1_clk: clk@01c200b4 { | |
423 | #clock-cells = <0>; | |
bf6534a1 | 424 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
425 | reg = <0x01c200b4 0x4>; |
426 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
427 | clock-output-names = "ir1"; | |
428 | }; | |
429 | ||
0076c8bd RB |
430 | usb_clk: clk@01c200cc { |
431 | #clock-cells = <1>; | |
432 | #reset-cells = <1>; | |
433 | compatible = "allwinner,sun4i-a10-usb-clk"; | |
434 | reg = <0x01c200cc 0x4>; | |
435 | clocks = <&pll6 1>; | |
436 | clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; | |
437 | }; | |
438 | ||
4b756ffb EL |
439 | spi3_clk: clk@01c200d4 { |
440 | #clock-cells = <0>; | |
bf6534a1 | 441 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
442 | reg = <0x01c200d4 0x4>; |
443 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
444 | clock-output-names = "spi3"; | |
445 | }; | |
69144e3b MR |
446 | }; |
447 | ||
6d92b80f HG |
448 | /* |
449 | * Note we use the address where the mmio registers start, not where | |
450 | * the SRAM blocks start, this cannot be changed because that would be | |
451 | * a devicetree ABI change. | |
452 | */ | |
b74aec1a | 453 | soc@01c00000 { |
69144e3b MR |
454 | compatible = "simple-bus"; |
455 | #address-cells = <1>; | |
456 | #size-cells = <1>; | |
69144e3b MR |
457 | ranges; |
458 | ||
6d92b80f HG |
459 | sram@00000000 { |
460 | compatible = "allwinner,sun4i-a10-sram"; | |
461 | reg = <0x00000000 0x4000>; | |
462 | allwinner,sram-name = "A1"; | |
463 | }; | |
464 | ||
465 | sram@00004000 { | |
466 | compatible = "allwinner,sun4i-a10-sram"; | |
467 | reg = <0x00004000 0x4000>; | |
468 | allwinner,sram-name = "A2"; | |
469 | }; | |
470 | ||
471 | sram@00008000 { | |
472 | compatible = "allwinner,sun4i-a10-sram"; | |
473 | reg = <0x00008000 0x4000>; | |
474 | allwinner,sram-name = "A3-A4"; | |
475 | }; | |
476 | ||
477 | sram@00010000 { | |
478 | compatible = "allwinner,sun4i-a10-sram"; | |
479 | reg = <0x00010000 0x1000>; | |
480 | allwinner,sram-name = "D"; | |
481 | }; | |
482 | ||
483 | sram-controller@01c00000 { | |
484 | compatible = "allwinner,sun4i-a10-sram-controller"; | |
485 | reg = <0x01c00000 0x30>; | |
486 | }; | |
487 | ||
1324f532 EL |
488 | dma: dma-controller@01c02000 { |
489 | compatible = "allwinner,sun4i-a10-dma"; | |
490 | reg = <0x01c02000 0x1000>; | |
491 | interrupts = <27>; | |
492 | clocks = <&ahb_gates 6>; | |
493 | #dma-cells = <2>; | |
494 | }; | |
495 | ||
65918e26 MR |
496 | spi0: spi@01c05000 { |
497 | compatible = "allwinner,sun4i-a10-spi"; | |
498 | reg = <0x01c05000 0x1000>; | |
499 | interrupts = <10>; | |
500 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
501 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
502 | dmas = <&dma SUN4I_DMA_DEDICATED 27>, |
503 | <&dma SUN4I_DMA_DEDICATED 26>; | |
4192ff81 | 504 | dma-names = "rx", "tx"; |
65918e26 MR |
505 | status = "disabled"; |
506 | #address-cells = <1>; | |
507 | #size-cells = <0>; | |
508 | }; | |
509 | ||
510 | spi1: spi@01c06000 { | |
511 | compatible = "allwinner,sun4i-a10-spi"; | |
512 | reg = <0x01c06000 0x1000>; | |
513 | interrupts = <11>; | |
514 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
515 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
516 | dmas = <&dma SUN4I_DMA_DEDICATED 9>, |
517 | <&dma SUN4I_DMA_DEDICATED 8>; | |
4192ff81 | 518 | dma-names = "rx", "tx"; |
65918e26 MR |
519 | status = "disabled"; |
520 | #address-cells = <1>; | |
521 | #size-cells = <0>; | |
522 | }; | |
523 | ||
e38afcb3 | 524 | emac: ethernet@01c0b000 { |
1c70e099 | 525 | compatible = "allwinner,sun4i-a10-emac"; |
e38afcb3 MR |
526 | reg = <0x01c0b000 0x1000>; |
527 | interrupts = <55>; | |
528 | clocks = <&ahb_gates 17>; | |
529 | status = "disabled"; | |
530 | }; | |
531 | ||
92395f56 | 532 | mdio: mdio@01c0b080 { |
1c70e099 | 533 | compatible = "allwinner,sun4i-a10-mdio"; |
e38afcb3 MR |
534 | reg = <0x01c0b080 0x14>; |
535 | status = "disabled"; | |
536 | #address-cells = <1>; | |
537 | #size-cells = <0>; | |
538 | }; | |
539 | ||
b258b369 DL |
540 | mmc0: mmc@01c0f000 { |
541 | compatible = "allwinner,sun4i-a10-mmc"; | |
542 | reg = <0x01c0f000 0x1000>; | |
d8c3a392 MR |
543 | clocks = <&ahb_gates 8>, |
544 | <&mmc0_clk 0>, | |
545 | <&mmc0_clk 1>, | |
546 | <&mmc0_clk 2>; | |
547 | clock-names = "ahb", | |
548 | "mmc", | |
549 | "output", | |
550 | "sample"; | |
b258b369 DL |
551 | interrupts = <32>; |
552 | status = "disabled"; | |
4c1bb9c3 HG |
553 | #address-cells = <1>; |
554 | #size-cells = <0>; | |
b258b369 DL |
555 | }; |
556 | ||
557 | mmc1: mmc@01c10000 { | |
558 | compatible = "allwinner,sun4i-a10-mmc"; | |
559 | reg = <0x01c10000 0x1000>; | |
d8c3a392 MR |
560 | clocks = <&ahb_gates 9>, |
561 | <&mmc1_clk 0>, | |
562 | <&mmc1_clk 1>, | |
563 | <&mmc1_clk 2>; | |
564 | clock-names = "ahb", | |
565 | "mmc", | |
566 | "output", | |
567 | "sample"; | |
b258b369 DL |
568 | interrupts = <33>; |
569 | status = "disabled"; | |
4c1bb9c3 HG |
570 | #address-cells = <1>; |
571 | #size-cells = <0>; | |
b258b369 DL |
572 | }; |
573 | ||
574 | mmc2: mmc@01c11000 { | |
575 | compatible = "allwinner,sun4i-a10-mmc"; | |
576 | reg = <0x01c11000 0x1000>; | |
d8c3a392 MR |
577 | clocks = <&ahb_gates 10>, |
578 | <&mmc2_clk 0>, | |
579 | <&mmc2_clk 1>, | |
580 | <&mmc2_clk 2>; | |
581 | clock-names = "ahb", | |
582 | "mmc", | |
583 | "output", | |
584 | "sample"; | |
b258b369 DL |
585 | interrupts = <34>; |
586 | status = "disabled"; | |
4c1bb9c3 HG |
587 | #address-cells = <1>; |
588 | #size-cells = <0>; | |
b258b369 DL |
589 | }; |
590 | ||
591 | mmc3: mmc@01c12000 { | |
592 | compatible = "allwinner,sun4i-a10-mmc"; | |
593 | reg = <0x01c12000 0x1000>; | |
d8c3a392 MR |
594 | clocks = <&ahb_gates 11>, |
595 | <&mmc3_clk 0>, | |
596 | <&mmc3_clk 1>, | |
597 | <&mmc3_clk 2>; | |
598 | clock-names = "ahb", | |
599 | "mmc", | |
600 | "output", | |
601 | "sample"; | |
b258b369 DL |
602 | interrupts = <35>; |
603 | status = "disabled"; | |
4c1bb9c3 HG |
604 | #address-cells = <1>; |
605 | #size-cells = <0>; | |
b258b369 DL |
606 | }; |
607 | ||
6ab1ce24 RB |
608 | usbphy: phy@01c13400 { |
609 | #phy-cells = <1>; | |
610 | compatible = "allwinner,sun4i-a10-usb-phy"; | |
611 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
612 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
613 | clocks = <&usb_clk 8>; | |
614 | clock-names = "usb_phy"; | |
4dba4185 CYT |
615 | resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; |
616 | reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; | |
6ab1ce24 RB |
617 | status = "disabled"; |
618 | }; | |
619 | ||
620 | ehci0: usb@01c14000 { | |
621 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
622 | reg = <0x01c14000 0x100>; | |
623 | interrupts = <39>; | |
624 | clocks = <&ahb_gates 1>; | |
625 | phys = <&usbphy 1>; | |
626 | phy-names = "usb"; | |
627 | status = "disabled"; | |
628 | }; | |
629 | ||
630 | ohci0: usb@01c14400 { | |
631 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
632 | reg = <0x01c14400 0x100>; | |
633 | interrupts = <64>; | |
634 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
635 | phys = <&usbphy 1>; | |
636 | phy-names = "usb"; | |
637 | status = "disabled"; | |
638 | }; | |
639 | ||
65918e26 MR |
640 | spi2: spi@01c17000 { |
641 | compatible = "allwinner,sun4i-a10-spi"; | |
642 | reg = <0x01c17000 0x1000>; | |
643 | interrupts = <12>; | |
644 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
645 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
646 | dmas = <&dma SUN4I_DMA_DEDICATED 29>, |
647 | <&dma SUN4I_DMA_DEDICATED 28>; | |
4192ff81 | 648 | dma-names = "rx", "tx"; |
65918e26 MR |
649 | status = "disabled"; |
650 | #address-cells = <1>; | |
651 | #size-cells = <0>; | |
652 | }; | |
653 | ||
248bd1e2 OS |
654 | ahci: sata@01c18000 { |
655 | compatible = "allwinner,sun4i-a10-ahci"; | |
656 | reg = <0x01c18000 0x1000>; | |
657 | interrupts = <56>; | |
658 | clocks = <&pll6 0>, <&ahb_gates 25>; | |
659 | status = "disabled"; | |
660 | }; | |
661 | ||
6ab1ce24 RB |
662 | ehci1: usb@01c1c000 { |
663 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
664 | reg = <0x01c1c000 0x100>; | |
665 | interrupts = <40>; | |
666 | clocks = <&ahb_gates 3>; | |
667 | phys = <&usbphy 2>; | |
668 | phy-names = "usb"; | |
669 | status = "disabled"; | |
670 | }; | |
671 | ||
672 | ohci1: usb@01c1c400 { | |
673 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
674 | reg = <0x01c1c400 0x100>; | |
675 | interrupts = <65>; | |
676 | clocks = <&usb_clk 7>, <&ahb_gates 4>; | |
677 | phys = <&usbphy 2>; | |
678 | phy-names = "usb"; | |
679 | status = "disabled"; | |
680 | }; | |
681 | ||
65918e26 MR |
682 | spi3: spi@01c1f000 { |
683 | compatible = "allwinner,sun4i-a10-spi"; | |
684 | reg = <0x01c1f000 0x1000>; | |
685 | interrupts = <50>; | |
686 | clocks = <&ahb_gates 23>, <&spi3_clk>; | |
687 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
688 | dmas = <&dma SUN4I_DMA_DEDICATED 31>, |
689 | <&dma SUN4I_DMA_DEDICATED 30>; | |
4192ff81 | 690 | dma-names = "rx", "tx"; |
65918e26 MR |
691 | status = "disabled"; |
692 | #address-cells = <1>; | |
693 | #size-cells = <0>; | |
694 | }; | |
695 | ||
69144e3b | 696 | intc: interrupt-controller@01c20400 { |
09504a7d | 697 | compatible = "allwinner,sun4i-a10-ic"; |
69144e3b MR |
698 | reg = <0x01c20400 0x400>; |
699 | interrupt-controller; | |
700 | #interrupt-cells = <1>; | |
701 | }; | |
702 | ||
e10911e1 | 703 | pio: pinctrl@01c20800 { |
874b4e45 MR |
704 | compatible = "allwinner,sun4i-a10-pinctrl"; |
705 | reg = <0x01c20800 0x400>; | |
39138bc6 | 706 | interrupts = <28>; |
36386d6e | 707 | clocks = <&apb0_gates 5>; |
e10911e1 | 708 | gpio-controller; |
39138bc6 | 709 | interrupt-controller; |
7d4ff96d | 710 | #interrupt-cells = <2>; |
874b4e45 | 711 | #size-cells = <0>; |
e10911e1 | 712 | #gpio-cells = <3>; |
581981be | 713 | |
1d5726e9 AB |
714 | pwm0_pins_a: pwm0@0 { |
715 | allwinner,pins = "PB2"; | |
716 | allwinner,function = "pwm"; | |
092a0c3b MR |
717 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
718 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1d5726e9 AB |
719 | }; |
720 | ||
721 | pwm1_pins_a: pwm1@0 { | |
722 | allwinner,pins = "PI3"; | |
723 | allwinner,function = "pwm"; | |
092a0c3b MR |
724 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
725 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1d5726e9 AB |
726 | }; |
727 | ||
581981be MR |
728 | uart0_pins_a: uart0@0 { |
729 | allwinner,pins = "PB22", "PB23"; | |
730 | allwinner,function = "uart0"; | |
092a0c3b MR |
731 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
732 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
581981be MR |
733 | }; |
734 | ||
735 | uart0_pins_b: uart0@1 { | |
736 | allwinner,pins = "PF2", "PF4"; | |
737 | allwinner,function = "uart0"; | |
092a0c3b MR |
738 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
739 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
581981be MR |
740 | }; |
741 | ||
742 | uart1_pins_a: uart1@0 { | |
743 | allwinner,pins = "PA10", "PA11"; | |
744 | allwinner,function = "uart1"; | |
092a0c3b MR |
745 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
746 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
581981be | 747 | }; |
27cce4ff MR |
748 | |
749 | i2c0_pins_a: i2c0@0 { | |
750 | allwinner,pins = "PB0", "PB1"; | |
751 | allwinner,function = "i2c0"; | |
092a0c3b MR |
752 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
753 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
27cce4ff MR |
754 | }; |
755 | ||
756 | i2c1_pins_a: i2c1@0 { | |
757 | allwinner,pins = "PB18", "PB19"; | |
758 | allwinner,function = "i2c1"; | |
092a0c3b MR |
759 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
760 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
27cce4ff MR |
761 | }; |
762 | ||
763 | i2c2_pins_a: i2c2@0 { | |
764 | allwinner,pins = "PB20", "PB21"; | |
765 | allwinner,function = "i2c2"; | |
092a0c3b MR |
766 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
767 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
27cce4ff | 768 | }; |
496322bc | 769 | |
b21da664 MR |
770 | emac_pins_a: emac0@0 { |
771 | allwinner,pins = "PA0", "PA1", "PA2", | |
772 | "PA3", "PA4", "PA5", "PA6", | |
773 | "PA7", "PA8", "PA9", "PA10", | |
774 | "PA11", "PA12", "PA13", "PA14", | |
775 | "PA15", "PA16"; | |
776 | allwinner,function = "emac"; | |
092a0c3b MR |
777 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
778 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
b21da664 | 779 | }; |
b5f86a3a HG |
780 | |
781 | mmc0_pins_a: mmc0@0 { | |
782 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | |
783 | allwinner,function = "mmc0"; | |
092a0c3b MR |
784 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
785 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
b5f86a3a HG |
786 | }; |
787 | ||
788 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { | |
789 | allwinner,pins = "PH1"; | |
790 | allwinner,function = "gpio_in"; | |
092a0c3b MR |
791 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
792 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
b5f86a3a | 793 | }; |
a4e1099a | 794 | |
469a22e6 MC |
795 | ir0_rx_pins_a: ir0@0 { |
796 | allwinner,pins = "PB4"; | |
a4e1099a | 797 | allwinner,function = "ir0"; |
092a0c3b MR |
798 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
799 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
a4e1099a HG |
800 | }; |
801 | ||
469a22e6 MC |
802 | ir0_tx_pins_a: ir0@1 { |
803 | allwinner,pins = "PB3"; | |
804 | allwinner,function = "ir0"; | |
805 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
806 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
807 | }; | |
808 | ||
809 | ir1_rx_pins_a: ir1@0 { | |
810 | allwinner,pins = "PB23"; | |
811 | allwinner,function = "ir1"; | |
812 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
813 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
814 | }; | |
815 | ||
816 | ir1_tx_pins_a: ir1@1 { | |
817 | allwinner,pins = "PB22"; | |
a4e1099a | 818 | allwinner,function = "ir1"; |
092a0c3b MR |
819 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
820 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
a4e1099a | 821 | }; |
ec66d0bb AG |
822 | |
823 | spi0_pins_a: spi0@0 { | |
824 | allwinner,pins = "PI10", "PI11", "PI12", "PI13"; | |
825 | allwinner,function = "spi0"; | |
092a0c3b MR |
826 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
827 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb AG |
828 | }; |
829 | ||
830 | spi1_pins_a: spi1@0 { | |
831 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; | |
832 | allwinner,function = "spi1"; | |
092a0c3b MR |
833 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
834 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb AG |
835 | }; |
836 | ||
837 | spi2_pins_a: spi2@0 { | |
838 | allwinner,pins = "PB14", "PB15", "PB16", "PB17"; | |
839 | allwinner,function = "spi2"; | |
092a0c3b MR |
840 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
841 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb AG |
842 | }; |
843 | ||
844 | spi2_pins_b: spi2@1 { | |
845 | allwinner,pins = "PC19", "PC20", "PC21", "PC22"; | |
846 | allwinner,function = "spi2"; | |
092a0c3b MR |
847 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
848 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb | 849 | }; |
1e8d1567 VP |
850 | |
851 | ps20_pins_a: ps20@0 { | |
852 | allwinner,pins = "PI20", "PI21"; | |
853 | allwinner,function = "ps2"; | |
854 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
855 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
856 | }; | |
857 | ||
858 | ps21_pins_a: ps21@0 { | |
859 | allwinner,pins = "PH12", "PH13"; | |
860 | allwinner,function = "ps2"; | |
861 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
862 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
a4e1099a | 863 | }; |
874b4e45 | 864 | }; |
89b3c99f | 865 | |
69144e3b | 866 | timer@01c20c00 { |
b4f26440 | 867 | compatible = "allwinner,sun4i-a10-timer"; |
69144e3b MR |
868 | reg = <0x01c20c00 0x90>; |
869 | interrupts = <22>; | |
870 | clocks = <&osc24M>; | |
871 | }; | |
872 | ||
873 | wdt: watchdog@01c20c90 { | |
ca5d04d9 | 874 | compatible = "allwinner,sun4i-a10-wdt"; |
69144e3b MR |
875 | reg = <0x01c20c90 0x10>; |
876 | }; | |
877 | ||
b5d905c7 | 878 | rtc: rtc@01c20d00 { |
5fc4bc89 | 879 | compatible = "allwinner,sun4i-a10-rtc"; |
b5d905c7 CC |
880 | reg = <0x01c20d00 0x20>; |
881 | interrupts = <24>; | |
882 | }; | |
883 | ||
4b57a395 AB |
884 | pwm: pwm@01c20e00 { |
885 | compatible = "allwinner,sun4i-a10-pwm"; | |
886 | reg = <0x01c20e00 0xc>; | |
887 | clocks = <&osc24M>; | |
888 | #pwm-cells = <3>; | |
889 | status = "disabled"; | |
890 | }; | |
891 | ||
a4e1099a HG |
892 | ir0: ir@01c21800 { |
893 | compatible = "allwinner,sun4i-a10-ir"; | |
894 | clocks = <&apb0_gates 6>, <&ir0_clk>; | |
895 | clock-names = "apb", "ir"; | |
896 | interrupts = <5>; | |
897 | reg = <0x01c21800 0x40>; | |
898 | status = "disabled"; | |
899 | }; | |
900 | ||
901 | ir1: ir@01c21c00 { | |
902 | compatible = "allwinner,sun4i-a10-ir"; | |
903 | clocks = <&apb0_gates 7>, <&ir1_clk>; | |
904 | clock-names = "apb", "ir"; | |
905 | interrupts = <6>; | |
906 | reg = <0x01c21c00 0x40>; | |
907 | status = "disabled"; | |
908 | }; | |
909 | ||
b0512e15 HG |
910 | lradc: lradc@01c22800 { |
911 | compatible = "allwinner,sun4i-a10-lradc-keys"; | |
912 | reg = <0x01c22800 0x100>; | |
913 | interrupts = <31>; | |
914 | status = "disabled"; | |
915 | }; | |
916 | ||
2bad969f | 917 | sid: eeprom@01c23800 { |
043d56ee | 918 | compatible = "allwinner,sun4i-a10-sid"; |
2bad969f OS |
919 | reg = <0x01c23800 0x10>; |
920 | }; | |
921 | ||
57c8839c | 922 | rtp: rtp@01c25000 { |
40dd8f3b | 923 | compatible = "allwinner,sun4i-a10-ts"; |
57c8839c HG |
924 | reg = <0x01c25000 0x100>; |
925 | interrupts = <29>; | |
41e7afb1 | 926 | #thermal-sensor-cells = <0>; |
57c8839c HG |
927 | }; |
928 | ||
89b3c99f MR |
929 | uart0: serial@01c28000 { |
930 | compatible = "snps,dw-apb-uart"; | |
931 | reg = <0x01c28000 0x400>; | |
932 | interrupts = <1>; | |
933 | reg-shift = <2>; | |
934 | reg-io-width = <4>; | |
9ff49ec7 | 935 | clocks = <&apb1_gates 16>; |
89b3c99f MR |
936 | status = "disabled"; |
937 | }; | |
76f14d0a | 938 | |
69144e3b MR |
939 | uart1: serial@01c28400 { |
940 | compatible = "snps,dw-apb-uart"; | |
941 | reg = <0x01c28400 0x400>; | |
942 | interrupts = <2>; | |
943 | reg-shift = <2>; | |
944 | reg-io-width = <4>; | |
945 | clocks = <&apb1_gates 17>; | |
946 | status = "disabled"; | |
947 | }; | |
948 | ||
76f14d0a MR |
949 | uart2: serial@01c28800 { |
950 | compatible = "snps,dw-apb-uart"; | |
951 | reg = <0x01c28800 0x400>; | |
952 | interrupts = <3>; | |
953 | reg-shift = <2>; | |
954 | reg-io-width = <4>; | |
9ff49ec7 | 955 | clocks = <&apb1_gates 18>; |
76f14d0a MR |
956 | status = "disabled"; |
957 | }; | |
958 | ||
69144e3b MR |
959 | uart3: serial@01c28c00 { |
960 | compatible = "snps,dw-apb-uart"; | |
961 | reg = <0x01c28c00 0x400>; | |
962 | interrupts = <4>; | |
963 | reg-shift = <2>; | |
964 | reg-io-width = <4>; | |
965 | clocks = <&apb1_gates 19>; | |
966 | status = "disabled"; | |
967 | }; | |
968 | ||
76f14d0a MR |
969 | uart4: serial@01c29000 { |
970 | compatible = "snps,dw-apb-uart"; | |
971 | reg = <0x01c29000 0x400>; | |
972 | interrupts = <17>; | |
973 | reg-shift = <2>; | |
974 | reg-io-width = <4>; | |
9ff49ec7 | 975 | clocks = <&apb1_gates 20>; |
76f14d0a MR |
976 | status = "disabled"; |
977 | }; | |
978 | ||
979 | uart5: serial@01c29400 { | |
980 | compatible = "snps,dw-apb-uart"; | |
981 | reg = <0x01c29400 0x400>; | |
982 | interrupts = <18>; | |
983 | reg-shift = <2>; | |
984 | reg-io-width = <4>; | |
9ff49ec7 | 985 | clocks = <&apb1_gates 21>; |
76f14d0a MR |
986 | status = "disabled"; |
987 | }; | |
988 | ||
989 | uart6: serial@01c29800 { | |
990 | compatible = "snps,dw-apb-uart"; | |
991 | reg = <0x01c29800 0x400>; | |
992 | interrupts = <19>; | |
993 | reg-shift = <2>; | |
994 | reg-io-width = <4>; | |
9ff49ec7 | 995 | clocks = <&apb1_gates 22>; |
76f14d0a MR |
996 | status = "disabled"; |
997 | }; | |
998 | ||
999 | uart7: serial@01c29c00 { | |
1000 | compatible = "snps,dw-apb-uart"; | |
1001 | reg = <0x01c29c00 0x400>; | |
1002 | interrupts = <20>; | |
1003 | reg-shift = <2>; | |
1004 | reg-io-width = <4>; | |
9ff49ec7 | 1005 | clocks = <&apb1_gates 23>; |
76f14d0a MR |
1006 | status = "disabled"; |
1007 | }; | |
f1741fda MR |
1008 | |
1009 | i2c0: i2c@01c2ac00 { | |
d275545e | 1010 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
1011 | reg = <0x01c2ac00 0x400>; |
1012 | interrupts = <7>; | |
1013 | clocks = <&apb1_gates 0>; | |
f1741fda | 1014 | status = "disabled"; |
60bbe316 HG |
1015 | #address-cells = <1>; |
1016 | #size-cells = <0>; | |
f1741fda MR |
1017 | }; |
1018 | ||
1019 | i2c1: i2c@01c2b000 { | |
d275545e | 1020 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
1021 | reg = <0x01c2b000 0x400>; |
1022 | interrupts = <8>; | |
1023 | clocks = <&apb1_gates 1>; | |
f1741fda | 1024 | status = "disabled"; |
60bbe316 HG |
1025 | #address-cells = <1>; |
1026 | #size-cells = <0>; | |
f1741fda MR |
1027 | }; |
1028 | ||
1029 | i2c2: i2c@01c2b400 { | |
d275545e | 1030 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
1031 | reg = <0x01c2b400 0x400>; |
1032 | interrupts = <9>; | |
1033 | clocks = <&apb1_gates 2>; | |
f1741fda | 1034 | status = "disabled"; |
60bbe316 HG |
1035 | #address-cells = <1>; |
1036 | #size-cells = <0>; | |
f1741fda | 1037 | }; |
196654ae VP |
1038 | |
1039 | ps20: ps2@01c2a000 { | |
1040 | compatible = "allwinner,sun4i-a10-ps2"; | |
1041 | reg = <0x01c2a000 0x400>; | |
1042 | interrupts = <62>; | |
1043 | clocks = <&apb1_gates 6>; | |
1044 | status = "disabled"; | |
1045 | }; | |
1046 | ||
1047 | ps21: ps2@01c2a400 { | |
1048 | compatible = "allwinner,sun4i-a10-ps2"; | |
1049 | reg = <0x01c2a400 0x400>; | |
1050 | interrupts = <63>; | |
1051 | clocks = <&apb1_gates 7>; | |
1052 | status = "disabled"; | |
1053 | }; | |
874b4e45 | 1054 | }; |
7423d2d8 | 1055 | }; |