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7423d2d8 SR |
1 | /* |
2 | * Copyright 2012 Stefan Roese | |
3 | * Stefan Roese <sr@denx.de> | |
4 | * | |
033ba3d7 MR |
5 | * This file is dual-licensed: you can use it either under the terms |
6 | * of the GPL or the X11 license, at your option. Note that this dual | |
7 | * licensing only applies to this file, and not this project as a | |
8 | * whole. | |
7423d2d8 | 9 | * |
033ba3d7 MR |
10 | * a) This library is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of the | |
13 | * License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
033ba3d7 MR |
20 | * Or, alternatively, |
21 | * | |
22 | * b) Permission is hereby granted, free of charge, to any person | |
23 | * obtaining a copy of this software and associated documentation | |
24 | * files (the "Software"), to deal in the Software without | |
25 | * restriction, including without limitation the rights to use, | |
26 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
27 | * sell copies of the Software, and to permit persons to whom the | |
28 | * Software is furnished to do so, subject to the following | |
29 | * conditions: | |
30 | * | |
31 | * The above copyright notice and this permission notice shall be | |
32 | * included in all copies or substantial portions of the Software. | |
33 | * | |
34 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
35 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
36 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
37 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
38 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
39 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
40 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
41 | * OTHER DEALINGS IN THE SOFTWARE. | |
7423d2d8 SR |
42 | */ |
43 | ||
71455701 | 44 | #include "skeleton.dtsi" |
7423d2d8 | 45 | |
541ce2ca CYT |
46 | #include <dt-bindings/thermal/thermal.h> |
47 | ||
b516fa5d | 48 | #include <dt-bindings/clock/sun4i-a10-pll2.h> |
1f9f6a78 | 49 | #include <dt-bindings/dma/sun4i-a10.h> |
092a0c3b | 50 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
7423d2d8 SR |
51 | |
52 | / { | |
69144e3b MR |
53 | interrupt-parent = <&intc>; |
54 | ||
e751cce9 EL |
55 | aliases { |
56 | ethernet0 = &emac; | |
57 | }; | |
58 | ||
5790d4ee HG |
59 | chosen { |
60 | #address-cells = <1>; | |
61 | #size-cells = <1>; | |
62 | ranges; | |
63 | ||
a9f8cda3 | 64 | framebuffer@0 { |
d8cacaa3 MR |
65 | compatible = "allwinner,simple-framebuffer", |
66 | "simple-framebuffer"; | |
a9f8cda3 | 67 | allwinner,pipeline = "de_be0-lcd0-hdmi"; |
f5e1648c PL |
68 | clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>, |
69 | <&de_be0_clk>, <&tcon0_ch0_clk>, <&dram_gates 26>; | |
5790d4ee HG |
70 | status = "disabled"; |
71 | }; | |
8cedd662 HG |
72 | |
73 | framebuffer@1 { | |
d8cacaa3 MR |
74 | compatible = "allwinner,simple-framebuffer", |
75 | "simple-framebuffer"; | |
8cedd662 | 76 | allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; |
f5e1648c PL |
77 | clocks = <&ahb_gates 36>, <&ahb_gates 43>, |
78 | <&ahb_gates 44>, <&ahb_gates 46>, | |
79 | <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, | |
82f8582f | 80 | <&dram_gates 25>, <&dram_gates 26>; |
8cedd662 HG |
81 | status = "disabled"; |
82 | }; | |
fd18c7ea HG |
83 | |
84 | framebuffer@2 { | |
85 | compatible = "allwinner,simple-framebuffer", | |
86 | "simple-framebuffer"; | |
87 | allwinner,pipeline = "de_fe0-de_be0-lcd0"; | |
f5e1648c PL |
88 | clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>, |
89 | <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, | |
b3b630b2 | 90 | <&dram_gates 25>, <&dram_gates 26>; |
fd18c7ea HG |
91 | status = "disabled"; |
92 | }; | |
93 | ||
94 | framebuffer@3 { | |
95 | compatible = "allwinner,simple-framebuffer", | |
96 | "simple-framebuffer"; | |
97 | allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; | |
f5e1648c PL |
98 | clocks = <&ahb_gates 34>, <&ahb_gates 36>, |
99 | <&ahb_gates 44>, <&ahb_gates 46>, | |
100 | <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, | |
bec38aaa | 101 | <&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>; |
fd18c7ea HG |
102 | status = "disabled"; |
103 | }; | |
5790d4ee HG |
104 | }; |
105 | ||
69144e3b | 106 | cpus { |
8b2efa89 AB |
107 | #address-cells = <1>; |
108 | #size-cells = <0>; | |
7294be5d | 109 | cpu0: cpu@0 { |
14c44aa5 | 110 | device_type = "cpu"; |
69144e3b | 111 | compatible = "arm,cortex-a8"; |
14c44aa5 | 112 | reg = <0x0>; |
7294be5d CYT |
113 | clocks = <&cpu>; |
114 | clock-latency = <244144>; /* 8 32k periods */ | |
115 | operating-points = < | |
8358aada | 116 | /* kHz uV */ |
7294be5d | 117 | 1008000 1400000 |
8358aada MR |
118 | 912000 1350000 |
119 | 864000 1300000 | |
120 | 624000 1250000 | |
7294be5d CYT |
121 | >; |
122 | #cooling-cells = <2>; | |
123 | cooling-min-level = <0>; | |
370a9b5f | 124 | cooling-max-level = <3>; |
69144e3b MR |
125 | }; |
126 | }; | |
127 | ||
541ce2ca CYT |
128 | thermal-zones { |
129 | cpu_thermal { | |
130 | /* milliseconds */ | |
131 | polling-delay-passive = <250>; | |
132 | polling-delay = <1000>; | |
133 | thermal-sensors = <&rtp>; | |
134 | ||
135 | cooling-maps { | |
136 | map0 { | |
137 | trip = <&cpu_alert0>; | |
138 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
139 | }; | |
140 | }; | |
141 | ||
142 | trips { | |
143 | cpu_alert0: cpu_alert0 { | |
144 | /* milliCelsius */ | |
145 | temperature = <850000>; | |
146 | hysteresis = <2000>; | |
147 | type = "passive"; | |
148 | }; | |
149 | ||
150 | cpu_crit: cpu_crit { | |
151 | /* milliCelsius */ | |
152 | temperature = <100000>; | |
153 | hysteresis = <2000>; | |
154 | type = "critical"; | |
155 | }; | |
156 | }; | |
69144e3b MR |
157 | }; |
158 | }; | |
159 | ||
7423d2d8 SR |
160 | memory { |
161 | reg = <0x40000000 0x80000000>; | |
162 | }; | |
874b4e45 | 163 | |
69144e3b MR |
164 | clocks { |
165 | #address-cells = <1>; | |
166 | #size-cells = <1>; | |
167 | ranges; | |
168 | ||
169 | /* | |
170 | * This is a dummy clock, to be used as placeholder on | |
171 | * other mux clocks when a specific parent clock is not | |
172 | * yet implemented. It should be dropped when the driver | |
173 | * is complete. | |
174 | */ | |
175 | dummy: dummy { | |
176 | #clock-cells = <0>; | |
177 | compatible = "fixed-clock"; | |
178 | clock-frequency = <0>; | |
179 | }; | |
180 | ||
dfb12c0c | 181 | osc24M: clk@01c20050 { |
69144e3b | 182 | #clock-cells = <0>; |
bf6534a1 | 183 | compatible = "allwinner,sun4i-a10-osc-clk"; |
69144e3b | 184 | reg = <0x01c20050 0x4>; |
92fd6e06 | 185 | clock-frequency = <24000000>; |
dfb12c0c | 186 | clock-output-names = "osc24M"; |
69144e3b MR |
187 | }; |
188 | ||
be5f83ff PL |
189 | osc3M: osc3M_clk { |
190 | compatible = "fixed-factor-clock"; | |
191 | #clock-cells = <0>; | |
192 | clock-div = <8>; | |
193 | clock-mult = <1>; | |
194 | clocks = <&osc24M>; | |
195 | clock-output-names = "osc3M"; | |
196 | }; | |
197 | ||
dfb12c0c | 198 | osc32k: clk@0 { |
69144e3b MR |
199 | #clock-cells = <0>; |
200 | compatible = "fixed-clock"; | |
201 | clock-frequency = <32768>; | |
dfb12c0c | 202 | clock-output-names = "osc32k"; |
69144e3b MR |
203 | }; |
204 | ||
dfb12c0c | 205 | pll1: clk@01c20000 { |
69144e3b | 206 | #clock-cells = <0>; |
bf6534a1 | 207 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
69144e3b MR |
208 | reg = <0x01c20000 0x4>; |
209 | clocks = <&osc24M>; | |
dfb12c0c | 210 | clock-output-names = "pll1"; |
69144e3b MR |
211 | }; |
212 | ||
6ee93e12 MR |
213 | pll2: clk@01c20008 { |
214 | #clock-cells = <1>; | |
215 | compatible = "allwinner,sun4i-a10-pll2-clk"; | |
216 | reg = <0x01c20008 0x8>; | |
217 | clocks = <&osc24M>; | |
218 | clock-output-names = "pll2-1x", "pll2-2x", | |
219 | "pll2-4x", "pll2-8x"; | |
220 | }; | |
221 | ||
be5f83ff PL |
222 | pll3: clk@01c20010 { |
223 | #clock-cells = <0>; | |
224 | compatible = "allwinner,sun4i-a10-pll3-clk"; | |
225 | reg = <0x01c20010 0x4>; | |
226 | clocks = <&osc3M>; | |
227 | clock-output-names = "pll3"; | |
228 | }; | |
229 | ||
230 | pll3x2: pll3x2_clk { | |
231 | compatible = "fixed-factor-clock"; | |
232 | #clock-cells = <0>; | |
233 | clock-div = <1>; | |
234 | clock-mult = <2>; | |
235 | clocks = <&pll3>; | |
236 | clock-output-names = "pll3-2x"; | |
237 | }; | |
238 | ||
dfb12c0c | 239 | pll4: clk@01c20018 { |
ec5589f7 | 240 | #clock-cells = <0>; |
bf6534a1 | 241 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
ec5589f7 EL |
242 | reg = <0x01c20018 0x4>; |
243 | clocks = <&osc24M>; | |
dfb12c0c | 244 | clock-output-names = "pll4"; |
ec5589f7 EL |
245 | }; |
246 | ||
dfb12c0c | 247 | pll5: clk@01c20020 { |
c3e5e66b | 248 | #clock-cells = <1>; |
bf6534a1 | 249 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
c3e5e66b EL |
250 | reg = <0x01c20020 0x4>; |
251 | clocks = <&osc24M>; | |
252 | clock-output-names = "pll5_ddr", "pll5_other"; | |
253 | }; | |
254 | ||
dfb12c0c | 255 | pll6: clk@01c20028 { |
c3e5e66b | 256 | #clock-cells = <1>; |
bf6534a1 | 257 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
c3e5e66b EL |
258 | reg = <0x01c20028 0x4>; |
259 | clocks = <&osc24M>; | |
260 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
261 | }; | |
262 | ||
be5f83ff PL |
263 | pll7: clk@01c20030 { |
264 | #clock-cells = <0>; | |
265 | compatible = "allwinner,sun4i-a10-pll3-clk"; | |
266 | reg = <0x01c20030 0x4>; | |
267 | clocks = <&osc3M>; | |
268 | clock-output-names = "pll7"; | |
269 | }; | |
270 | ||
271 | pll7x2: pll7x2_clk { | |
272 | compatible = "fixed-factor-clock"; | |
273 | #clock-cells = <0>; | |
274 | clock-div = <1>; | |
275 | clock-mult = <2>; | |
276 | clocks = <&pll7>; | |
277 | clock-output-names = "pll7-2x"; | |
278 | }; | |
279 | ||
69144e3b MR |
280 | /* dummy is 200M */ |
281 | cpu: cpu@01c20054 { | |
282 | #clock-cells = <0>; | |
bf6534a1 | 283 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
69144e3b MR |
284 | reg = <0x01c20054 0x4>; |
285 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
dfb12c0c | 286 | clock-output-names = "cpu"; |
69144e3b MR |
287 | }; |
288 | ||
289 | axi: axi@01c20054 { | |
290 | #clock-cells = <0>; | |
bf6534a1 | 291 | compatible = "allwinner,sun4i-a10-axi-clk"; |
69144e3b MR |
292 | reg = <0x01c20054 0x4>; |
293 | clocks = <&cpu>; | |
dfb12c0c | 294 | clock-output-names = "axi"; |
69144e3b MR |
295 | }; |
296 | ||
dfb12c0c | 297 | axi_gates: clk@01c2005c { |
69144e3b | 298 | #clock-cells = <1>; |
bf6534a1 | 299 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
69144e3b MR |
300 | reg = <0x01c2005c 0x4>; |
301 | clocks = <&axi>; | |
a3854006 | 302 | clock-indices = <0>; |
69144e3b MR |
303 | clock-output-names = "axi_dram"; |
304 | }; | |
305 | ||
306 | ahb: ahb@01c20054 { | |
307 | #clock-cells = <0>; | |
bf6534a1 | 308 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
69144e3b MR |
309 | reg = <0x01c20054 0x4>; |
310 | clocks = <&axi>; | |
dfb12c0c | 311 | clock-output-names = "ahb"; |
69144e3b MR |
312 | }; |
313 | ||
dfb12c0c | 314 | ahb_gates: clk@01c20060 { |
69144e3b | 315 | #clock-cells = <1>; |
bf6534a1 | 316 | compatible = "allwinner,sun4i-a10-ahb-gates-clk"; |
69144e3b MR |
317 | reg = <0x01c20060 0x8>; |
318 | clocks = <&ahb>; | |
a3854006 MR |
319 | clock-indices = <0>, <1>, |
320 | <2>, <3>, | |
321 | <4>, <5>, <6>, | |
322 | <7>, <8>, <9>, | |
323 | <10>, <11>, <12>, | |
324 | <13>, <14>, <16>, | |
325 | <17>, <18>, <20>, | |
326 | <21>, <22>, <23>, | |
327 | <24>, <25>, <26>, | |
328 | <32>, <33>, <34>, | |
329 | <35>, <36>, <37>, | |
330 | <40>, <41>, <43>, | |
331 | <44>, <45>, | |
332 | <46>, <47>, | |
333 | <50>, <52>; | |
69144e3b | 334 | clock-output-names = "ahb_usb0", "ahb_ehci0", |
a3854006 MR |
335 | "ahb_ohci0", "ahb_ehci1", |
336 | "ahb_ohci1", "ahb_ss", "ahb_dma", | |
337 | "ahb_bist", "ahb_mmc0", "ahb_mmc1", | |
338 | "ahb_mmc2", "ahb_mmc3", "ahb_ms", | |
339 | "ahb_nand", "ahb_sdram", "ahb_ace", | |
340 | "ahb_emac", "ahb_ts", "ahb_spi0", | |
341 | "ahb_spi1", "ahb_spi2", "ahb_spi3", | |
342 | "ahb_pata", "ahb_sata", "ahb_gps", | |
343 | "ahb_ve", "ahb_tvd", "ahb_tve0", | |
344 | "ahb_tve1", "ahb_lcd0", "ahb_lcd1", | |
345 | "ahb_csi0", "ahb_csi1", "ahb_hdmi", | |
346 | "ahb_de_be0", "ahb_de_be1", | |
347 | "ahb_de_fe0", "ahb_de_fe1", | |
348 | "ahb_mp", "ahb_mali400"; | |
69144e3b MR |
349 | }; |
350 | ||
351 | apb0: apb0@01c20054 { | |
352 | #clock-cells = <0>; | |
bf6534a1 | 353 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
69144e3b MR |
354 | reg = <0x01c20054 0x4>; |
355 | clocks = <&ahb>; | |
dfb12c0c | 356 | clock-output-names = "apb0"; |
69144e3b MR |
357 | }; |
358 | ||
dfb12c0c | 359 | apb0_gates: clk@01c20068 { |
69144e3b | 360 | #clock-cells = <1>; |
bf6534a1 | 361 | compatible = "allwinner,sun4i-a10-apb0-gates-clk"; |
69144e3b MR |
362 | reg = <0x01c20068 0x4>; |
363 | clocks = <&apb0>; | |
a3854006 MR |
364 | clock-indices = <0>, <1>, |
365 | <2>, <3>, | |
366 | <5>, <6>, | |
367 | <7>, <10>; | |
69144e3b | 368 | clock-output-names = "apb0_codec", "apb0_spdif", |
a3854006 MR |
369 | "apb0_ac97", "apb0_iis", |
370 | "apb0_pio", "apb0_ir0", | |
371 | "apb0_ir1", "apb0_keypad"; | |
69144e3b MR |
372 | }; |
373 | ||
acbcc0f0 | 374 | apb1: clk@01c20058 { |
69144e3b | 375 | #clock-cells = <0>; |
bf6534a1 | 376 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
69144e3b | 377 | reg = <0x01c20058 0x4>; |
acbcc0f0 | 378 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
dfb12c0c | 379 | clock-output-names = "apb1"; |
69144e3b MR |
380 | }; |
381 | ||
dfb12c0c | 382 | apb1_gates: clk@01c2006c { |
69144e3b | 383 | #clock-cells = <1>; |
bf6534a1 | 384 | compatible = "allwinner,sun4i-a10-apb1-gates-clk"; |
69144e3b MR |
385 | reg = <0x01c2006c 0x4>; |
386 | clocks = <&apb1>; | |
a3854006 MR |
387 | clock-indices = <0>, <1>, |
388 | <2>, <4>, | |
389 | <5>, <6>, | |
390 | <7>, <16>, | |
391 | <17>, <18>, | |
392 | <19>, <20>, | |
393 | <21>, <22>, | |
394 | <23>; | |
69144e3b | 395 | clock-output-names = "apb1_i2c0", "apb1_i2c1", |
a3854006 MR |
396 | "apb1_i2c2", "apb1_can", |
397 | "apb1_scr", "apb1_ps20", | |
398 | "apb1_ps21", "apb1_uart0", | |
399 | "apb1_uart1", "apb1_uart2", | |
400 | "apb1_uart3", "apb1_uart4", | |
401 | "apb1_uart5", "apb1_uart6", | |
402 | "apb1_uart7"; | |
69144e3b | 403 | }; |
4b756ffb EL |
404 | |
405 | nand_clk: clk@01c20080 { | |
406 | #clock-cells = <0>; | |
bf6534a1 | 407 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
408 | reg = <0x01c20080 0x4>; |
409 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
410 | clock-output-names = "nand"; | |
411 | }; | |
412 | ||
413 | ms_clk: clk@01c20084 { | |
414 | #clock-cells = <0>; | |
bf6534a1 | 415 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
416 | reg = <0x01c20084 0x4>; |
417 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
418 | clock-output-names = "ms"; | |
419 | }; | |
420 | ||
421 | mmc0_clk: clk@01c20088 { | |
d8c3a392 MR |
422 | #clock-cells = <1>; |
423 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
424 | reg = <0x01c20088 0x4>; |
425 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
426 | clock-output-names = "mmc0", |
427 | "mmc0_output", | |
428 | "mmc0_sample"; | |
4b756ffb EL |
429 | }; |
430 | ||
431 | mmc1_clk: clk@01c2008c { | |
d8c3a392 MR |
432 | #clock-cells = <1>; |
433 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
434 | reg = <0x01c2008c 0x4>; |
435 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
436 | clock-output-names = "mmc1", |
437 | "mmc1_output", | |
438 | "mmc1_sample"; | |
4b756ffb EL |
439 | }; |
440 | ||
441 | mmc2_clk: clk@01c20090 { | |
d8c3a392 MR |
442 | #clock-cells = <1>; |
443 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
444 | reg = <0x01c20090 0x4>; |
445 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
446 | clock-output-names = "mmc2", |
447 | "mmc2_output", | |
448 | "mmc2_sample"; | |
4b756ffb EL |
449 | }; |
450 | ||
451 | mmc3_clk: clk@01c20094 { | |
d8c3a392 MR |
452 | #clock-cells = <1>; |
453 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
454 | reg = <0x01c20094 0x4>; |
455 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
456 | clock-output-names = "mmc3", |
457 | "mmc3_output", | |
458 | "mmc3_sample"; | |
4b756ffb EL |
459 | }; |
460 | ||
461 | ts_clk: clk@01c20098 { | |
462 | #clock-cells = <0>; | |
bf6534a1 | 463 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
464 | reg = <0x01c20098 0x4>; |
465 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
466 | clock-output-names = "ts"; | |
467 | }; | |
468 | ||
469 | ss_clk: clk@01c2009c { | |
470 | #clock-cells = <0>; | |
bf6534a1 | 471 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
472 | reg = <0x01c2009c 0x4>; |
473 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
474 | clock-output-names = "ss"; | |
475 | }; | |
476 | ||
477 | spi0_clk: clk@01c200a0 { | |
478 | #clock-cells = <0>; | |
bf6534a1 | 479 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
480 | reg = <0x01c200a0 0x4>; |
481 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
482 | clock-output-names = "spi0"; | |
483 | }; | |
484 | ||
485 | spi1_clk: clk@01c200a4 { | |
486 | #clock-cells = <0>; | |
bf6534a1 | 487 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
488 | reg = <0x01c200a4 0x4>; |
489 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
490 | clock-output-names = "spi1"; | |
491 | }; | |
492 | ||
493 | spi2_clk: clk@01c200a8 { | |
494 | #clock-cells = <0>; | |
bf6534a1 | 495 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
496 | reg = <0x01c200a8 0x4>; |
497 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
498 | clock-output-names = "spi2"; | |
499 | }; | |
500 | ||
501 | pata_clk: clk@01c200ac { | |
502 | #clock-cells = <0>; | |
bf6534a1 | 503 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
504 | reg = <0x01c200ac 0x4>; |
505 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
506 | clock-output-names = "pata"; | |
507 | }; | |
508 | ||
509 | ir0_clk: clk@01c200b0 { | |
510 | #clock-cells = <0>; | |
bf6534a1 | 511 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
512 | reg = <0x01c200b0 0x4>; |
513 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
514 | clock-output-names = "ir0"; | |
515 | }; | |
516 | ||
517 | ir1_clk: clk@01c200b4 { | |
518 | #clock-cells = <0>; | |
bf6534a1 | 519 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
520 | reg = <0x01c200b4 0x4>; |
521 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
522 | clock-output-names = "ir1"; | |
523 | }; | |
524 | ||
1010cd54 MC |
525 | spdif_clk: clk@01c200c0 { |
526 | #clock-cells = <0>; | |
527 | compatible = "allwinner,sun4i-a10-mod1-clk"; | |
528 | reg = <0x01c200c0 0x4>; | |
529 | clocks = <&pll2 SUN4I_A10_PLL2_8X>, | |
530 | <&pll2 SUN4I_A10_PLL2_4X>, | |
531 | <&pll2 SUN4I_A10_PLL2_2X>, | |
532 | <&pll2 SUN4I_A10_PLL2_1X>; | |
533 | clock-output-names = "spdif"; | |
534 | }; | |
535 | ||
0076c8bd RB |
536 | usb_clk: clk@01c200cc { |
537 | #clock-cells = <1>; | |
8358aada | 538 | #reset-cells = <1>; |
0076c8bd RB |
539 | compatible = "allwinner,sun4i-a10-usb-clk"; |
540 | reg = <0x01c200cc 0x4>; | |
541 | clocks = <&pll6 1>; | |
d8cacaa3 MR |
542 | clock-output-names = "usb_ohci0", "usb_ohci1", |
543 | "usb_phy"; | |
0076c8bd RB |
544 | }; |
545 | ||
4b756ffb EL |
546 | spi3_clk: clk@01c200d4 { |
547 | #clock-cells = <0>; | |
bf6534a1 | 548 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
549 | reg = <0x01c200d4 0x4>; |
550 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
551 | clock-output-names = "spi3"; | |
552 | }; | |
b516fa5d | 553 | |
82f8582f CYT |
554 | dram_gates: clk@01c20100 { |
555 | #clock-cells = <1>; | |
556 | compatible = "allwinner,sun4i-a10-dram-gates-clk"; | |
557 | reg = <0x01c20100 0x4>; | |
558 | clocks = <&pll5 0>; | |
559 | clock-indices = <0>, | |
560 | <1>, <2>, | |
561 | <3>, | |
562 | <4>, | |
563 | <5>, <6>, | |
564 | <15>, | |
565 | <24>, <25>, | |
566 | <26>, <27>, | |
567 | <28>, <29>; | |
568 | clock-output-names = "dram_ve", | |
569 | "dram_csi0", "dram_csi1", | |
570 | "dram_ts", | |
571 | "dram_tvd", | |
572 | "dram_tve0", "dram_tve1", | |
573 | "dram_output", | |
574 | "dram_de_fe1", "dram_de_fe0", | |
575 | "dram_de_be0", "dram_de_be1", | |
576 | "dram_de_mp", "dram_ace"; | |
577 | }; | |
578 | ||
f5e1648c PL |
579 | de_be0_clk: clk@01c20104 { |
580 | #clock-cells = <0>; | |
581 | #reset-cells = <0>; | |
582 | compatible = "allwinner,sun4i-a10-display-clk"; | |
583 | reg = <0x01c20104 0x4>; | |
584 | clocks = <&pll3>, <&pll7>, <&pll5 1>; | |
585 | clock-output-names = "de-be0"; | |
586 | }; | |
587 | ||
588 | de_be1_clk: clk@01c20108 { | |
589 | #clock-cells = <0>; | |
590 | #reset-cells = <0>; | |
591 | compatible = "allwinner,sun4i-a10-display-clk"; | |
592 | reg = <0x01c20108 0x4>; | |
593 | clocks = <&pll3>, <&pll7>, <&pll5 1>; | |
594 | clock-output-names = "de-be1"; | |
595 | }; | |
596 | ||
597 | de_fe0_clk: clk@01c2010c { | |
598 | #clock-cells = <0>; | |
599 | #reset-cells = <0>; | |
600 | compatible = "allwinner,sun4i-a10-display-clk"; | |
601 | reg = <0x01c2010c 0x4>; | |
602 | clocks = <&pll3>, <&pll7>, <&pll5 1>; | |
603 | clock-output-names = "de-fe0"; | |
604 | }; | |
605 | ||
606 | de_fe1_clk: clk@01c20110 { | |
607 | #clock-cells = <0>; | |
608 | #reset-cells = <0>; | |
609 | compatible = "allwinner,sun4i-a10-display-clk"; | |
610 | reg = <0x01c20110 0x4>; | |
611 | clocks = <&pll3>, <&pll7>, <&pll5 1>; | |
612 | clock-output-names = "de-fe1"; | |
613 | }; | |
614 | ||
615 | ||
616 | tcon0_ch0_clk: clk@01c20118 { | |
617 | #clock-cells = <0>; | |
618 | #reset-cells = <1>; | |
619 | compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; | |
620 | reg = <0x01c20118 0x4>; | |
621 | clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; | |
622 | clock-output-names = "tcon0-ch0-sclk"; | |
623 | ||
624 | }; | |
625 | ||
626 | tcon1_ch0_clk: clk@01c2011c { | |
627 | #clock-cells = <0>; | |
628 | #reset-cells = <1>; | |
629 | compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; | |
630 | reg = <0x01c2011c 0x4>; | |
631 | clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; | |
632 | clock-output-names = "tcon1-ch0-sclk"; | |
633 | ||
634 | }; | |
635 | ||
636 | tcon0_ch1_clk: clk@01c2012c { | |
637 | #clock-cells = <0>; | |
638 | compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; | |
639 | reg = <0x01c2012c 0x4>; | |
640 | clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; | |
641 | clock-output-names = "tcon0-ch1-sclk"; | |
642 | ||
643 | }; | |
644 | ||
645 | tcon1_ch1_clk: clk@01c20130 { | |
646 | #clock-cells = <0>; | |
647 | compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; | |
648 | reg = <0x01c20130 0x4>; | |
649 | clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; | |
650 | clock-output-names = "tcon1-ch1-sclk"; | |
651 | ||
652 | }; | |
653 | ||
1ccc4939 CYT |
654 | ve_clk: clk@01c2013c { |
655 | #clock-cells = <0>; | |
656 | #reset-cells = <0>; | |
657 | compatible = "allwinner,sun4i-a10-ve-clk"; | |
658 | reg = <0x01c2013c 0x4>; | |
659 | clocks = <&pll4>; | |
660 | clock-output-names = "ve"; | |
661 | }; | |
662 | ||
b516fa5d MR |
663 | codec_clk: clk@01c20140 { |
664 | #clock-cells = <0>; | |
665 | compatible = "allwinner,sun4i-a10-codec-clk"; | |
666 | reg = <0x01c20140 0x4>; | |
667 | clocks = <&pll2 SUN4I_A10_PLL2_1X>; | |
668 | clock-output-names = "codec"; | |
669 | }; | |
69144e3b MR |
670 | }; |
671 | ||
b74aec1a | 672 | soc@01c00000 { |
69144e3b MR |
673 | compatible = "simple-bus"; |
674 | #address-cells = <1>; | |
675 | #size-cells = <1>; | |
69144e3b MR |
676 | ranges; |
677 | ||
1fbc1517 MR |
678 | sram-controller@01c00000 { |
679 | compatible = "allwinner,sun4i-a10-sram-controller"; | |
680 | reg = <0x01c00000 0x30>; | |
681 | #address-cells = <1>; | |
682 | #size-cells = <1>; | |
683 | ranges; | |
684 | ||
685 | sram_a: sram@00000000 { | |
686 | compatible = "mmio-sram"; | |
687 | reg = <0x00000000 0xc000>; | |
688 | #address-cells = <1>; | |
689 | #size-cells = <1>; | |
690 | ranges = <0 0x00000000 0xc000>; | |
691 | ||
692 | emac_sram: sram-section@8000 { | |
693 | compatible = "allwinner,sun4i-a10-sram-a3-a4"; | |
694 | reg = <0x8000 0x4000>; | |
695 | status = "disabled"; | |
696 | }; | |
697 | }; | |
698 | ||
699 | sram_d: sram@00010000 { | |
700 | compatible = "mmio-sram"; | |
701 | reg = <0x00010000 0x1000>; | |
702 | #address-cells = <1>; | |
703 | #size-cells = <1>; | |
704 | ranges = <0 0x00010000 0x1000>; | |
705 | ||
706 | otg_sram: sram-section@0000 { | |
707 | compatible = "allwinner,sun4i-a10-sram-d"; | |
708 | reg = <0x0000 0x1000>; | |
709 | status = "disabled"; | |
710 | }; | |
711 | }; | |
712 | }; | |
713 | ||
1324f532 EL |
714 | dma: dma-controller@01c02000 { |
715 | compatible = "allwinner,sun4i-a10-dma"; | |
716 | reg = <0x01c02000 0x1000>; | |
717 | interrupts = <27>; | |
718 | clocks = <&ahb_gates 6>; | |
719 | #dma-cells = <2>; | |
720 | }; | |
721 | ||
65918e26 MR |
722 | spi0: spi@01c05000 { |
723 | compatible = "allwinner,sun4i-a10-spi"; | |
724 | reg = <0x01c05000 0x1000>; | |
725 | interrupts = <10>; | |
726 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
727 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
728 | dmas = <&dma SUN4I_DMA_DEDICATED 27>, |
729 | <&dma SUN4I_DMA_DEDICATED 26>; | |
4192ff81 | 730 | dma-names = "rx", "tx"; |
65918e26 MR |
731 | status = "disabled"; |
732 | #address-cells = <1>; | |
733 | #size-cells = <0>; | |
734 | }; | |
735 | ||
736 | spi1: spi@01c06000 { | |
737 | compatible = "allwinner,sun4i-a10-spi"; | |
738 | reg = <0x01c06000 0x1000>; | |
739 | interrupts = <11>; | |
740 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
741 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
742 | dmas = <&dma SUN4I_DMA_DEDICATED 9>, |
743 | <&dma SUN4I_DMA_DEDICATED 8>; | |
4192ff81 | 744 | dma-names = "rx", "tx"; |
65918e26 MR |
745 | status = "disabled"; |
746 | #address-cells = <1>; | |
747 | #size-cells = <0>; | |
748 | }; | |
749 | ||
e38afcb3 | 750 | emac: ethernet@01c0b000 { |
1c70e099 | 751 | compatible = "allwinner,sun4i-a10-emac"; |
e38afcb3 MR |
752 | reg = <0x01c0b000 0x1000>; |
753 | interrupts = <55>; | |
754 | clocks = <&ahb_gates 17>; | |
1fbc1517 | 755 | allwinner,sram = <&emac_sram 1>; |
e38afcb3 MR |
756 | status = "disabled"; |
757 | }; | |
758 | ||
92395f56 | 759 | mdio: mdio@01c0b080 { |
1c70e099 | 760 | compatible = "allwinner,sun4i-a10-mdio"; |
e38afcb3 MR |
761 | reg = <0x01c0b080 0x14>; |
762 | status = "disabled"; | |
763 | #address-cells = <1>; | |
764 | #size-cells = <0>; | |
765 | }; | |
766 | ||
b258b369 DL |
767 | mmc0: mmc@01c0f000 { |
768 | compatible = "allwinner,sun4i-a10-mmc"; | |
769 | reg = <0x01c0f000 0x1000>; | |
d8c3a392 MR |
770 | clocks = <&ahb_gates 8>, |
771 | <&mmc0_clk 0>, | |
772 | <&mmc0_clk 1>, | |
773 | <&mmc0_clk 2>; | |
774 | clock-names = "ahb", | |
775 | "mmc", | |
776 | "output", | |
777 | "sample"; | |
b258b369 DL |
778 | interrupts = <32>; |
779 | status = "disabled"; | |
4c1bb9c3 HG |
780 | #address-cells = <1>; |
781 | #size-cells = <0>; | |
b258b369 DL |
782 | }; |
783 | ||
784 | mmc1: mmc@01c10000 { | |
785 | compatible = "allwinner,sun4i-a10-mmc"; | |
786 | reg = <0x01c10000 0x1000>; | |
d8c3a392 MR |
787 | clocks = <&ahb_gates 9>, |
788 | <&mmc1_clk 0>, | |
789 | <&mmc1_clk 1>, | |
790 | <&mmc1_clk 2>; | |
791 | clock-names = "ahb", | |
792 | "mmc", | |
793 | "output", | |
794 | "sample"; | |
b258b369 DL |
795 | interrupts = <33>; |
796 | status = "disabled"; | |
4c1bb9c3 HG |
797 | #address-cells = <1>; |
798 | #size-cells = <0>; | |
b258b369 DL |
799 | }; |
800 | ||
801 | mmc2: mmc@01c11000 { | |
802 | compatible = "allwinner,sun4i-a10-mmc"; | |
803 | reg = <0x01c11000 0x1000>; | |
d8c3a392 MR |
804 | clocks = <&ahb_gates 10>, |
805 | <&mmc2_clk 0>, | |
806 | <&mmc2_clk 1>, | |
807 | <&mmc2_clk 2>; | |
808 | clock-names = "ahb", | |
809 | "mmc", | |
810 | "output", | |
811 | "sample"; | |
b258b369 DL |
812 | interrupts = <34>; |
813 | status = "disabled"; | |
4c1bb9c3 HG |
814 | #address-cells = <1>; |
815 | #size-cells = <0>; | |
b258b369 DL |
816 | }; |
817 | ||
818 | mmc3: mmc@01c12000 { | |
819 | compatible = "allwinner,sun4i-a10-mmc"; | |
820 | reg = <0x01c12000 0x1000>; | |
d8c3a392 MR |
821 | clocks = <&ahb_gates 11>, |
822 | <&mmc3_clk 0>, | |
823 | <&mmc3_clk 1>, | |
824 | <&mmc3_clk 2>; | |
825 | clock-names = "ahb", | |
826 | "mmc", | |
827 | "output", | |
828 | "sample"; | |
b258b369 DL |
829 | interrupts = <35>; |
830 | status = "disabled"; | |
4c1bb9c3 HG |
831 | #address-cells = <1>; |
832 | #size-cells = <0>; | |
b258b369 DL |
833 | }; |
834 | ||
ce65037f HG |
835 | usb_otg: usb@01c13000 { |
836 | compatible = "allwinner,sun4i-a10-musb"; | |
837 | reg = <0x01c13000 0x0400>; | |
838 | clocks = <&ahb_gates 0>; | |
839 | interrupts = <38>; | |
840 | interrupt-names = "mc"; | |
841 | phys = <&usbphy 0>; | |
842 | phy-names = "usb"; | |
843 | extcon = <&usbphy 0>; | |
844 | allwinner,sram = <&otg_sram 1>; | |
845 | status = "disabled"; | |
846 | }; | |
847 | ||
6ab1ce24 RB |
848 | usbphy: phy@01c13400 { |
849 | #phy-cells = <1>; | |
850 | compatible = "allwinner,sun4i-a10-usb-phy"; | |
851 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
852 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
853 | clocks = <&usb_clk 8>; | |
854 | clock-names = "usb_phy"; | |
4dba4185 CYT |
855 | resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; |
856 | reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; | |
6ab1ce24 RB |
857 | status = "disabled"; |
858 | }; | |
859 | ||
860 | ehci0: usb@01c14000 { | |
861 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
862 | reg = <0x01c14000 0x100>; | |
863 | interrupts = <39>; | |
864 | clocks = <&ahb_gates 1>; | |
865 | phys = <&usbphy 1>; | |
866 | phy-names = "usb"; | |
867 | status = "disabled"; | |
868 | }; | |
869 | ||
870 | ohci0: usb@01c14400 { | |
871 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
872 | reg = <0x01c14400 0x100>; | |
873 | interrupts = <64>; | |
874 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
875 | phys = <&usbphy 1>; | |
876 | phy-names = "usb"; | |
877 | status = "disabled"; | |
878 | }; | |
879 | ||
56ba8c58 LC |
880 | crypto: crypto-engine@01c15000 { |
881 | compatible = "allwinner,sun4i-a10-crypto"; | |
882 | reg = <0x01c15000 0x1000>; | |
883 | interrupts = <86>; | |
884 | clocks = <&ahb_gates 5>, <&ss_clk>; | |
885 | clock-names = "ahb", "mod"; | |
886 | }; | |
887 | ||
65918e26 MR |
888 | spi2: spi@01c17000 { |
889 | compatible = "allwinner,sun4i-a10-spi"; | |
890 | reg = <0x01c17000 0x1000>; | |
891 | interrupts = <12>; | |
892 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
893 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
894 | dmas = <&dma SUN4I_DMA_DEDICATED 29>, |
895 | <&dma SUN4I_DMA_DEDICATED 28>; | |
4192ff81 | 896 | dma-names = "rx", "tx"; |
65918e26 MR |
897 | status = "disabled"; |
898 | #address-cells = <1>; | |
899 | #size-cells = <0>; | |
900 | }; | |
901 | ||
248bd1e2 OS |
902 | ahci: sata@01c18000 { |
903 | compatible = "allwinner,sun4i-a10-ahci"; | |
904 | reg = <0x01c18000 0x1000>; | |
905 | interrupts = <56>; | |
906 | clocks = <&pll6 0>, <&ahb_gates 25>; | |
907 | status = "disabled"; | |
908 | }; | |
909 | ||
6ab1ce24 RB |
910 | ehci1: usb@01c1c000 { |
911 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
912 | reg = <0x01c1c000 0x100>; | |
913 | interrupts = <40>; | |
914 | clocks = <&ahb_gates 3>; | |
915 | phys = <&usbphy 2>; | |
916 | phy-names = "usb"; | |
917 | status = "disabled"; | |
918 | }; | |
919 | ||
920 | ohci1: usb@01c1c400 { | |
921 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
922 | reg = <0x01c1c400 0x100>; | |
923 | interrupts = <65>; | |
924 | clocks = <&usb_clk 7>, <&ahb_gates 4>; | |
925 | phys = <&usbphy 2>; | |
926 | phy-names = "usb"; | |
927 | status = "disabled"; | |
928 | }; | |
929 | ||
65918e26 MR |
930 | spi3: spi@01c1f000 { |
931 | compatible = "allwinner,sun4i-a10-spi"; | |
932 | reg = <0x01c1f000 0x1000>; | |
933 | interrupts = <50>; | |
934 | clocks = <&ahb_gates 23>, <&spi3_clk>; | |
935 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
936 | dmas = <&dma SUN4I_DMA_DEDICATED 31>, |
937 | <&dma SUN4I_DMA_DEDICATED 30>; | |
4192ff81 | 938 | dma-names = "rx", "tx"; |
65918e26 MR |
939 | status = "disabled"; |
940 | #address-cells = <1>; | |
941 | #size-cells = <0>; | |
942 | }; | |
943 | ||
69144e3b | 944 | intc: interrupt-controller@01c20400 { |
09504a7d | 945 | compatible = "allwinner,sun4i-a10-ic"; |
69144e3b MR |
946 | reg = <0x01c20400 0x400>; |
947 | interrupt-controller; | |
948 | #interrupt-cells = <1>; | |
949 | }; | |
950 | ||
e10911e1 | 951 | pio: pinctrl@01c20800 { |
874b4e45 MR |
952 | compatible = "allwinner,sun4i-a10-pinctrl"; |
953 | reg = <0x01c20800 0x400>; | |
39138bc6 | 954 | interrupts = <28>; |
36386d6e | 955 | clocks = <&apb0_gates 5>; |
e10911e1 | 956 | gpio-controller; |
39138bc6 | 957 | interrupt-controller; |
b03e0816 | 958 | #interrupt-cells = <3>; |
e10911e1 | 959 | #gpio-cells = <3>; |
581981be | 960 | |
1d5726e9 AB |
961 | pwm0_pins_a: pwm0@0 { |
962 | allwinner,pins = "PB2"; | |
963 | allwinner,function = "pwm"; | |
092a0c3b MR |
964 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
965 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1d5726e9 AB |
966 | }; |
967 | ||
968 | pwm1_pins_a: pwm1@0 { | |
969 | allwinner,pins = "PI3"; | |
970 | allwinner,function = "pwm"; | |
092a0c3b MR |
971 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
972 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1d5726e9 AB |
973 | }; |
974 | ||
581981be MR |
975 | uart0_pins_a: uart0@0 { |
976 | allwinner,pins = "PB22", "PB23"; | |
977 | allwinner,function = "uart0"; | |
092a0c3b MR |
978 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
979 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
581981be MR |
980 | }; |
981 | ||
982 | uart0_pins_b: uart0@1 { | |
983 | allwinner,pins = "PF2", "PF4"; | |
984 | allwinner,function = "uart0"; | |
092a0c3b MR |
985 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
986 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
581981be MR |
987 | }; |
988 | ||
989 | uart1_pins_a: uart1@0 { | |
990 | allwinner,pins = "PA10", "PA11"; | |
991 | allwinner,function = "uart1"; | |
092a0c3b MR |
992 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
993 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
581981be | 994 | }; |
27cce4ff MR |
995 | |
996 | i2c0_pins_a: i2c0@0 { | |
997 | allwinner,pins = "PB0", "PB1"; | |
998 | allwinner,function = "i2c0"; | |
092a0c3b MR |
999 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1000 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
27cce4ff MR |
1001 | }; |
1002 | ||
1003 | i2c1_pins_a: i2c1@0 { | |
1004 | allwinner,pins = "PB18", "PB19"; | |
1005 | allwinner,function = "i2c1"; | |
092a0c3b MR |
1006 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1007 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
27cce4ff MR |
1008 | }; |
1009 | ||
1010 | i2c2_pins_a: i2c2@0 { | |
1011 | allwinner,pins = "PB20", "PB21"; | |
1012 | allwinner,function = "i2c2"; | |
092a0c3b MR |
1013 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1014 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
27cce4ff | 1015 | }; |
496322bc | 1016 | |
b21da664 MR |
1017 | emac_pins_a: emac0@0 { |
1018 | allwinner,pins = "PA0", "PA1", "PA2", | |
1019 | "PA3", "PA4", "PA5", "PA6", | |
1020 | "PA7", "PA8", "PA9", "PA10", | |
1021 | "PA11", "PA12", "PA13", "PA14", | |
1022 | "PA15", "PA16"; | |
1023 | allwinner,function = "emac"; | |
092a0c3b MR |
1024 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1025 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
b21da664 | 1026 | }; |
b5f86a3a HG |
1027 | |
1028 | mmc0_pins_a: mmc0@0 { | |
d8cacaa3 MR |
1029 | allwinner,pins = "PF0", "PF1", "PF2", |
1030 | "PF3", "PF4", "PF5"; | |
b5f86a3a | 1031 | allwinner,function = "mmc0"; |
092a0c3b MR |
1032 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
1033 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
b5f86a3a HG |
1034 | }; |
1035 | ||
1036 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { | |
1037 | allwinner,pins = "PH1"; | |
1038 | allwinner,function = "gpio_in"; | |
092a0c3b MR |
1039 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1040 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
b5f86a3a | 1041 | }; |
a4e1099a | 1042 | |
469a22e6 MC |
1043 | ir0_rx_pins_a: ir0@0 { |
1044 | allwinner,pins = "PB4"; | |
a4e1099a | 1045 | allwinner,function = "ir0"; |
092a0c3b MR |
1046 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1047 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
a4e1099a HG |
1048 | }; |
1049 | ||
469a22e6 MC |
1050 | ir0_tx_pins_a: ir0@1 { |
1051 | allwinner,pins = "PB3"; | |
1052 | allwinner,function = "ir0"; | |
1053 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1054 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1055 | }; | |
1056 | ||
1057 | ir1_rx_pins_a: ir1@0 { | |
1058 | allwinner,pins = "PB23"; | |
1059 | allwinner,function = "ir1"; | |
1060 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1061 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1062 | }; | |
1063 | ||
1064 | ir1_tx_pins_a: ir1@1 { | |
1065 | allwinner,pins = "PB22"; | |
a4e1099a | 1066 | allwinner,function = "ir1"; |
092a0c3b MR |
1067 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1068 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
a4e1099a | 1069 | }; |
ec66d0bb AG |
1070 | |
1071 | spi0_pins_a: spi0@0 { | |
f3022c6c MR |
1072 | allwinner,pins = "PI11", "PI12", "PI13"; |
1073 | allwinner,function = "spi0"; | |
1074 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1075 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1076 | }; | |
1077 | ||
1078 | spi0_cs0_pins_a: spi0_cs0@0 { | |
1079 | allwinner,pins = "PI10"; | |
ec66d0bb | 1080 | allwinner,function = "spi0"; |
092a0c3b MR |
1081 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1082 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb AG |
1083 | }; |
1084 | ||
1085 | spi1_pins_a: spi1@0 { | |
f3022c6c MR |
1086 | allwinner,pins = "PI17", "PI18", "PI19"; |
1087 | allwinner,function = "spi1"; | |
1088 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1089 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1090 | }; | |
1091 | ||
1092 | spi1_cs0_pins_a: spi1_cs0@0 { | |
1093 | allwinner,pins = "PI16"; | |
ec66d0bb | 1094 | allwinner,function = "spi1"; |
092a0c3b MR |
1095 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1096 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb AG |
1097 | }; |
1098 | ||
1099 | spi2_pins_a: spi2@0 { | |
f3022c6c | 1100 | allwinner,pins = "PC20", "PC21", "PC22"; |
ec66d0bb | 1101 | allwinner,function = "spi2"; |
092a0c3b MR |
1102 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1103 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb AG |
1104 | }; |
1105 | ||
1106 | spi2_pins_b: spi2@1 { | |
f3022c6c MR |
1107 | allwinner,pins = "PB15", "PB16", "PB17"; |
1108 | allwinner,function = "spi2"; | |
1109 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1110 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1111 | }; | |
1112 | ||
1113 | spi2_cs0_pins_a: spi2_cs0@0 { | |
1114 | allwinner,pins = "PC19"; | |
1115 | allwinner,function = "spi2"; | |
1116 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1117 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1118 | }; | |
1119 | ||
1120 | spi2_cs0_pins_b: spi2_cs0@1 { | |
1121 | allwinner,pins = "PB14"; | |
ec66d0bb | 1122 | allwinner,function = "spi2"; |
092a0c3b MR |
1123 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1124 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb | 1125 | }; |
1e8d1567 VP |
1126 | |
1127 | ps20_pins_a: ps20@0 { | |
1128 | allwinner,pins = "PI20", "PI21"; | |
1129 | allwinner,function = "ps2"; | |
1130 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1131 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1132 | }; | |
1133 | ||
1134 | ps21_pins_a: ps21@0 { | |
1135 | allwinner,pins = "PH12", "PH13"; | |
1136 | allwinner,function = "ps2"; | |
1137 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1138 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
a4e1099a | 1139 | }; |
79f969f0 MC |
1140 | |
1141 | spdif_tx_pins_a: spdif@0 { | |
1142 | allwinner,pins = "PB13"; | |
1143 | allwinner,function = "spdif"; | |
1144 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1145 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
1146 | }; | |
874b4e45 | 1147 | }; |
89b3c99f | 1148 | |
69144e3b | 1149 | timer@01c20c00 { |
b4f26440 | 1150 | compatible = "allwinner,sun4i-a10-timer"; |
69144e3b MR |
1151 | reg = <0x01c20c00 0x90>; |
1152 | interrupts = <22>; | |
1153 | clocks = <&osc24M>; | |
1154 | }; | |
1155 | ||
1156 | wdt: watchdog@01c20c90 { | |
ca5d04d9 | 1157 | compatible = "allwinner,sun4i-a10-wdt"; |
69144e3b MR |
1158 | reg = <0x01c20c90 0x10>; |
1159 | }; | |
1160 | ||
b5d905c7 | 1161 | rtc: rtc@01c20d00 { |
5fc4bc89 | 1162 | compatible = "allwinner,sun4i-a10-rtc"; |
b5d905c7 CC |
1163 | reg = <0x01c20d00 0x20>; |
1164 | interrupts = <24>; | |
1165 | }; | |
1166 | ||
4b57a395 AB |
1167 | pwm: pwm@01c20e00 { |
1168 | compatible = "allwinner,sun4i-a10-pwm"; | |
1169 | reg = <0x01c20e00 0xc>; | |
1170 | clocks = <&osc24M>; | |
1171 | #pwm-cells = <3>; | |
1172 | status = "disabled"; | |
1173 | }; | |
1174 | ||
166db83e MC |
1175 | spdif: spdif@01c21000 { |
1176 | #sound-dai-cells = <0>; | |
1177 | compatible = "allwinner,sun4i-a10-spdif"; | |
1178 | reg = <0x01c21000 0x400>; | |
1179 | interrupts = <13>; | |
1180 | clocks = <&apb0_gates 1>, <&spdif_clk>; | |
1181 | clock-names = "apb", "spdif"; | |
1182 | dmas = <&dma SUN4I_DMA_NORMAL 2>, | |
1183 | <&dma SUN4I_DMA_NORMAL 2>; | |
1184 | dma-names = "rx", "tx"; | |
1185 | status = "disabled"; | |
1186 | }; | |
1187 | ||
a4e1099a HG |
1188 | ir0: ir@01c21800 { |
1189 | compatible = "allwinner,sun4i-a10-ir"; | |
1190 | clocks = <&apb0_gates 6>, <&ir0_clk>; | |
1191 | clock-names = "apb", "ir"; | |
1192 | interrupts = <5>; | |
1193 | reg = <0x01c21800 0x40>; | |
1194 | status = "disabled"; | |
1195 | }; | |
1196 | ||
1197 | ir1: ir@01c21c00 { | |
1198 | compatible = "allwinner,sun4i-a10-ir"; | |
1199 | clocks = <&apb0_gates 7>, <&ir1_clk>; | |
1200 | clock-names = "apb", "ir"; | |
1201 | interrupts = <6>; | |
1202 | reg = <0x01c21c00 0x40>; | |
1203 | status = "disabled"; | |
1204 | }; | |
1205 | ||
b0512e15 HG |
1206 | lradc: lradc@01c22800 { |
1207 | compatible = "allwinner,sun4i-a10-lradc-keys"; | |
1208 | reg = <0x01c22800 0x100>; | |
1209 | interrupts = <31>; | |
1210 | status = "disabled"; | |
1211 | }; | |
1212 | ||
bcf88450 MC |
1213 | codec: codec@01c22c00 { |
1214 | #sound-dai-cells = <0>; | |
1215 | compatible = "allwinner,sun4i-a10-codec"; | |
1216 | reg = <0x01c22c00 0x40>; | |
1217 | interrupts = <30>; | |
1218 | clocks = <&apb0_gates 0>, <&codec_clk>; | |
1219 | clock-names = "apb", "codec"; | |
1220 | dmas = <&dma SUN4I_DMA_NORMAL 19>, | |
1221 | <&dma SUN4I_DMA_NORMAL 19>; | |
1222 | dma-names = "rx", "tx"; | |
1223 | status = "disabled"; | |
1224 | }; | |
1225 | ||
2bad969f | 1226 | sid: eeprom@01c23800 { |
043d56ee | 1227 | compatible = "allwinner,sun4i-a10-sid"; |
2bad969f OS |
1228 | reg = <0x01c23800 0x10>; |
1229 | }; | |
1230 | ||
57c8839c | 1231 | rtp: rtp@01c25000 { |
40dd8f3b | 1232 | compatible = "allwinner,sun4i-a10-ts"; |
57c8839c HG |
1233 | reg = <0x01c25000 0x100>; |
1234 | interrupts = <29>; | |
41e7afb1 | 1235 | #thermal-sensor-cells = <0>; |
57c8839c HG |
1236 | }; |
1237 | ||
89b3c99f MR |
1238 | uart0: serial@01c28000 { |
1239 | compatible = "snps,dw-apb-uart"; | |
1240 | reg = <0x01c28000 0x400>; | |
1241 | interrupts = <1>; | |
1242 | reg-shift = <2>; | |
1243 | reg-io-width = <4>; | |
9ff49ec7 | 1244 | clocks = <&apb1_gates 16>; |
89b3c99f MR |
1245 | status = "disabled"; |
1246 | }; | |
76f14d0a | 1247 | |
69144e3b MR |
1248 | uart1: serial@01c28400 { |
1249 | compatible = "snps,dw-apb-uart"; | |
1250 | reg = <0x01c28400 0x400>; | |
1251 | interrupts = <2>; | |
1252 | reg-shift = <2>; | |
1253 | reg-io-width = <4>; | |
1254 | clocks = <&apb1_gates 17>; | |
1255 | status = "disabled"; | |
1256 | }; | |
1257 | ||
76f14d0a MR |
1258 | uart2: serial@01c28800 { |
1259 | compatible = "snps,dw-apb-uart"; | |
1260 | reg = <0x01c28800 0x400>; | |
1261 | interrupts = <3>; | |
1262 | reg-shift = <2>; | |
1263 | reg-io-width = <4>; | |
9ff49ec7 | 1264 | clocks = <&apb1_gates 18>; |
76f14d0a MR |
1265 | status = "disabled"; |
1266 | }; | |
1267 | ||
69144e3b MR |
1268 | uart3: serial@01c28c00 { |
1269 | compatible = "snps,dw-apb-uart"; | |
1270 | reg = <0x01c28c00 0x400>; | |
1271 | interrupts = <4>; | |
1272 | reg-shift = <2>; | |
1273 | reg-io-width = <4>; | |
1274 | clocks = <&apb1_gates 19>; | |
1275 | status = "disabled"; | |
1276 | }; | |
1277 | ||
76f14d0a MR |
1278 | uart4: serial@01c29000 { |
1279 | compatible = "snps,dw-apb-uart"; | |
1280 | reg = <0x01c29000 0x400>; | |
1281 | interrupts = <17>; | |
1282 | reg-shift = <2>; | |
1283 | reg-io-width = <4>; | |
9ff49ec7 | 1284 | clocks = <&apb1_gates 20>; |
76f14d0a MR |
1285 | status = "disabled"; |
1286 | }; | |
1287 | ||
1288 | uart5: serial@01c29400 { | |
1289 | compatible = "snps,dw-apb-uart"; | |
1290 | reg = <0x01c29400 0x400>; | |
1291 | interrupts = <18>; | |
1292 | reg-shift = <2>; | |
1293 | reg-io-width = <4>; | |
9ff49ec7 | 1294 | clocks = <&apb1_gates 21>; |
76f14d0a MR |
1295 | status = "disabled"; |
1296 | }; | |
1297 | ||
1298 | uart6: serial@01c29800 { | |
1299 | compatible = "snps,dw-apb-uart"; | |
1300 | reg = <0x01c29800 0x400>; | |
1301 | interrupts = <19>; | |
1302 | reg-shift = <2>; | |
1303 | reg-io-width = <4>; | |
9ff49ec7 | 1304 | clocks = <&apb1_gates 22>; |
76f14d0a MR |
1305 | status = "disabled"; |
1306 | }; | |
1307 | ||
1308 | uart7: serial@01c29c00 { | |
1309 | compatible = "snps,dw-apb-uart"; | |
1310 | reg = <0x01c29c00 0x400>; | |
1311 | interrupts = <20>; | |
1312 | reg-shift = <2>; | |
1313 | reg-io-width = <4>; | |
9ff49ec7 | 1314 | clocks = <&apb1_gates 23>; |
76f14d0a MR |
1315 | status = "disabled"; |
1316 | }; | |
f1741fda MR |
1317 | |
1318 | i2c0: i2c@01c2ac00 { | |
d275545e | 1319 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
1320 | reg = <0x01c2ac00 0x400>; |
1321 | interrupts = <7>; | |
1322 | clocks = <&apb1_gates 0>; | |
f1741fda | 1323 | status = "disabled"; |
60bbe316 HG |
1324 | #address-cells = <1>; |
1325 | #size-cells = <0>; | |
f1741fda MR |
1326 | }; |
1327 | ||
1328 | i2c1: i2c@01c2b000 { | |
d275545e | 1329 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
1330 | reg = <0x01c2b000 0x400>; |
1331 | interrupts = <8>; | |
1332 | clocks = <&apb1_gates 1>; | |
f1741fda | 1333 | status = "disabled"; |
60bbe316 HG |
1334 | #address-cells = <1>; |
1335 | #size-cells = <0>; | |
f1741fda MR |
1336 | }; |
1337 | ||
1338 | i2c2: i2c@01c2b400 { | |
d275545e | 1339 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
1340 | reg = <0x01c2b400 0x400>; |
1341 | interrupts = <9>; | |
1342 | clocks = <&apb1_gates 2>; | |
f1741fda | 1343 | status = "disabled"; |
60bbe316 HG |
1344 | #address-cells = <1>; |
1345 | #size-cells = <0>; | |
f1741fda | 1346 | }; |
196654ae VP |
1347 | |
1348 | ps20: ps2@01c2a000 { | |
1349 | compatible = "allwinner,sun4i-a10-ps2"; | |
1350 | reg = <0x01c2a000 0x400>; | |
1351 | interrupts = <62>; | |
1352 | clocks = <&apb1_gates 6>; | |
1353 | status = "disabled"; | |
1354 | }; | |
1355 | ||
1356 | ps21: ps2@01c2a400 { | |
1357 | compatible = "allwinner,sun4i-a10-ps2"; | |
1358 | reg = <0x01c2a400 0x400>; | |
1359 | interrupts = <63>; | |
1360 | clocks = <&apb1_gates 7>; | |
1361 | status = "disabled"; | |
1362 | }; | |
874b4e45 | 1363 | }; |
7423d2d8 | 1364 | }; |