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7423d2d8 SR |
1 | /* |
2 | * Copyright 2012 Stefan Roese | |
3 | * Stefan Roese <sr@denx.de> | |
4 | * | |
033ba3d7 MR |
5 | * This file is dual-licensed: you can use it either under the terms |
6 | * of the GPL or the X11 license, at your option. Note that this dual | |
7 | * licensing only applies to this file, and not this project as a | |
8 | * whole. | |
7423d2d8 | 9 | * |
033ba3d7 MR |
10 | * a) This library is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of the | |
13 | * License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
033ba3d7 MR |
20 | * Or, alternatively, |
21 | * | |
22 | * b) Permission is hereby granted, free of charge, to any person | |
23 | * obtaining a copy of this software and associated documentation | |
24 | * files (the "Software"), to deal in the Software without | |
25 | * restriction, including without limitation the rights to use, | |
26 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
27 | * sell copies of the Software, and to permit persons to whom the | |
28 | * Software is furnished to do so, subject to the following | |
29 | * conditions: | |
30 | * | |
31 | * The above copyright notice and this permission notice shall be | |
32 | * included in all copies or substantial portions of the Software. | |
33 | * | |
34 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
35 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
36 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
37 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
38 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
39 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
40 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
41 | * OTHER DEALINGS IN THE SOFTWARE. | |
7423d2d8 SR |
42 | */ |
43 | ||
541ce2ca | 44 | #include <dt-bindings/thermal/thermal.h> |
1f9f6a78 | 45 | #include <dt-bindings/dma/sun4i-a10.h> |
41193869 PL |
46 | #include <dt-bindings/clock/sun4i-a10-ccu.h> |
47 | #include <dt-bindings/reset/sun4i-a10-ccu.h> | |
7423d2d8 SR |
48 | |
49 | / { | |
6ab3cf04 MR |
50 | #address-cells = <1>; |
51 | #size-cells = <1>; | |
69144e3b MR |
52 | interrupt-parent = <&intc>; |
53 | ||
e751cce9 EL |
54 | aliases { |
55 | ethernet0 = &emac; | |
56 | }; | |
57 | ||
5790d4ee HG |
58 | chosen { |
59 | #address-cells = <1>; | |
60 | #size-cells = <1>; | |
61 | ranges; | |
62 | ||
71299dd4 | 63 | framebuffer-lcd0-hdmi { |
d8cacaa3 MR |
64 | compatible = "allwinner,simple-framebuffer", |
65 | "simple-framebuffer"; | |
a9f8cda3 | 66 | allwinner,pipeline = "de_be0-lcd0-hdmi"; |
41193869 PL |
67 | clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, |
68 | <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, | |
69 | <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>; | |
5790d4ee HG |
70 | status = "disabled"; |
71 | }; | |
8cedd662 | 72 | |
71299dd4 | 73 | framebuffer-fe0-lcd0-hdmi { |
d8cacaa3 MR |
74 | compatible = "allwinner,simple-framebuffer", |
75 | "simple-framebuffer"; | |
8cedd662 | 76 | allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; |
41193869 PL |
77 | clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, |
78 | <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, | |
590b0c0c | 79 | <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, |
41193869 PL |
80 | <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>, |
81 | <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; | |
8cedd662 HG |
82 | status = "disabled"; |
83 | }; | |
fd18c7ea | 84 | |
71299dd4 | 85 | framebuffer-fe0-lcd0 { |
fd18c7ea HG |
86 | compatible = "allwinner,simple-framebuffer", |
87 | "simple-framebuffer"; | |
88 | allwinner,pipeline = "de_fe0-de_be0-lcd0"; | |
41193869 PL |
89 | clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, |
90 | <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>, | |
590b0c0c | 91 | <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>, |
41193869 | 92 | <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; |
fd18c7ea HG |
93 | status = "disabled"; |
94 | }; | |
95 | ||
71299dd4 | 96 | framebuffer-fe0-lcd0-tve0 { |
fd18c7ea HG |
97 | compatible = "allwinner,simple-framebuffer", |
98 | "simple-framebuffer"; | |
99 | allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; | |
41193869 PL |
100 | clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, |
101 | <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, | |
590b0c0c | 102 | <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, |
41193869 PL |
103 | <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>, |
104 | <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; | |
fd18c7ea HG |
105 | status = "disabled"; |
106 | }; | |
5790d4ee HG |
107 | }; |
108 | ||
69144e3b | 109 | cpus { |
8b2efa89 AB |
110 | #address-cells = <1>; |
111 | #size-cells = <0>; | |
7294be5d | 112 | cpu0: cpu@0 { |
14c44aa5 | 113 | device_type = "cpu"; |
69144e3b | 114 | compatible = "arm,cortex-a8"; |
14c44aa5 | 115 | reg = <0x0>; |
41193869 | 116 | clocks = <&ccu CLK_CPU>; |
7294be5d CYT |
117 | clock-latency = <244144>; /* 8 32k periods */ |
118 | operating-points = < | |
8358aada | 119 | /* kHz uV */ |
7294be5d | 120 | 1008000 1400000 |
8358aada MR |
121 | 912000 1350000 |
122 | 864000 1300000 | |
123 | 624000 1250000 | |
7294be5d CYT |
124 | >; |
125 | #cooling-cells = <2>; | |
69144e3b MR |
126 | }; |
127 | }; | |
128 | ||
541ce2ca | 129 | thermal-zones { |
124d19dc | 130 | cpu-thermal { |
541ce2ca CYT |
131 | /* milliseconds */ |
132 | polling-delay-passive = <250>; | |
133 | polling-delay = <1000>; | |
134 | thermal-sensors = <&rtp>; | |
135 | ||
136 | cooling-maps { | |
137 | map0 { | |
138 | trip = <&cpu_alert0>; | |
139 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
140 | }; | |
141 | }; | |
142 | ||
143 | trips { | |
124d19dc | 144 | cpu_alert0: cpu-alert0 { |
541ce2ca CYT |
145 | /* milliCelsius */ |
146 | temperature = <850000>; | |
147 | hysteresis = <2000>; | |
148 | type = "passive"; | |
149 | }; | |
150 | ||
124d19dc | 151 | cpu_crit: cpu-crit { |
541ce2ca CYT |
152 | /* milliCelsius */ |
153 | temperature = <100000>; | |
154 | hysteresis = <2000>; | |
155 | type = "critical"; | |
156 | }; | |
157 | }; | |
69144e3b MR |
158 | }; |
159 | }; | |
160 | ||
69144e3b MR |
161 | clocks { |
162 | #address-cells = <1>; | |
163 | #size-cells = <1>; | |
164 | ranges; | |
165 | ||
5c58319f | 166 | osc24M: clk-24M { |
69144e3b | 167 | #clock-cells = <0>; |
41193869 | 168 | compatible = "fixed-clock"; |
92fd6e06 | 169 | clock-frequency = <24000000>; |
dfb12c0c | 170 | clock-output-names = "osc24M"; |
69144e3b MR |
171 | }; |
172 | ||
5c58319f | 173 | osc32k: clk-32k { |
69144e3b MR |
174 | #clock-cells = <0>; |
175 | compatible = "fixed-clock"; | |
176 | clock-frequency = <32768>; | |
dfb12c0c | 177 | clock-output-names = "osc32k"; |
69144e3b | 178 | }; |
69144e3b MR |
179 | }; |
180 | ||
0df4cf33 CYT |
181 | de: display-engine { |
182 | compatible = "allwinner,sun4i-a10-display-engine"; | |
183 | allwinner,pipelines = <&fe0>, <&fe1>; | |
184 | status = "disabled"; | |
185 | }; | |
186 | ||
7e345d25 HG |
187 | pmu { |
188 | compatible = "arm,cortex-a8-pmu"; | |
189 | interrupts = <3>; | |
190 | }; | |
191 | ||
5949bc56 PK |
192 | reserved-memory { |
193 | #address-cells = <1>; | |
194 | #size-cells = <1>; | |
195 | ranges; | |
196 | ||
197 | /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ | |
198 | default-pool { | |
199 | compatible = "shared-dma-pool"; | |
200 | size = <0x6000000>; | |
201 | alloc-ranges = <0x4a000000 0x6000000>; | |
202 | reusable; | |
203 | linux,cma-default; | |
204 | }; | |
205 | }; | |
206 | ||
39f8a71b | 207 | soc { |
69144e3b MR |
208 | compatible = "simple-bus"; |
209 | #address-cells = <1>; | |
210 | #size-cells = <1>; | |
69144e3b MR |
211 | ranges; |
212 | ||
37fb1f8d PK |
213 | system-control@1c00000 { |
214 | compatible = "allwinner,sun4i-a10-system-control"; | |
1fbc1517 MR |
215 | reg = <0x01c00000 0x30>; |
216 | #address-cells = <1>; | |
217 | #size-cells = <1>; | |
218 | ranges; | |
219 | ||
5841f6c0 | 220 | sram_a: sram@0 { |
1fbc1517 MR |
221 | compatible = "mmio-sram"; |
222 | reg = <0x00000000 0xc000>; | |
223 | #address-cells = <1>; | |
224 | #size-cells = <1>; | |
225 | ranges = <0 0x00000000 0xc000>; | |
226 | ||
227 | emac_sram: sram-section@8000 { | |
228 | compatible = "allwinner,sun4i-a10-sram-a3-a4"; | |
229 | reg = <0x8000 0x4000>; | |
230 | status = "disabled"; | |
231 | }; | |
232 | }; | |
233 | ||
5841f6c0 | 234 | sram_d: sram@10000 { |
1fbc1517 MR |
235 | compatible = "mmio-sram"; |
236 | reg = <0x00010000 0x1000>; | |
237 | #address-cells = <1>; | |
238 | #size-cells = <1>; | |
239 | ranges = <0 0x00010000 0x1000>; | |
240 | ||
5841f6c0 | 241 | otg_sram: sram-section@0 { |
1fbc1517 MR |
242 | compatible = "allwinner,sun4i-a10-sram-d"; |
243 | reg = <0x0000 0x1000>; | |
244 | status = "disabled"; | |
245 | }; | |
246 | }; | |
890c5067 PK |
247 | |
248 | sram_c: sram@1d00000 { | |
249 | compatible = "mmio-sram"; | |
250 | reg = <0x01d00000 0xd0000>; | |
251 | #address-cells = <1>; | |
252 | #size-cells = <1>; | |
253 | ranges = <0 0x01d00000 0xd0000>; | |
254 | ||
255 | ve_sram: sram-section@0 { | |
256 | compatible = "allwinner,sun4i-a10-sram-c1"; | |
257 | reg = <0x000000 0x80000>; | |
258 | }; | |
259 | }; | |
1fbc1517 MR |
260 | }; |
261 | ||
5841f6c0 | 262 | dma: dma-controller@1c02000 { |
1324f532 EL |
263 | compatible = "allwinner,sun4i-a10-dma"; |
264 | reg = <0x01c02000 0x1000>; | |
265 | interrupts = <27>; | |
41193869 | 266 | clocks = <&ccu CLK_AHB_DMA>; |
1324f532 EL |
267 | #dma-cells = <2>; |
268 | }; | |
269 | ||
c9d10c3e | 270 | nfc: nand-controller@1c03000 { |
cefd4860 BB |
271 | compatible = "allwinner,sun4i-a10-nand"; |
272 | reg = <0x01c03000 0x1000>; | |
273 | interrupts = <37>; | |
41193869 | 274 | clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; |
cefd4860 BB |
275 | clock-names = "ahb", "mod"; |
276 | dmas = <&dma SUN4I_DMA_DEDICATED 3>; | |
277 | dma-names = "rxtx"; | |
278 | status = "disabled"; | |
279 | #address-cells = <1>; | |
280 | #size-cells = <0>; | |
281 | }; | |
282 | ||
5841f6c0 | 283 | spi0: spi@1c05000 { |
65918e26 MR |
284 | compatible = "allwinner,sun4i-a10-spi"; |
285 | reg = <0x01c05000 0x1000>; | |
286 | interrupts = <10>; | |
41193869 | 287 | clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; |
65918e26 | 288 | clock-names = "ahb", "mod"; |
1f9f6a78 MR |
289 | dmas = <&dma SUN4I_DMA_DEDICATED 27>, |
290 | <&dma SUN4I_DMA_DEDICATED 26>; | |
4192ff81 | 291 | dma-names = "rx", "tx"; |
65918e26 MR |
292 | status = "disabled"; |
293 | #address-cells = <1>; | |
294 | #size-cells = <0>; | |
295 | }; | |
296 | ||
5841f6c0 | 297 | spi1: spi@1c06000 { |
65918e26 MR |
298 | compatible = "allwinner,sun4i-a10-spi"; |
299 | reg = <0x01c06000 0x1000>; | |
300 | interrupts = <11>; | |
41193869 | 301 | clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; |
65918e26 | 302 | clock-names = "ahb", "mod"; |
1f9f6a78 MR |
303 | dmas = <&dma SUN4I_DMA_DEDICATED 9>, |
304 | <&dma SUN4I_DMA_DEDICATED 8>; | |
4192ff81 | 305 | dma-names = "rx", "tx"; |
bca0d7d9 MR |
306 | pinctrl-names = "default"; |
307 | pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>; | |
65918e26 MR |
308 | status = "disabled"; |
309 | #address-cells = <1>; | |
310 | #size-cells = <0>; | |
311 | }; | |
312 | ||
5841f6c0 | 313 | emac: ethernet@1c0b000 { |
1c70e099 | 314 | compatible = "allwinner,sun4i-a10-emac"; |
e38afcb3 MR |
315 | reg = <0x01c0b000 0x1000>; |
316 | interrupts = <55>; | |
41193869 | 317 | clocks = <&ccu CLK_AHB_EMAC>; |
1fbc1517 | 318 | allwinner,sram = <&emac_sram 1>; |
bca0d7d9 MR |
319 | pinctrl-names = "default"; |
320 | pinctrl-0 = <&emac_pins>; | |
e38afcb3 MR |
321 | status = "disabled"; |
322 | }; | |
323 | ||
5841f6c0 | 324 | mdio: mdio@1c0b080 { |
1c70e099 | 325 | compatible = "allwinner,sun4i-a10-mdio"; |
e38afcb3 MR |
326 | reg = <0x01c0b080 0x14>; |
327 | status = "disabled"; | |
328 | #address-cells = <1>; | |
329 | #size-cells = <0>; | |
330 | }; | |
331 | ||
0df4cf33 CYT |
332 | tcon0: lcd-controller@1c0c000 { |
333 | compatible = "allwinner,sun4i-a10-tcon"; | |
334 | reg = <0x01c0c000 0x1000>; | |
335 | interrupts = <44>; | |
336 | resets = <&ccu RST_TCON0>; | |
337 | reset-names = "lcd"; | |
338 | clocks = <&ccu CLK_AHB_LCD0>, | |
339 | <&ccu CLK_TCON0_CH0>, | |
340 | <&ccu CLK_TCON0_CH1>; | |
341 | clock-names = "ahb", | |
342 | "tcon-ch0", | |
343 | "tcon-ch1"; | |
344 | clock-output-names = "tcon0-pixel-clock"; | |
09f29dcc | 345 | #clock-cells = <0>; |
0df4cf33 CYT |
346 | dmas = <&dma SUN4I_DMA_DEDICATED 14>; |
347 | ||
348 | ports { | |
349 | #address-cells = <1>; | |
350 | #size-cells = <0>; | |
351 | ||
352 | tcon0_in: port@0 { | |
353 | #address-cells = <1>; | |
354 | #size-cells = <0>; | |
355 | reg = <0>; | |
356 | ||
357 | tcon0_in_be0: endpoint@0 { | |
358 | reg = <0>; | |
359 | remote-endpoint = <&be0_out_tcon0>; | |
360 | }; | |
361 | ||
362 | tcon0_in_be1: endpoint@1 { | |
363 | reg = <1>; | |
364 | remote-endpoint = <&be1_out_tcon0>; | |
365 | }; | |
366 | }; | |
367 | ||
368 | tcon0_out: port@1 { | |
369 | #address-cells = <1>; | |
370 | #size-cells = <0>; | |
371 | reg = <1>; | |
372 | ||
373 | tcon0_out_hdmi: endpoint@1 { | |
374 | reg = <1>; | |
375 | remote-endpoint = <&hdmi_in_tcon0>; | |
376 | allwinner,tcon-channel = <1>; | |
377 | }; | |
378 | }; | |
379 | }; | |
380 | }; | |
381 | ||
382 | tcon1: lcd-controller@1c0d000 { | |
383 | compatible = "allwinner,sun4i-a10-tcon"; | |
384 | reg = <0x01c0d000 0x1000>; | |
385 | interrupts = <45>; | |
386 | resets = <&ccu RST_TCON1>; | |
387 | reset-names = "lcd"; | |
388 | clocks = <&ccu CLK_AHB_LCD1>, | |
389 | <&ccu CLK_TCON1_CH0>, | |
390 | <&ccu CLK_TCON1_CH1>; | |
391 | clock-names = "ahb", | |
392 | "tcon-ch0", | |
393 | "tcon-ch1"; | |
394 | clock-output-names = "tcon1-pixel-clock"; | |
09f29dcc | 395 | #clock-cells = <0>; |
0df4cf33 CYT |
396 | dmas = <&dma SUN4I_DMA_DEDICATED 15>; |
397 | ||
398 | ports { | |
399 | #address-cells = <1>; | |
400 | #size-cells = <0>; | |
401 | ||
402 | tcon1_in: port@0 { | |
403 | #address-cells = <1>; | |
404 | #size-cells = <0>; | |
405 | reg = <0>; | |
406 | ||
407 | tcon1_in_be0: endpoint@0 { | |
408 | reg = <0>; | |
409 | remote-endpoint = <&be0_out_tcon1>; | |
410 | }; | |
411 | ||
412 | tcon1_in_be1: endpoint@1 { | |
413 | reg = <1>; | |
414 | remote-endpoint = <&be1_out_tcon1>; | |
415 | }; | |
416 | }; | |
417 | ||
418 | tcon1_out: port@1 { | |
419 | #address-cells = <1>; | |
420 | #size-cells = <0>; | |
421 | reg = <1>; | |
422 | ||
423 | tcon1_out_hdmi: endpoint@1 { | |
424 | reg = <1>; | |
425 | remote-endpoint = <&hdmi_in_tcon1>; | |
426 | allwinner,tcon-channel = <1>; | |
427 | }; | |
428 | }; | |
429 | }; | |
430 | }; | |
431 | ||
5949bc56 PK |
432 | video-codec@1c0e000 { |
433 | compatible = "allwinner,sun4i-a10-video-engine"; | |
434 | reg = <0x01c0e000 0x1000>; | |
435 | clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, | |
436 | <&ccu CLK_DRAM_VE>; | |
437 | clock-names = "ahb", "mod", "ram"; | |
438 | resets = <&ccu RST_VE>; | |
439 | interrupts = <53>; | |
440 | allwinner,sram = <&ve_sram 1>; | |
441 | }; | |
442 | ||
5841f6c0 | 443 | mmc0: mmc@1c0f000 { |
b258b369 DL |
444 | compatible = "allwinner,sun4i-a10-mmc"; |
445 | reg = <0x01c0f000 0x1000>; | |
41193869 PL |
446 | clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; |
447 | clock-names = "ahb", "mmc"; | |
b258b369 | 448 | interrupts = <32>; |
bca0d7d9 MR |
449 | pinctrl-names = "default"; |
450 | pinctrl-0 = <&mmc0_pins>; | |
b258b369 | 451 | status = "disabled"; |
4c1bb9c3 HG |
452 | #address-cells = <1>; |
453 | #size-cells = <0>; | |
b258b369 DL |
454 | }; |
455 | ||
5841f6c0 | 456 | mmc1: mmc@1c10000 { |
b258b369 DL |
457 | compatible = "allwinner,sun4i-a10-mmc"; |
458 | reg = <0x01c10000 0x1000>; | |
41193869 PL |
459 | clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; |
460 | clock-names = "ahb", "mmc"; | |
b258b369 DL |
461 | interrupts = <33>; |
462 | status = "disabled"; | |
4c1bb9c3 HG |
463 | #address-cells = <1>; |
464 | #size-cells = <0>; | |
b258b369 DL |
465 | }; |
466 | ||
5841f6c0 | 467 | mmc2: mmc@1c11000 { |
b258b369 DL |
468 | compatible = "allwinner,sun4i-a10-mmc"; |
469 | reg = <0x01c11000 0x1000>; | |
41193869 PL |
470 | clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; |
471 | clock-names = "ahb", "mmc"; | |
b258b369 DL |
472 | interrupts = <34>; |
473 | status = "disabled"; | |
4c1bb9c3 HG |
474 | #address-cells = <1>; |
475 | #size-cells = <0>; | |
b258b369 DL |
476 | }; |
477 | ||
5841f6c0 | 478 | mmc3: mmc@1c12000 { |
b258b369 DL |
479 | compatible = "allwinner,sun4i-a10-mmc"; |
480 | reg = <0x01c12000 0x1000>; | |
41193869 PL |
481 | clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>; |
482 | clock-names = "ahb", "mmc"; | |
b258b369 DL |
483 | interrupts = <35>; |
484 | status = "disabled"; | |
4c1bb9c3 HG |
485 | #address-cells = <1>; |
486 | #size-cells = <0>; | |
b258b369 DL |
487 | }; |
488 | ||
5841f6c0 | 489 | usb_otg: usb@1c13000 { |
ce65037f HG |
490 | compatible = "allwinner,sun4i-a10-musb"; |
491 | reg = <0x01c13000 0x0400>; | |
41193869 | 492 | clocks = <&ccu CLK_AHB_OTG>; |
ce65037f HG |
493 | interrupts = <38>; |
494 | interrupt-names = "mc"; | |
495 | phys = <&usbphy 0>; | |
496 | phy-names = "usb"; | |
497 | extcon = <&usbphy 0>; | |
498 | allwinner,sram = <&otg_sram 1>; | |
d4fe5b15 | 499 | dr_mode = "otg"; |
ce65037f HG |
500 | status = "disabled"; |
501 | }; | |
502 | ||
5841f6c0 | 503 | usbphy: phy@1c13400 { |
6ab1ce24 RB |
504 | #phy-cells = <1>; |
505 | compatible = "allwinner,sun4i-a10-usb-phy"; | |
655c0f42 | 506 | reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>; |
6ab1ce24 | 507 | reg-names = "phy_ctrl", "pmu1", "pmu2"; |
41193869 | 508 | clocks = <&ccu CLK_USB_PHY>; |
6ab1ce24 | 509 | clock-names = "usb_phy"; |
41193869 PL |
510 | resets = <&ccu RST_USB_PHY0>, |
511 | <&ccu RST_USB_PHY1>, | |
512 | <&ccu RST_USB_PHY2>; | |
4dba4185 | 513 | reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; |
6ab1ce24 RB |
514 | status = "disabled"; |
515 | }; | |
516 | ||
5841f6c0 | 517 | ehci0: usb@1c14000 { |
6ab1ce24 RB |
518 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; |
519 | reg = <0x01c14000 0x100>; | |
520 | interrupts = <39>; | |
41193869 | 521 | clocks = <&ccu CLK_AHB_EHCI0>; |
6ab1ce24 | 522 | phys = <&usbphy 1>; |
6ab1ce24 RB |
523 | status = "disabled"; |
524 | }; | |
525 | ||
5841f6c0 | 526 | ohci0: usb@1c14400 { |
6ab1ce24 RB |
527 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; |
528 | reg = <0x01c14400 0x100>; | |
529 | interrupts = <64>; | |
41193869 | 530 | clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; |
6ab1ce24 | 531 | phys = <&usbphy 1>; |
6ab1ce24 RB |
532 | status = "disabled"; |
533 | }; | |
534 | ||
5841f6c0 | 535 | crypto: crypto-engine@1c15000 { |
56ba8c58 LC |
536 | compatible = "allwinner,sun4i-a10-crypto"; |
537 | reg = <0x01c15000 0x1000>; | |
538 | interrupts = <86>; | |
41193869 | 539 | clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; |
56ba8c58 LC |
540 | clock-names = "ahb", "mod"; |
541 | }; | |
542 | ||
0df4cf33 CYT |
543 | hdmi: hdmi@1c16000 { |
544 | compatible = "allwinner,sun4i-a10-hdmi"; | |
545 | reg = <0x01c16000 0x1000>; | |
546 | interrupts = <58>; | |
547 | clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, | |
e17e237c CYT |
548 | <&ccu CLK_PLL_VIDEO0_2X>, |
549 | <&ccu CLK_PLL_VIDEO1_2X>; | |
0df4cf33 CYT |
550 | clock-names = "ahb", "mod", "pll-0", "pll-1"; |
551 | dmas = <&dma SUN4I_DMA_NORMAL 16>, | |
552 | <&dma SUN4I_DMA_NORMAL 16>, | |
553 | <&dma SUN4I_DMA_DEDICATED 24>; | |
554 | dma-names = "ddc-tx", "ddc-rx", "audio-tx"; | |
555 | status = "disabled"; | |
556 | ||
557 | ports { | |
558 | #address-cells = <1>; | |
559 | #size-cells = <0>; | |
560 | ||
561 | hdmi_in: port@0 { | |
562 | #address-cells = <1>; | |
563 | #size-cells = <0>; | |
564 | reg = <0>; | |
565 | ||
566 | hdmi_in_tcon0: endpoint@0 { | |
567 | reg = <0>; | |
568 | remote-endpoint = <&tcon0_out_hdmi>; | |
569 | }; | |
570 | ||
571 | hdmi_in_tcon1: endpoint@1 { | |
572 | reg = <1>; | |
573 | remote-endpoint = <&tcon1_out_hdmi>; | |
574 | }; | |
575 | }; | |
576 | ||
577 | hdmi_out: port@1 { | |
0df4cf33 CYT |
578 | reg = <1>; |
579 | }; | |
580 | }; | |
581 | }; | |
582 | ||
5841f6c0 | 583 | spi2: spi@1c17000 { |
65918e26 MR |
584 | compatible = "allwinner,sun4i-a10-spi"; |
585 | reg = <0x01c17000 0x1000>; | |
586 | interrupts = <12>; | |
41193869 | 587 | clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; |
65918e26 | 588 | clock-names = "ahb", "mod"; |
1f9f6a78 MR |
589 | dmas = <&dma SUN4I_DMA_DEDICATED 29>, |
590 | <&dma SUN4I_DMA_DEDICATED 28>; | |
4192ff81 | 591 | dma-names = "rx", "tx"; |
65918e26 MR |
592 | status = "disabled"; |
593 | #address-cells = <1>; | |
594 | #size-cells = <0>; | |
595 | }; | |
596 | ||
5841f6c0 | 597 | ahci: sata@1c18000 { |
248bd1e2 OS |
598 | compatible = "allwinner,sun4i-a10-ahci"; |
599 | reg = <0x01c18000 0x1000>; | |
600 | interrupts = <56>; | |
41193869 | 601 | clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; |
248bd1e2 OS |
602 | status = "disabled"; |
603 | }; | |
604 | ||
5841f6c0 | 605 | ehci1: usb@1c1c000 { |
6ab1ce24 RB |
606 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; |
607 | reg = <0x01c1c000 0x100>; | |
608 | interrupts = <40>; | |
41193869 | 609 | clocks = <&ccu CLK_AHB_EHCI1>; |
6ab1ce24 | 610 | phys = <&usbphy 2>; |
6ab1ce24 RB |
611 | status = "disabled"; |
612 | }; | |
613 | ||
5841f6c0 | 614 | ohci1: usb@1c1c400 { |
6ab1ce24 RB |
615 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; |
616 | reg = <0x01c1c400 0x100>; | |
617 | interrupts = <65>; | |
41193869 | 618 | clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; |
6ab1ce24 | 619 | phys = <&usbphy 2>; |
6ab1ce24 RB |
620 | status = "disabled"; |
621 | }; | |
622 | ||
5841f6c0 | 623 | spi3: spi@1c1f000 { |
65918e26 MR |
624 | compatible = "allwinner,sun4i-a10-spi"; |
625 | reg = <0x01c1f000 0x1000>; | |
626 | interrupts = <50>; | |
41193869 | 627 | clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; |
65918e26 | 628 | clock-names = "ahb", "mod"; |
1f9f6a78 MR |
629 | dmas = <&dma SUN4I_DMA_DEDICATED 31>, |
630 | <&dma SUN4I_DMA_DEDICATED 30>; | |
4192ff81 | 631 | dma-names = "rx", "tx"; |
65918e26 MR |
632 | status = "disabled"; |
633 | #address-cells = <1>; | |
634 | #size-cells = <0>; | |
635 | }; | |
636 | ||
5841f6c0 | 637 | ccu: clock@1c20000 { |
41193869 PL |
638 | compatible = "allwinner,sun4i-a10-ccu"; |
639 | reg = <0x01c20000 0x400>; | |
640 | clocks = <&osc24M>, <&osc32k>; | |
641 | clock-names = "hosc", "losc"; | |
642 | #clock-cells = <1>; | |
643 | #reset-cells = <1>; | |
644 | }; | |
645 | ||
5841f6c0 | 646 | intc: interrupt-controller@1c20400 { |
09504a7d | 647 | compatible = "allwinner,sun4i-a10-ic"; |
69144e3b MR |
648 | reg = <0x01c20400 0x400>; |
649 | interrupt-controller; | |
650 | #interrupt-cells = <1>; | |
651 | }; | |
652 | ||
5841f6c0 | 653 | pio: pinctrl@1c20800 { |
874b4e45 MR |
654 | compatible = "allwinner,sun4i-a10-pinctrl"; |
655 | reg = <0x01c20800 0x400>; | |
39138bc6 | 656 | interrupts = <28>; |
41193869 | 657 | clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; |
be7bc6b9 | 658 | clock-names = "apb", "hosc", "losc"; |
e10911e1 | 659 | gpio-controller; |
39138bc6 | 660 | interrupt-controller; |
b03e0816 | 661 | #interrupt-cells = <3>; |
e10911e1 | 662 | #gpio-cells = <3>; |
581981be | 663 | |
e53bd761 | 664 | can0_ph_pins: can0-ph-pins { |
908370f6 PM |
665 | pins = "PH20", "PH21"; |
666 | function = "can"; | |
667 | }; | |
668 | ||
e53bd761 | 669 | emac_pins: emac0-pins { |
1edcd36f MR |
670 | pins = "PA0", "PA1", "PA2", |
671 | "PA3", "PA4", "PA5", "PA6", | |
672 | "PA7", "PA8", "PA9", "PA10", | |
673 | "PA11", "PA12", "PA13", "PA14", | |
674 | "PA15", "PA16"; | |
675 | function = "emac"; | |
1d5726e9 AB |
676 | }; |
677 | ||
e53bd761 | 678 | i2c0_pins: i2c0-pins { |
1edcd36f MR |
679 | pins = "PB0", "PB1"; |
680 | function = "i2c0"; | |
581981be MR |
681 | }; |
682 | ||
e53bd761 | 683 | i2c1_pins: i2c1-pins { |
1edcd36f MR |
684 | pins = "PB18", "PB19"; |
685 | function = "i2c1"; | |
581981be MR |
686 | }; |
687 | ||
e53bd761 | 688 | i2c2_pins: i2c2-pins { |
1edcd36f MR |
689 | pins = "PB20", "PB21"; |
690 | function = "i2c2"; | |
581981be | 691 | }; |
27cce4ff | 692 | |
e53bd761 | 693 | ir0_rx_pins: ir0-rx-pin { |
1edcd36f MR |
694 | pins = "PB4"; |
695 | function = "ir0"; | |
27cce4ff MR |
696 | }; |
697 | ||
e53bd761 | 698 | ir0_tx_pins: ir0-tx-pin { |
1edcd36f MR |
699 | pins = "PB3"; |
700 | function = "ir0"; | |
27cce4ff MR |
701 | }; |
702 | ||
e53bd761 | 703 | ir1_rx_pins: ir1-rx-pin { |
1edcd36f MR |
704 | pins = "PB23"; |
705 | function = "ir1"; | |
27cce4ff | 706 | }; |
496322bc | 707 | |
e53bd761 | 708 | ir1_tx_pins: ir1-tx-pin { |
1edcd36f MR |
709 | pins = "PB22"; |
710 | function = "ir1"; | |
b21da664 | 711 | }; |
b5f86a3a | 712 | |
e53bd761 | 713 | mmc0_pins: mmc0-pins { |
1edcd36f MR |
714 | pins = "PF0", "PF1", "PF2", |
715 | "PF3", "PF4", "PF5"; | |
716 | function = "mmc0"; | |
717 | drive-strength = <30>; | |
80ee72e7 | 718 | bias-pull-up; |
b5f86a3a HG |
719 | }; |
720 | ||
e53bd761 | 721 | ps2_ch0_pins: ps2-ch0-pins { |
1edcd36f MR |
722 | pins = "PI20", "PI21"; |
723 | function = "ps2"; | |
a4e1099a HG |
724 | }; |
725 | ||
e53bd761 | 726 | ps2_ch1_ph_pins: ps2-ch1-ph-pins { |
1edcd36f MR |
727 | pins = "PH12", "PH13"; |
728 | function = "ps2"; | |
469a22e6 MC |
729 | }; |
730 | ||
e53bd761 | 731 | pwm0_pin: pwm0-pin { |
1edcd36f MR |
732 | pins = "PB2"; |
733 | function = "pwm"; | |
469a22e6 MC |
734 | }; |
735 | ||
e53bd761 | 736 | pwm1_pin: pwm1-pin { |
1edcd36f MR |
737 | pins = "PI3"; |
738 | function = "pwm"; | |
a4e1099a | 739 | }; |
ec66d0bb | 740 | |
e53bd761 | 741 | spdif_tx_pin: spdif-tx-pin { |
1edcd36f MR |
742 | pins = "PB13"; |
743 | function = "spdif"; | |
744 | bias-pull-up; | |
03907ab3 AM |
745 | }; |
746 | ||
e53bd761 | 747 | spi0_pi_pins: spi0-pi-pins { |
1edcd36f MR |
748 | pins = "PI11", "PI12", "PI13"; |
749 | function = "spi0"; | |
f3022c6c MR |
750 | }; |
751 | ||
e53bd761 | 752 | spi0_cs0_pi_pin: spi0-cs0-pi-pin { |
1edcd36f MR |
753 | pins = "PI10"; |
754 | function = "spi0"; | |
ec66d0bb AG |
755 | }; |
756 | ||
e53bd761 | 757 | spi1_pins: spi1-pins { |
1edcd36f MR |
758 | pins = "PI17", "PI18", "PI19"; |
759 | function = "spi1"; | |
f3022c6c MR |
760 | }; |
761 | ||
e53bd761 | 762 | spi1_cs0_pin: spi1-cs0-pin { |
1edcd36f MR |
763 | pins = "PI16"; |
764 | function = "spi1"; | |
ec66d0bb AG |
765 | }; |
766 | ||
e53bd761 MR |
767 | spi2_pb_pins: spi2-pb-pins { |
768 | pins = "PB15", "PB16", "PB17"; | |
1edcd36f | 769 | function = "spi2"; |
ec66d0bb AG |
770 | }; |
771 | ||
e53bd761 MR |
772 | spi2_pc_pins: spi2-pc-pins { |
773 | pins = "PC20", "PC21", "PC22"; | |
1edcd36f | 774 | function = "spi2"; |
f3022c6c MR |
775 | }; |
776 | ||
e53bd761 MR |
777 | spi2_cs0_pb_pin: spi2-cs0-pb-pin { |
778 | pins = "PB14"; | |
1edcd36f | 779 | function = "spi2"; |
f3022c6c MR |
780 | }; |
781 | ||
e53bd761 MR |
782 | spi2_cs0_pc_pins: spi2-cs0-pc-pin { |
783 | pins = "PC19"; | |
1edcd36f | 784 | function = "spi2"; |
ec66d0bb | 785 | }; |
1e8d1567 | 786 | |
e53bd761 | 787 | uart0_pb_pins: uart0-pb-pins { |
1edcd36f MR |
788 | pins = "PB22", "PB23"; |
789 | function = "uart0"; | |
1e8d1567 VP |
790 | }; |
791 | ||
e53bd761 | 792 | uart0_pf_pins: uart0-pf-pins { |
1edcd36f MR |
793 | pins = "PF2", "PF4"; |
794 | function = "uart0"; | |
a4e1099a | 795 | }; |
79f969f0 | 796 | |
e53bd761 | 797 | uart1_pins: uart1-pins { |
1edcd36f MR |
798 | pins = "PA10", "PA11"; |
799 | function = "uart1"; | |
79f969f0 | 800 | }; |
874b4e45 | 801 | }; |
89b3c99f | 802 | |
5841f6c0 | 803 | timer@1c20c00 { |
b4f26440 | 804 | compatible = "allwinner,sun4i-a10-timer"; |
69144e3b MR |
805 | reg = <0x01c20c00 0x90>; |
806 | interrupts = <22>; | |
807 | clocks = <&osc24M>; | |
808 | }; | |
809 | ||
5841f6c0 | 810 | wdt: watchdog@1c20c90 { |
ca5d04d9 | 811 | compatible = "allwinner,sun4i-a10-wdt"; |
69144e3b MR |
812 | reg = <0x01c20c90 0x10>; |
813 | }; | |
814 | ||
5841f6c0 | 815 | rtc: rtc@1c20d00 { |
5fc4bc89 | 816 | compatible = "allwinner,sun4i-a10-rtc"; |
b5d905c7 CC |
817 | reg = <0x01c20d00 0x20>; |
818 | interrupts = <24>; | |
819 | }; | |
820 | ||
5841f6c0 | 821 | pwm: pwm@1c20e00 { |
4b57a395 AB |
822 | compatible = "allwinner,sun4i-a10-pwm"; |
823 | reg = <0x01c20e00 0xc>; | |
824 | clocks = <&osc24M>; | |
825 | #pwm-cells = <3>; | |
826 | status = "disabled"; | |
827 | }; | |
828 | ||
5841f6c0 | 829 | spdif: spdif@1c21000 { |
166db83e MC |
830 | #sound-dai-cells = <0>; |
831 | compatible = "allwinner,sun4i-a10-spdif"; | |
832 | reg = <0x01c21000 0x400>; | |
833 | interrupts = <13>; | |
41193869 | 834 | clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; |
166db83e MC |
835 | clock-names = "apb", "spdif"; |
836 | dmas = <&dma SUN4I_DMA_NORMAL 2>, | |
837 | <&dma SUN4I_DMA_NORMAL 2>; | |
838 | dma-names = "rx", "tx"; | |
839 | status = "disabled"; | |
840 | }; | |
841 | ||
5841f6c0 | 842 | ir0: ir@1c21800 { |
a4e1099a | 843 | compatible = "allwinner,sun4i-a10-ir"; |
41193869 | 844 | clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; |
a4e1099a HG |
845 | clock-names = "apb", "ir"; |
846 | interrupts = <5>; | |
847 | reg = <0x01c21800 0x40>; | |
848 | status = "disabled"; | |
849 | }; | |
850 | ||
5841f6c0 | 851 | ir1: ir@1c21c00 { |
a4e1099a | 852 | compatible = "allwinner,sun4i-a10-ir"; |
41193869 | 853 | clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; |
a4e1099a HG |
854 | clock-names = "apb", "ir"; |
855 | interrupts = <6>; | |
856 | reg = <0x01c21c00 0x40>; | |
857 | status = "disabled"; | |
858 | }; | |
859 | ||
5841f6c0 | 860 | i2s0: i2s@1c22400 { |
d84a0c0a PL |
861 | #sound-dai-cells = <0>; |
862 | compatible = "allwinner,sun4i-a10-i2s"; | |
863 | reg = <0x01c22400 0x400>; | |
864 | interrupts = <16>; | |
865 | clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; | |
866 | clock-names = "apb", "mod"; | |
867 | dmas = <&dma SUN4I_DMA_NORMAL 3>, | |
868 | <&dma SUN4I_DMA_NORMAL 3>; | |
869 | dma-names = "rx", "tx"; | |
870 | status = "disabled"; | |
871 | }; | |
872 | ||
5841f6c0 | 873 | lradc: lradc@1c22800 { |
b0512e15 HG |
874 | compatible = "allwinner,sun4i-a10-lradc-keys"; |
875 | reg = <0x01c22800 0x100>; | |
876 | interrupts = <31>; | |
877 | status = "disabled"; | |
878 | }; | |
879 | ||
5841f6c0 | 880 | codec: codec@1c22c00 { |
bcf88450 MC |
881 | #sound-dai-cells = <0>; |
882 | compatible = "allwinner,sun4i-a10-codec"; | |
883 | reg = <0x01c22c00 0x40>; | |
884 | interrupts = <30>; | |
41193869 | 885 | clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; |
bcf88450 MC |
886 | clock-names = "apb", "codec"; |
887 | dmas = <&dma SUN4I_DMA_NORMAL 19>, | |
888 | <&dma SUN4I_DMA_NORMAL 19>; | |
889 | dma-names = "rx", "tx"; | |
890 | status = "disabled"; | |
891 | }; | |
892 | ||
5841f6c0 | 893 | sid: eeprom@1c23800 { |
043d56ee | 894 | compatible = "allwinner,sun4i-a10-sid"; |
2bad969f OS |
895 | reg = <0x01c23800 0x10>; |
896 | }; | |
897 | ||
5841f6c0 | 898 | rtp: rtp@1c25000 { |
40dd8f3b | 899 | compatible = "allwinner,sun4i-a10-ts"; |
57c8839c HG |
900 | reg = <0x01c25000 0x100>; |
901 | interrupts = <29>; | |
41e7afb1 | 902 | #thermal-sensor-cells = <0>; |
57c8839c HG |
903 | }; |
904 | ||
5841f6c0 | 905 | uart0: serial@1c28000 { |
89b3c99f MR |
906 | compatible = "snps,dw-apb-uart"; |
907 | reg = <0x01c28000 0x400>; | |
908 | interrupts = <1>; | |
909 | reg-shift = <2>; | |
910 | reg-io-width = <4>; | |
41193869 | 911 | clocks = <&ccu CLK_APB1_UART0>; |
89b3c99f MR |
912 | status = "disabled"; |
913 | }; | |
76f14d0a | 914 | |
5841f6c0 | 915 | uart1: serial@1c28400 { |
69144e3b MR |
916 | compatible = "snps,dw-apb-uart"; |
917 | reg = <0x01c28400 0x400>; | |
918 | interrupts = <2>; | |
919 | reg-shift = <2>; | |
920 | reg-io-width = <4>; | |
41193869 | 921 | clocks = <&ccu CLK_APB1_UART1>; |
69144e3b MR |
922 | status = "disabled"; |
923 | }; | |
924 | ||
5841f6c0 | 925 | uart2: serial@1c28800 { |
76f14d0a MR |
926 | compatible = "snps,dw-apb-uart"; |
927 | reg = <0x01c28800 0x400>; | |
928 | interrupts = <3>; | |
929 | reg-shift = <2>; | |
930 | reg-io-width = <4>; | |
41193869 | 931 | clocks = <&ccu CLK_APB1_UART2>; |
76f14d0a MR |
932 | status = "disabled"; |
933 | }; | |
934 | ||
5841f6c0 | 935 | uart3: serial@1c28c00 { |
69144e3b MR |
936 | compatible = "snps,dw-apb-uart"; |
937 | reg = <0x01c28c00 0x400>; | |
938 | interrupts = <4>; | |
939 | reg-shift = <2>; | |
940 | reg-io-width = <4>; | |
41193869 | 941 | clocks = <&ccu CLK_APB1_UART3>; |
69144e3b MR |
942 | status = "disabled"; |
943 | }; | |
944 | ||
5841f6c0 | 945 | uart4: serial@1c29000 { |
76f14d0a MR |
946 | compatible = "snps,dw-apb-uart"; |
947 | reg = <0x01c29000 0x400>; | |
948 | interrupts = <17>; | |
949 | reg-shift = <2>; | |
950 | reg-io-width = <4>; | |
41193869 | 951 | clocks = <&ccu CLK_APB1_UART4>; |
76f14d0a MR |
952 | status = "disabled"; |
953 | }; | |
954 | ||
5841f6c0 | 955 | uart5: serial@1c29400 { |
76f14d0a MR |
956 | compatible = "snps,dw-apb-uart"; |
957 | reg = <0x01c29400 0x400>; | |
958 | interrupts = <18>; | |
959 | reg-shift = <2>; | |
960 | reg-io-width = <4>; | |
41193869 | 961 | clocks = <&ccu CLK_APB1_UART5>; |
76f14d0a MR |
962 | status = "disabled"; |
963 | }; | |
964 | ||
5841f6c0 | 965 | uart6: serial@1c29800 { |
76f14d0a MR |
966 | compatible = "snps,dw-apb-uart"; |
967 | reg = <0x01c29800 0x400>; | |
968 | interrupts = <19>; | |
969 | reg-shift = <2>; | |
970 | reg-io-width = <4>; | |
41193869 | 971 | clocks = <&ccu CLK_APB1_UART6>; |
76f14d0a MR |
972 | status = "disabled"; |
973 | }; | |
974 | ||
5841f6c0 | 975 | uart7: serial@1c29c00 { |
76f14d0a MR |
976 | compatible = "snps,dw-apb-uart"; |
977 | reg = <0x01c29c00 0x400>; | |
978 | interrupts = <20>; | |
979 | reg-shift = <2>; | |
980 | reg-io-width = <4>; | |
41193869 | 981 | clocks = <&ccu CLK_APB1_UART7>; |
76f14d0a MR |
982 | status = "disabled"; |
983 | }; | |
f1741fda | 984 | |
5841f6c0 | 985 | ps20: ps2@1c2a000 { |
a2294bd6 PM |
986 | compatible = "allwinner,sun4i-a10-ps2"; |
987 | reg = <0x01c2a000 0x400>; | |
988 | interrupts = <62>; | |
41193869 | 989 | clocks = <&ccu CLK_APB1_PS20>; |
a2294bd6 PM |
990 | status = "disabled"; |
991 | }; | |
992 | ||
5841f6c0 | 993 | ps21: ps2@1c2a400 { |
a2294bd6 PM |
994 | compatible = "allwinner,sun4i-a10-ps2"; |
995 | reg = <0x01c2a400 0x400>; | |
996 | interrupts = <63>; | |
41193869 | 997 | clocks = <&ccu CLK_APB1_PS21>; |
a2294bd6 PM |
998 | status = "disabled"; |
999 | }; | |
1000 | ||
5841f6c0 | 1001 | i2c0: i2c@1c2ac00 { |
d275545e | 1002 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
1003 | reg = <0x01c2ac00 0x400>; |
1004 | interrupts = <7>; | |
41193869 | 1005 | clocks = <&ccu CLK_APB1_I2C0>; |
bca0d7d9 MR |
1006 | pinctrl-names = "default"; |
1007 | pinctrl-0 = <&i2c0_pins>; | |
f1741fda | 1008 | status = "disabled"; |
60bbe316 HG |
1009 | #address-cells = <1>; |
1010 | #size-cells = <0>; | |
f1741fda MR |
1011 | }; |
1012 | ||
5841f6c0 | 1013 | i2c1: i2c@1c2b000 { |
d275545e | 1014 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
1015 | reg = <0x01c2b000 0x400>; |
1016 | interrupts = <8>; | |
41193869 | 1017 | clocks = <&ccu CLK_APB1_I2C1>; |
bca0d7d9 MR |
1018 | pinctrl-names = "default"; |
1019 | pinctrl-0 = <&i2c1_pins>; | |
f1741fda | 1020 | status = "disabled"; |
60bbe316 HG |
1021 | #address-cells = <1>; |
1022 | #size-cells = <0>; | |
f1741fda MR |
1023 | }; |
1024 | ||
5841f6c0 | 1025 | i2c2: i2c@1c2b400 { |
d275545e | 1026 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
1027 | reg = <0x01c2b400 0x400>; |
1028 | interrupts = <9>; | |
41193869 | 1029 | clocks = <&ccu CLK_APB1_I2C2>; |
bca0d7d9 MR |
1030 | pinctrl-names = "default"; |
1031 | pinctrl-0 = <&i2c2_pins>; | |
f1741fda | 1032 | status = "disabled"; |
60bbe316 HG |
1033 | #address-cells = <1>; |
1034 | #size-cells = <0>; | |
f1741fda | 1035 | }; |
196654ae | 1036 | |
5841f6c0 | 1037 | can0: can@1c2bc00 { |
adb83474 PM |
1038 | compatible = "allwinner,sun4i-a10-can"; |
1039 | reg = <0x01c2bc00 0x400>; | |
1040 | interrupts = <26>; | |
41193869 | 1041 | clocks = <&ccu CLK_APB1_CAN>; |
adb83474 PM |
1042 | status = "disabled"; |
1043 | }; | |
0df4cf33 | 1044 | |
c0476a31 SVB |
1045 | mali: gpu@1c40000 { |
1046 | compatible = "allwinner,sun4i-a10-mali", "arm,mali-400"; | |
1047 | reg = <0x01c40000 0x10000>; | |
1048 | interrupts = <69>, | |
1049 | <70>, | |
1050 | <71>, | |
1051 | <72>, | |
1052 | <73>; | |
1053 | interrupt-names = "gp", | |
1054 | "gpmmu", | |
1055 | "pp0", | |
1056 | "ppmmu0", | |
1057 | "pmu"; | |
1058 | clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; | |
1059 | clock-names = "bus", "core"; | |
1060 | resets = <&ccu RST_GPU>; | |
1061 | ||
1062 | assigned-clocks = <&ccu CLK_GPU>; | |
1063 | assigned-clock-rates = <384000000>; | |
1064 | }; | |
1065 | ||
0df4cf33 CYT |
1066 | fe0: display-frontend@1e00000 { |
1067 | compatible = "allwinner,sun4i-a10-display-frontend"; | |
1068 | reg = <0x01e00000 0x20000>; | |
1069 | interrupts = <47>; | |
1070 | clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, | |
1071 | <&ccu CLK_DRAM_DE_FE0>; | |
1072 | clock-names = "ahb", "mod", | |
1073 | "ram"; | |
1074 | resets = <&ccu RST_DE_FE0>; | |
1075 | ||
1076 | ports { | |
1077 | #address-cells = <1>; | |
1078 | #size-cells = <0>; | |
1079 | ||
1080 | fe0_out: port@1 { | |
1081 | #address-cells = <1>; | |
1082 | #size-cells = <0>; | |
1083 | reg = <1>; | |
1084 | ||
1085 | fe0_out_be0: endpoint@0 { | |
1086 | reg = <0>; | |
1087 | remote-endpoint = <&be0_in_fe0>; | |
1088 | }; | |
1089 | ||
1090 | fe0_out_be1: endpoint@1 { | |
1091 | reg = <1>; | |
1092 | remote-endpoint = <&be1_in_fe0>; | |
1093 | }; | |
1094 | }; | |
1095 | }; | |
1096 | }; | |
1097 | ||
1098 | fe1: display-frontend@1e20000 { | |
1099 | compatible = "allwinner,sun4i-a10-display-frontend"; | |
1100 | reg = <0x01e20000 0x20000>; | |
1101 | interrupts = <48>; | |
1102 | clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, | |
1103 | <&ccu CLK_DRAM_DE_FE1>; | |
1104 | clock-names = "ahb", "mod", | |
1105 | "ram"; | |
1106 | resets = <&ccu RST_DE_FE1>; | |
1107 | ||
1108 | ports { | |
1109 | #address-cells = <1>; | |
1110 | #size-cells = <0>; | |
1111 | ||
1112 | fe1_out: port@1 { | |
1113 | #address-cells = <1>; | |
1114 | #size-cells = <0>; | |
1115 | reg = <1>; | |
1116 | ||
1117 | fe1_out_be0: endpoint@0 { | |
1118 | reg = <0>; | |
1119 | remote-endpoint = <&be0_in_fe1>; | |
1120 | }; | |
1121 | ||
1122 | fe1_out_be1: endpoint@1 { | |
1123 | reg = <1>; | |
1124 | remote-endpoint = <&be1_in_fe1>; | |
1125 | }; | |
1126 | }; | |
1127 | }; | |
1128 | }; | |
1129 | ||
1130 | be1: display-backend@1e40000 { | |
1131 | compatible = "allwinner,sun4i-a10-display-backend"; | |
1132 | reg = <0x01e40000 0x10000>; | |
1133 | interrupts = <48>; | |
1134 | clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, | |
1135 | <&ccu CLK_DRAM_DE_BE1>; | |
1136 | clock-names = "ahb", "mod", | |
1137 | "ram"; | |
1138 | resets = <&ccu RST_DE_BE1>; | |
1139 | ||
1140 | ports { | |
1141 | #address-cells = <1>; | |
1142 | #size-cells = <0>; | |
1143 | ||
1144 | be1_in: port@0 { | |
1145 | #address-cells = <1>; | |
1146 | #size-cells = <0>; | |
1147 | reg = <0>; | |
1148 | ||
1149 | be1_in_fe0: endpoint@0 { | |
1150 | reg = <0>; | |
1151 | remote-endpoint = <&fe0_out_be1>; | |
1152 | }; | |
1153 | ||
1154 | be1_in_fe1: endpoint@1 { | |
1155 | reg = <1>; | |
1156 | remote-endpoint = <&fe1_out_be1>; | |
1157 | }; | |
1158 | }; | |
1159 | ||
1160 | be1_out: port@1 { | |
1161 | #address-cells = <1>; | |
1162 | #size-cells = <0>; | |
1163 | reg = <1>; | |
1164 | ||
1165 | be1_out_tcon0: endpoint@0 { | |
1166 | reg = <0>; | |
bdae4470 | 1167 | remote-endpoint = <&tcon0_in_be1>; |
0df4cf33 CYT |
1168 | }; |
1169 | ||
1170 | be1_out_tcon1: endpoint@1 { | |
1171 | reg = <1>; | |
1172 | remote-endpoint = <&tcon1_in_be1>; | |
1173 | }; | |
1174 | }; | |
1175 | }; | |
1176 | }; | |
1177 | ||
1178 | be0: display-backend@1e60000 { | |
1179 | compatible = "allwinner,sun4i-a10-display-backend"; | |
1180 | reg = <0x01e60000 0x10000>; | |
1181 | interrupts = <47>; | |
1182 | clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, | |
1183 | <&ccu CLK_DRAM_DE_BE0>; | |
1184 | clock-names = "ahb", "mod", | |
1185 | "ram"; | |
1186 | resets = <&ccu RST_DE_BE0>; | |
1187 | ||
1188 | ports { | |
1189 | #address-cells = <1>; | |
1190 | #size-cells = <0>; | |
1191 | ||
1192 | be0_in: port@0 { | |
1193 | #address-cells = <1>; | |
1194 | #size-cells = <0>; | |
1195 | reg = <0>; | |
1196 | ||
1197 | be0_in_fe0: endpoint@0 { | |
1198 | reg = <0>; | |
1199 | remote-endpoint = <&fe0_out_be0>; | |
1200 | }; | |
1201 | ||
1202 | be0_in_fe1: endpoint@1 { | |
1203 | reg = <1>; | |
1204 | remote-endpoint = <&fe1_out_be0>; | |
1205 | }; | |
1206 | }; | |
1207 | ||
1208 | be0_out: port@1 { | |
1209 | #address-cells = <1>; | |
1210 | #size-cells = <0>; | |
1211 | reg = <1>; | |
1212 | ||
1213 | be0_out_tcon0: endpoint@0 { | |
1214 | reg = <0>; | |
1215 | remote-endpoint = <&tcon0_in_be0>; | |
1216 | }; | |
1217 | ||
1218 | be0_out_tcon1: endpoint@1 { | |
1219 | reg = <1>; | |
1220 | remote-endpoint = <&tcon1_in_be0>; | |
1221 | }; | |
1222 | }; | |
1223 | }; | |
1224 | }; | |
874b4e45 | 1225 | }; |
7423d2d8 | 1226 | }; |