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Commit | Line | Data |
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d3ae078e MR |
1 | /* |
2 | * Copyright 2013 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | * http://www.opensource.org/licenses/gpl-license.html | |
11 | * http://www.gnu.org/copyleft/gpl.html | |
12 | */ | |
13 | ||
14 | /include/ "skeleton.dtsi" | |
15 | ||
16 | / { | |
17 | interrupt-parent = <&intc>; | |
18 | ||
e751cce9 EL |
19 | aliases { |
20 | ethernet0 = &emac; | |
4dd4065f MR |
21 | serial0 = &uart0; |
22 | serial1 = &uart1; | |
23 | serial2 = &uart2; | |
24 | serial3 = &uart3; | |
e751cce9 EL |
25 | }; |
26 | ||
d501841f HG |
27 | chosen { |
28 | #address-cells = <1>; | |
29 | #size-cells = <1>; | |
30 | ranges; | |
31 | ||
32 | framebuffer0-hdmi { | |
33 | compatible = "simple-framebuffer"; | |
34 | clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>; | |
35 | status = "disabled"; | |
36 | }; | |
37 | }; | |
38 | ||
d3ae078e MR |
39 | cpus { |
40 | cpu@0 { | |
41 | compatible = "arm,cortex-a8"; | |
42 | }; | |
43 | }; | |
44 | ||
45 | memory { | |
46 | reg = <0x40000000 0x20000000>; | |
47 | }; | |
48 | ||
49 | clocks { | |
50 | #address-cells = <1>; | |
51 | #size-cells = <1>; | |
52 | ranges; | |
53 | ||
54 | /* | |
55 | * This is a dummy clock, to be used as placeholder on | |
56 | * other mux clocks when a specific parent clock is not | |
57 | * yet implemented. It should be dropped when the driver | |
58 | * is complete. | |
59 | */ | |
60 | dummy: dummy { | |
61 | #clock-cells = <0>; | |
62 | compatible = "fixed-clock"; | |
63 | clock-frequency = <0>; | |
64 | }; | |
65 | ||
3dce8324 | 66 | osc24M: clk@01c20050 { |
d3ae078e | 67 | #clock-cells = <0>; |
bf6534a1 | 68 | compatible = "allwinner,sun4i-a10-osc-clk"; |
d3ae078e MR |
69 | reg = <0x01c20050 0x4>; |
70 | clock-frequency = <24000000>; | |
3dce8324 | 71 | clock-output-names = "osc24M"; |
d3ae078e MR |
72 | }; |
73 | ||
3dce8324 | 74 | osc32k: clk@0 { |
d3ae078e MR |
75 | #clock-cells = <0>; |
76 | compatible = "fixed-clock"; | |
77 | clock-frequency = <32768>; | |
3dce8324 | 78 | clock-output-names = "osc32k"; |
d3ae078e MR |
79 | }; |
80 | ||
3dce8324 | 81 | pll1: clk@01c20000 { |
d3ae078e | 82 | #clock-cells = <0>; |
bf6534a1 | 83 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
d3ae078e MR |
84 | reg = <0x01c20000 0x4>; |
85 | clocks = <&osc24M>; | |
3dce8324 | 86 | clock-output-names = "pll1"; |
d3ae078e MR |
87 | }; |
88 | ||
3dce8324 | 89 | pll4: clk@01c20018 { |
ec5589f7 | 90 | #clock-cells = <0>; |
bf6534a1 | 91 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
ec5589f7 EL |
92 | reg = <0x01c20018 0x4>; |
93 | clocks = <&osc24M>; | |
3dce8324 | 94 | clock-output-names = "pll4"; |
ec5589f7 EL |
95 | }; |
96 | ||
3dce8324 | 97 | pll5: clk@01c20020 { |
c3e5e66b | 98 | #clock-cells = <1>; |
bf6534a1 | 99 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
c3e5e66b EL |
100 | reg = <0x01c20020 0x4>; |
101 | clocks = <&osc24M>; | |
102 | clock-output-names = "pll5_ddr", "pll5_other"; | |
103 | }; | |
104 | ||
3dce8324 | 105 | pll6: clk@01c20028 { |
c3e5e66b | 106 | #clock-cells = <1>; |
bf6534a1 | 107 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
c3e5e66b EL |
108 | reg = <0x01c20028 0x4>; |
109 | clocks = <&osc24M>; | |
110 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
111 | }; | |
112 | ||
d3ae078e MR |
113 | /* dummy is 200M */ |
114 | cpu: cpu@01c20054 { | |
115 | #clock-cells = <0>; | |
bf6534a1 | 116 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
d3ae078e MR |
117 | reg = <0x01c20054 0x4>; |
118 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
3dce8324 | 119 | clock-output-names = "cpu"; |
d3ae078e MR |
120 | }; |
121 | ||
122 | axi: axi@01c20054 { | |
123 | #clock-cells = <0>; | |
bf6534a1 | 124 | compatible = "allwinner,sun4i-a10-axi-clk"; |
d3ae078e MR |
125 | reg = <0x01c20054 0x4>; |
126 | clocks = <&cpu>; | |
3dce8324 | 127 | clock-output-names = "axi"; |
d3ae078e MR |
128 | }; |
129 | ||
3dce8324 | 130 | axi_gates: clk@01c2005c { |
d3ae078e | 131 | #clock-cells = <1>; |
bf6534a1 | 132 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
d3ae078e MR |
133 | reg = <0x01c2005c 0x4>; |
134 | clocks = <&axi>; | |
135 | clock-output-names = "axi_dram"; | |
136 | }; | |
137 | ||
138 | ahb: ahb@01c20054 { | |
139 | #clock-cells = <0>; | |
bf6534a1 | 140 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
d3ae078e MR |
141 | reg = <0x01c20054 0x4>; |
142 | clocks = <&axi>; | |
3dce8324 | 143 | clock-output-names = "ahb"; |
d3ae078e MR |
144 | }; |
145 | ||
3dce8324 | 146 | ahb_gates: clk@01c20060 { |
d3ae078e | 147 | #clock-cells = <1>; |
29bb8054 | 148 | compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; |
d3ae078e MR |
149 | reg = <0x01c20060 0x8>; |
150 | clocks = <&ahb>; | |
29bb8054 MR |
151 | clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", |
152 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", | |
153 | "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram", | |
154 | "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", | |
155 | "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve", | |
156 | "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi", | |
157 | "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400"; | |
d3ae078e MR |
158 | }; |
159 | ||
160 | apb0: apb0@01c20054 { | |
161 | #clock-cells = <0>; | |
bf6534a1 | 162 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
d3ae078e MR |
163 | reg = <0x01c20054 0x4>; |
164 | clocks = <&ahb>; | |
3dce8324 | 165 | clock-output-names = "apb0"; |
d3ae078e MR |
166 | }; |
167 | ||
3dce8324 | 168 | apb0_gates: clk@01c20068 { |
d3ae078e | 169 | #clock-cells = <1>; |
29bb8054 | 170 | compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; |
d3ae078e MR |
171 | reg = <0x01c20068 0x4>; |
172 | clocks = <&apb0>; | |
29bb8054 MR |
173 | clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio", |
174 | "apb0_ir", "apb0_keypad"; | |
d3ae078e MR |
175 | }; |
176 | ||
d3ae078e MR |
177 | apb1_mux: apb1_mux@01c20058 { |
178 | #clock-cells = <0>; | |
bf6534a1 | 179 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
d3ae078e | 180 | reg = <0x01c20058 0x4>; |
c3e5e66b | 181 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
3dce8324 | 182 | clock-output-names = "apb1_mux"; |
d3ae078e MR |
183 | }; |
184 | ||
185 | apb1: apb1@01c20058 { | |
186 | #clock-cells = <0>; | |
bf6534a1 | 187 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
d3ae078e MR |
188 | reg = <0x01c20058 0x4>; |
189 | clocks = <&apb1_mux>; | |
3dce8324 | 190 | clock-output-names = "apb1"; |
d3ae078e MR |
191 | }; |
192 | ||
3dce8324 | 193 | apb1_gates: clk@01c2006c { |
d3ae078e | 194 | #clock-cells = <1>; |
29bb8054 | 195 | compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; |
d3ae078e MR |
196 | reg = <0x01c2006c 0x4>; |
197 | clocks = <&apb1>; | |
198 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
29bb8054 MR |
199 | "apb1_i2c2", "apb1_uart0", "apb1_uart1", |
200 | "apb1_uart2", "apb1_uart3"; | |
d3ae078e | 201 | }; |
8dc36bff EL |
202 | |
203 | nand_clk: clk@01c20080 { | |
204 | #clock-cells = <0>; | |
bf6534a1 | 205 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
206 | reg = <0x01c20080 0x4>; |
207 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
208 | clock-output-names = "nand"; | |
209 | }; | |
210 | ||
211 | ms_clk: clk@01c20084 { | |
212 | #clock-cells = <0>; | |
bf6534a1 | 213 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
214 | reg = <0x01c20084 0x4>; |
215 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
216 | clock-output-names = "ms"; | |
217 | }; | |
218 | ||
219 | mmc0_clk: clk@01c20088 { | |
220 | #clock-cells = <0>; | |
bf6534a1 | 221 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
222 | reg = <0x01c20088 0x4>; |
223 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
224 | clock-output-names = "mmc0"; | |
225 | }; | |
226 | ||
227 | mmc1_clk: clk@01c2008c { | |
228 | #clock-cells = <0>; | |
bf6534a1 | 229 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
230 | reg = <0x01c2008c 0x4>; |
231 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
232 | clock-output-names = "mmc1"; | |
233 | }; | |
234 | ||
235 | mmc2_clk: clk@01c20090 { | |
236 | #clock-cells = <0>; | |
bf6534a1 | 237 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
238 | reg = <0x01c20090 0x4>; |
239 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
240 | clock-output-names = "mmc2"; | |
241 | }; | |
242 | ||
243 | ts_clk: clk@01c20098 { | |
244 | #clock-cells = <0>; | |
bf6534a1 | 245 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
246 | reg = <0x01c20098 0x4>; |
247 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
248 | clock-output-names = "ts"; | |
249 | }; | |
250 | ||
251 | ss_clk: clk@01c2009c { | |
252 | #clock-cells = <0>; | |
bf6534a1 | 253 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
254 | reg = <0x01c2009c 0x4>; |
255 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
256 | clock-output-names = "ss"; | |
257 | }; | |
258 | ||
259 | spi0_clk: clk@01c200a0 { | |
260 | #clock-cells = <0>; | |
bf6534a1 | 261 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
262 | reg = <0x01c200a0 0x4>; |
263 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
264 | clock-output-names = "spi0"; | |
265 | }; | |
266 | ||
267 | spi1_clk: clk@01c200a4 { | |
268 | #clock-cells = <0>; | |
bf6534a1 | 269 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
270 | reg = <0x01c200a4 0x4>; |
271 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
272 | clock-output-names = "spi1"; | |
273 | }; | |
274 | ||
275 | spi2_clk: clk@01c200a8 { | |
276 | #clock-cells = <0>; | |
bf6534a1 | 277 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
278 | reg = <0x01c200a8 0x4>; |
279 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
280 | clock-output-names = "spi2"; | |
281 | }; | |
282 | ||
283 | ir0_clk: clk@01c200b0 { | |
284 | #clock-cells = <0>; | |
bf6534a1 | 285 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
286 | reg = <0x01c200b0 0x4>; |
287 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
288 | clock-output-names = "ir0"; | |
289 | }; | |
118c07ae | 290 | |
4c5d72f8 RB |
291 | usb_clk: clk@01c200cc { |
292 | #clock-cells = <1>; | |
293 | #reset-cells = <1>; | |
294 | compatible = "allwinner,sun5i-a13-usb-clk"; | |
295 | reg = <0x01c200cc 0x4>; | |
296 | clocks = <&pll6 1>; | |
297 | clock-output-names = "usb_ohci0", "usb_phy"; | |
298 | }; | |
299 | ||
118c07ae EL |
300 | mbus_clk: clk@01c2015c { |
301 | #clock-cells = <0>; | |
7868c5eb | 302 | compatible = "allwinner,sun5i-a13-mbus-clk"; |
118c07ae EL |
303 | reg = <0x01c2015c 0x4>; |
304 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
305 | clock-output-names = "mbus"; | |
306 | }; | |
d3ae078e MR |
307 | }; |
308 | ||
9e199292 | 309 | soc@01c00000 { |
d3ae078e MR |
310 | compatible = "simple-bus"; |
311 | #address-cells = <1>; | |
312 | #size-cells = <1>; | |
d3ae078e MR |
313 | ranges; |
314 | ||
6a5775e4 EL |
315 | dma: dma-controller@01c02000 { |
316 | compatible = "allwinner,sun4i-a10-dma"; | |
317 | reg = <0x01c02000 0x1000>; | |
318 | interrupts = <27>; | |
319 | clocks = <&ahb_gates 6>; | |
320 | #dma-cells = <2>; | |
321 | }; | |
322 | ||
8a689569 MR |
323 | spi0: spi@01c05000 { |
324 | compatible = "allwinner,sun4i-a10-spi"; | |
325 | reg = <0x01c05000 0x1000>; | |
326 | interrupts = <10>; | |
327 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
328 | clock-names = "ahb", "mod"; | |
fed4c5c6 EL |
329 | dmas = <&dma 1 27>, <&dma 1 26>; |
330 | dma-names = "rx", "tx"; | |
8a689569 MR |
331 | status = "disabled"; |
332 | #address-cells = <1>; | |
333 | #size-cells = <0>; | |
334 | }; | |
335 | ||
336 | spi1: spi@01c06000 { | |
337 | compatible = "allwinner,sun4i-a10-spi"; | |
338 | reg = <0x01c06000 0x1000>; | |
339 | interrupts = <11>; | |
340 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
341 | clock-names = "ahb", "mod"; | |
fed4c5c6 EL |
342 | dmas = <&dma 1 9>, <&dma 1 8>; |
343 | dma-names = "rx", "tx"; | |
8a689569 MR |
344 | status = "disabled"; |
345 | #address-cells = <1>; | |
346 | #size-cells = <0>; | |
347 | }; | |
348 | ||
d3ae078e | 349 | emac: ethernet@01c0b000 { |
1c70e099 | 350 | compatible = "allwinner,sun4i-a10-emac"; |
d3ae078e MR |
351 | reg = <0x01c0b000 0x1000>; |
352 | interrupts = <55>; | |
353 | clocks = <&ahb_gates 17>; | |
354 | status = "disabled"; | |
355 | }; | |
356 | ||
357 | mdio@01c0b080 { | |
1c70e099 | 358 | compatible = "allwinner,sun4i-a10-mdio"; |
d3ae078e MR |
359 | reg = <0x01c0b080 0x14>; |
360 | status = "disabled"; | |
361 | #address-cells = <1>; | |
362 | #size-cells = <0>; | |
363 | }; | |
364 | ||
d3aed1df DL |
365 | mmc0: mmc@01c0f000 { |
366 | compatible = "allwinner,sun5i-a13-mmc"; | |
367 | reg = <0x01c0f000 0x1000>; | |
368 | clocks = <&ahb_gates 8>, <&mmc0_clk>; | |
369 | clock-names = "ahb", "mmc"; | |
370 | interrupts = <32>; | |
371 | status = "disabled"; | |
372 | }; | |
373 | ||
374 | mmc1: mmc@01c10000 { | |
375 | compatible = "allwinner,sun5i-a13-mmc"; | |
376 | reg = <0x01c10000 0x1000>; | |
377 | clocks = <&ahb_gates 9>, <&mmc1_clk>; | |
378 | clock-names = "ahb", "mmc"; | |
379 | interrupts = <33>; | |
380 | status = "disabled"; | |
381 | }; | |
382 | ||
383 | mmc2: mmc@01c11000 { | |
384 | compatible = "allwinner,sun5i-a13-mmc"; | |
385 | reg = <0x01c11000 0x1000>; | |
386 | clocks = <&ahb_gates 10>, <&mmc2_clk>; | |
387 | clock-names = "ahb", "mmc"; | |
388 | interrupts = <34>; | |
389 | status = "disabled"; | |
390 | }; | |
391 | ||
06c7d52f RB |
392 | usbphy: phy@01c13400 { |
393 | #phy-cells = <1>; | |
394 | compatible = "allwinner,sun5i-a13-usb-phy"; | |
395 | reg = <0x01c13400 0x10 0x01c14800 0x4>; | |
396 | reg-names = "phy_ctrl", "pmu1"; | |
397 | clocks = <&usb_clk 8>; | |
398 | clock-names = "usb_phy"; | |
399 | resets = <&usb_clk 1>; | |
400 | reset-names = "usb1_reset"; | |
401 | status = "disabled"; | |
402 | }; | |
403 | ||
404 | ehci0: usb@01c14000 { | |
405 | compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci"; | |
406 | reg = <0x01c14000 0x100>; | |
407 | interrupts = <39>; | |
408 | clocks = <&ahb_gates 1>; | |
409 | phys = <&usbphy 1>; | |
410 | phy-names = "usb"; | |
411 | status = "disabled"; | |
412 | }; | |
413 | ||
414 | ohci0: usb@01c14400 { | |
415 | compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci"; | |
416 | reg = <0x01c14400 0x100>; | |
417 | interrupts = <40>; | |
418 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
419 | phys = <&usbphy 1>; | |
420 | phy-names = "usb"; | |
421 | status = "disabled"; | |
422 | }; | |
423 | ||
8a689569 MR |
424 | spi2: spi@01c17000 { |
425 | compatible = "allwinner,sun4i-a10-spi"; | |
426 | reg = <0x01c17000 0x1000>; | |
427 | interrupts = <12>; | |
428 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
429 | clock-names = "ahb", "mod"; | |
fed4c5c6 EL |
430 | dmas = <&dma 1 29>, <&dma 1 28>; |
431 | dma-names = "rx", "tx"; | |
8a689569 MR |
432 | status = "disabled"; |
433 | #address-cells = <1>; | |
434 | #size-cells = <0>; | |
435 | }; | |
436 | ||
d3ae078e | 437 | intc: interrupt-controller@01c20400 { |
09504a7d | 438 | compatible = "allwinner,sun4i-a10-ic"; |
d3ae078e MR |
439 | reg = <0x01c20400 0x400>; |
440 | interrupt-controller; | |
441 | #interrupt-cells = <1>; | |
442 | }; | |
443 | ||
444 | pio: pinctrl@01c20800 { | |
445 | compatible = "allwinner,sun5i-a10s-pinctrl"; | |
446 | reg = <0x01c20800 0x400>; | |
447 | interrupts = <28>; | |
448 | clocks = <&apb0_gates 5>; | |
449 | gpio-controller; | |
450 | interrupt-controller; | |
7d4ff96d | 451 | #interrupt-cells = <2>; |
d3ae078e MR |
452 | #size-cells = <0>; |
453 | #gpio-cells = <3>; | |
454 | ||
455 | uart0_pins_a: uart0@0 { | |
456 | allwinner,pins = "PB19", "PB20"; | |
457 | allwinner,function = "uart0"; | |
458 | allwinner,drive = <0>; | |
459 | allwinner,pull = <0>; | |
460 | }; | |
461 | ||
462 | uart2_pins_a: uart2@0 { | |
463 | allwinner,pins = "PC18", "PC19"; | |
464 | allwinner,function = "uart2"; | |
465 | allwinner,drive = <0>; | |
466 | allwinner,pull = <0>; | |
467 | }; | |
468 | ||
469 | uart3_pins_a: uart3@0 { | |
470 | allwinner,pins = "PG9", "PG10"; | |
471 | allwinner,function = "uart3"; | |
472 | allwinner,drive = <0>; | |
473 | allwinner,pull = <0>; | |
474 | }; | |
475 | ||
476 | emac_pins_a: emac0@0 { | |
477 | allwinner,pins = "PA0", "PA1", "PA2", | |
478 | "PA3", "PA4", "PA5", "PA6", | |
479 | "PA7", "PA8", "PA9", "PA10", | |
480 | "PA11", "PA12", "PA13", "PA14", | |
481 | "PA15", "PA16"; | |
482 | allwinner,function = "emac"; | |
483 | allwinner,drive = <0>; | |
484 | allwinner,pull = <0>; | |
485 | }; | |
170ab436 EL |
486 | |
487 | i2c0_pins_a: i2c0@0 { | |
488 | allwinner,pins = "PB0", "PB1"; | |
489 | allwinner,function = "i2c0"; | |
490 | allwinner,drive = <0>; | |
491 | allwinner,pull = <0>; | |
492 | }; | |
493 | ||
494 | i2c1_pins_a: i2c1@0 { | |
495 | allwinner,pins = "PB15", "PB16"; | |
496 | allwinner,function = "i2c1"; | |
497 | allwinner,drive = <0>; | |
498 | allwinner,pull = <0>; | |
499 | }; | |
500 | ||
501 | i2c2_pins_a: i2c2@0 { | |
502 | allwinner,pins = "PB17", "PB18"; | |
503 | allwinner,function = "i2c2"; | |
504 | allwinner,drive = <0>; | |
505 | allwinner,pull = <0>; | |
506 | }; | |
6da50f13 HG |
507 | |
508 | mmc0_pins_a: mmc0@0 { | |
509 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | |
510 | allwinner,function = "mmc0"; | |
511 | allwinner,drive = <2>; | |
512 | allwinner,pull = <0>; | |
513 | }; | |
514 | ||
515 | mmc1_pins_a: mmc1@0 { | |
516 | allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8"; | |
517 | allwinner,function = "mmc1"; | |
518 | allwinner,drive = <2>; | |
519 | allwinner,pull = <0>; | |
520 | }; | |
d3ae078e MR |
521 | }; |
522 | ||
523 | timer@01c20c00 { | |
b4f26440 | 524 | compatible = "allwinner,sun4i-a10-timer"; |
d3ae078e MR |
525 | reg = <0x01c20c00 0x90>; |
526 | interrupts = <22>; | |
527 | clocks = <&osc24M>; | |
528 | }; | |
529 | ||
530 | wdt: watchdog@01c20c90 { | |
ca5d04d9 | 531 | compatible = "allwinner,sun4i-a10-wdt"; |
d3ae078e MR |
532 | reg = <0x01c20c90 0x10>; |
533 | }; | |
534 | ||
2bad969f | 535 | sid: eeprom@01c23800 { |
043d56ee | 536 | compatible = "allwinner,sun4i-a10-sid"; |
2bad969f OS |
537 | reg = <0x01c23800 0x10>; |
538 | }; | |
539 | ||
f65c93a0 | 540 | rtp: rtp@01c25000 { |
40dd8f3b | 541 | compatible = "allwinner,sun4i-a10-ts"; |
f65c93a0 HG |
542 | reg = <0x01c25000 0x100>; |
543 | interrupts = <29>; | |
544 | }; | |
545 | ||
d3ae078e MR |
546 | uart0: serial@01c28000 { |
547 | compatible = "snps,dw-apb-uart"; | |
548 | reg = <0x01c28000 0x400>; | |
549 | interrupts = <1>; | |
550 | reg-shift = <2>; | |
551 | reg-io-width = <4>; | |
552 | clocks = <&apb1_gates 16>; | |
553 | status = "disabled"; | |
554 | }; | |
555 | ||
556 | uart1: serial@01c28400 { | |
557 | compatible = "snps,dw-apb-uart"; | |
558 | reg = <0x01c28400 0x400>; | |
559 | interrupts = <2>; | |
560 | reg-shift = <2>; | |
561 | reg-io-width = <4>; | |
562 | clocks = <&apb1_gates 17>; | |
563 | status = "disabled"; | |
564 | }; | |
565 | ||
566 | uart2: serial@01c28800 { | |
567 | compatible = "snps,dw-apb-uart"; | |
568 | reg = <0x01c28800 0x400>; | |
569 | interrupts = <3>; | |
570 | reg-shift = <2>; | |
571 | reg-io-width = <4>; | |
572 | clocks = <&apb1_gates 18>; | |
573 | status = "disabled"; | |
574 | }; | |
575 | ||
576 | uart3: serial@01c28c00 { | |
577 | compatible = "snps,dw-apb-uart"; | |
578 | reg = <0x01c28c00 0x400>; | |
579 | interrupts = <4>; | |
580 | reg-shift = <2>; | |
581 | reg-io-width = <4>; | |
582 | clocks = <&apb1_gates 19>; | |
583 | status = "disabled"; | |
584 | }; | |
ca3d4ed5 EL |
585 | |
586 | i2c0: i2c@01c2ac00 { | |
587 | #address-cells = <1>; | |
588 | #size-cells = <0>; | |
d275545e | 589 | compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; |
ca3d4ed5 EL |
590 | reg = <0x01c2ac00 0x400>; |
591 | interrupts = <7>; | |
592 | clocks = <&apb1_gates 0>; | |
ca3d4ed5 EL |
593 | status = "disabled"; |
594 | }; | |
595 | ||
596 | i2c1: i2c@01c2b000 { | |
597 | #address-cells = <1>; | |
598 | #size-cells = <0>; | |
d275545e | 599 | compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; |
ca3d4ed5 EL |
600 | reg = <0x01c2b000 0x400>; |
601 | interrupts = <8>; | |
602 | clocks = <&apb1_gates 1>; | |
ca3d4ed5 EL |
603 | status = "disabled"; |
604 | }; | |
605 | ||
606 | i2c2: i2c@01c2b400 { | |
607 | #address-cells = <1>; | |
608 | #size-cells = <0>; | |
d275545e | 609 | compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; |
ca3d4ed5 EL |
610 | reg = <0x01c2b400 0x400>; |
611 | interrupts = <9>; | |
612 | clocks = <&apb1_gates 2>; | |
ca3d4ed5 EL |
613 | status = "disabled"; |
614 | }; | |
f2b50028 MR |
615 | |
616 | timer@01c60000 { | |
617 | compatible = "allwinner,sun5i-a13-hstimer"; | |
618 | reg = <0x01c60000 0x1000>; | |
619 | interrupts = <82>, <83>; | |
620 | clocks = <&ahb_gates 28>; | |
621 | }; | |
d3ae078e MR |
622 | }; |
623 | }; |