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d4da2ebb MR |
1 | /* |
2 | * Copyright 2012 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | * http://www.opensource.org/licenses/gpl-license.html | |
11 | * http://www.gnu.org/copyleft/gpl.html | |
12 | */ | |
13 | ||
69144e3b | 14 | /include/ "skeleton.dtsi" |
d4da2ebb MR |
15 | |
16 | / { | |
69144e3b MR |
17 | interrupt-parent = <&intc>; |
18 | ||
19 | cpus { | |
20 | cpu@0 { | |
21 | compatible = "arm,cortex-a8"; | |
22 | }; | |
23 | }; | |
24 | ||
d4da2ebb MR |
25 | memory { |
26 | reg = <0x40000000 0x20000000>; | |
27 | }; | |
9e2dcb2f | 28 | |
69144e3b MR |
29 | clocks { |
30 | #address-cells = <1>; | |
31 | #size-cells = <1>; | |
32 | ranges; | |
33 | ||
34 | /* | |
35 | * This is a dummy clock, to be used as placeholder on | |
36 | * other mux clocks when a specific parent clock is not | |
37 | * yet implemented. It should be dropped when the driver | |
38 | * is complete. | |
39 | */ | |
40 | dummy: dummy { | |
41 | #clock-cells = <0>; | |
42 | compatible = "fixed-clock"; | |
43 | clock-frequency = <0>; | |
44 | }; | |
45 | ||
46 | osc24M_fixed: osc24M_fixed { | |
47 | #clock-cells = <0>; | |
48 | compatible = "fixed-clock"; | |
49 | clock-frequency = <24000000>; | |
50 | }; | |
51 | ||
52 | osc24M: osc24M@01c20050 { | |
53 | #clock-cells = <0>; | |
54 | compatible = "allwinner,sun4i-osc-clk"; | |
55 | reg = <0x01c20050 0x4>; | |
56 | clocks = <&osc24M_fixed>; | |
57 | }; | |
58 | ||
59 | osc32k: osc32k { | |
60 | #clock-cells = <0>; | |
61 | compatible = "fixed-clock"; | |
62 | clock-frequency = <32768>; | |
63 | }; | |
64 | ||
65 | pll1: pll1@01c20000 { | |
66 | #clock-cells = <0>; | |
67 | compatible = "allwinner,sun4i-pll1-clk"; | |
68 | reg = <0x01c20000 0x4>; | |
69 | clocks = <&osc24M>; | |
70 | }; | |
71 | ||
72 | /* dummy is 200M */ | |
73 | cpu: cpu@01c20054 { | |
74 | #clock-cells = <0>; | |
75 | compatible = "allwinner,sun4i-cpu-clk"; | |
76 | reg = <0x01c20054 0x4>; | |
77 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
78 | }; | |
79 | ||
80 | axi: axi@01c20054 { | |
81 | #clock-cells = <0>; | |
82 | compatible = "allwinner,sun4i-axi-clk"; | |
83 | reg = <0x01c20054 0x4>; | |
84 | clocks = <&cpu>; | |
85 | }; | |
86 | ||
87 | axi_gates: axi_gates@01c2005c { | |
88 | #clock-cells = <1>; | |
89 | compatible = "allwinner,sun4i-axi-gates-clk"; | |
90 | reg = <0x01c2005c 0x4>; | |
91 | clocks = <&axi>; | |
92 | clock-output-names = "axi_dram"; | |
93 | }; | |
94 | ||
95 | ahb: ahb@01c20054 { | |
96 | #clock-cells = <0>; | |
97 | compatible = "allwinner,sun4i-ahb-clk"; | |
98 | reg = <0x01c20054 0x4>; | |
99 | clocks = <&axi>; | |
100 | }; | |
101 | ||
102 | ahb_gates: ahb_gates@01c20060 { | |
103 | #clock-cells = <1>; | |
104 | compatible = "allwinner,sun4i-ahb-gates-clk"; | |
105 | reg = <0x01c20060 0x8>; | |
106 | clocks = <&ahb>; | |
107 | clock-output-names = "ahb_usb0", "ahb_ehci0", | |
108 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", | |
109 | "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", | |
110 | "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", | |
111 | "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", | |
112 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", | |
113 | "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", | |
114 | "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", | |
115 | "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", | |
116 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
117 | "ahb_de_fe1", "ahb_mp", "ahb_mali400"; | |
118 | }; | |
119 | ||
120 | apb0: apb0@01c20054 { | |
121 | #clock-cells = <0>; | |
122 | compatible = "allwinner,sun4i-apb0-clk"; | |
123 | reg = <0x01c20054 0x4>; | |
124 | clocks = <&ahb>; | |
125 | }; | |
126 | ||
127 | apb0_gates: apb0_gates@01c20068 { | |
128 | #clock-cells = <1>; | |
129 | compatible = "allwinner,sun4i-apb0-gates-clk"; | |
130 | reg = <0x01c20068 0x4>; | |
131 | clocks = <&apb0>; | |
132 | clock-output-names = "apb0_codec", "apb0_spdif", | |
133 | "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", | |
134 | "apb0_ir1", "apb0_keypad"; | |
135 | }; | |
136 | ||
137 | /* dummy is pll62 */ | |
138 | apb1_mux: apb1_mux@01c20058 { | |
139 | #clock-cells = <0>; | |
140 | compatible = "allwinner,sun4i-apb1-mux-clk"; | |
141 | reg = <0x01c20058 0x4>; | |
142 | clocks = <&osc24M>, <&dummy>, <&osc32k>; | |
143 | }; | |
144 | ||
145 | apb1: apb1@01c20058 { | |
146 | #clock-cells = <0>; | |
147 | compatible = "allwinner,sun4i-apb1-clk"; | |
148 | reg = <0x01c20058 0x4>; | |
149 | clocks = <&apb1_mux>; | |
150 | }; | |
151 | ||
152 | apb1_gates: apb1_gates@01c2006c { | |
153 | #clock-cells = <1>; | |
154 | compatible = "allwinner,sun4i-apb1-gates-clk"; | |
155 | reg = <0x01c2006c 0x4>; | |
156 | clocks = <&apb1>; | |
157 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
158 | "apb1_i2c2", "apb1_can", "apb1_scr", | |
159 | "apb1_ps20", "apb1_ps21", "apb1_uart0", | |
160 | "apb1_uart1", "apb1_uart2", "apb1_uart3", | |
161 | "apb1_uart4", "apb1_uart5", "apb1_uart6", | |
162 | "apb1_uart7"; | |
163 | }; | |
164 | }; | |
165 | ||
166 | soc@01c20000 { | |
167 | compatible = "simple-bus"; | |
168 | #address-cells = <1>; | |
169 | #size-cells = <1>; | |
170 | reg = <0x01c20000 0x300000>; | |
171 | ranges; | |
172 | ||
173 | intc: interrupt-controller@01c20400 { | |
6def126d | 174 | compatible = "allwinner,sun4i-ic"; |
69144e3b MR |
175 | reg = <0x01c20400 0x400>; |
176 | interrupt-controller; | |
177 | #interrupt-cells = <1>; | |
178 | }; | |
179 | ||
e10911e1 | 180 | pio: pinctrl@01c20800 { |
9e2dcb2f MR |
181 | compatible = "allwinner,sun5i-a13-pinctrl"; |
182 | reg = <0x01c20800 0x400>; | |
36386d6e | 183 | clocks = <&apb0_gates 5>; |
e10911e1 | 184 | gpio-controller; |
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185 | #address-cells = <1>; |
186 | #size-cells = <0>; | |
e10911e1 | 187 | #gpio-cells = <3>; |
4348cc64 MR |
188 | |
189 | uart1_pins_a: uart1@0 { | |
190 | allwinner,pins = "PE10", "PE11"; | |
191 | allwinner,function = "uart1"; | |
192 | allwinner,drive = <0>; | |
193 | allwinner,pull = <0>; | |
194 | }; | |
195 | ||
196 | uart1_pins_b: uart1@1 { | |
197 | allwinner,pins = "PG3", "PG4"; | |
198 | allwinner,function = "uart1"; | |
199 | allwinner,drive = <0>; | |
200 | allwinner,pull = <0>; | |
201 | }; | |
9e2dcb2f | 202 | }; |
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203 | |
204 | timer@01c20c00 { | |
b6e1a53b | 205 | compatible = "allwinner,sun4i-timer"; |
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206 | reg = <0x01c20c00 0x90>; |
207 | interrupts = <22>; | |
208 | clocks = <&osc24M>; | |
209 | }; | |
210 | ||
211 | wdt: watchdog@01c20c90 { | |
0b19b7c2 | 212 | compatible = "allwinner,sun4i-wdt"; |
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213 | reg = <0x01c20c90 0x10>; |
214 | }; | |
215 | ||
216 | uart1: serial@01c28400 { | |
217 | compatible = "snps,dw-apb-uart"; | |
218 | reg = <0x01c28400 0x400>; | |
219 | interrupts = <2>; | |
220 | reg-shift = <2>; | |
221 | reg-io-width = <4>; | |
222 | clocks = <&apb1_gates 17>; | |
223 | status = "disabled"; | |
224 | }; | |
225 | ||
226 | uart3: serial@01c28c00 { | |
227 | compatible = "snps,dw-apb-uart"; | |
228 | reg = <0x01c28c00 0x400>; | |
229 | interrupts = <4>; | |
230 | reg-shift = <2>; | |
231 | reg-io-width = <4>; | |
232 | clocks = <&apb1_gates 19>; | |
233 | status = "disabled"; | |
234 | }; | |
9e2dcb2f | 235 | }; |
d4da2ebb | 236 | }; |