projects / mirror_ubuntu-zesty-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| e8f4351a MJ |
1 | /* |
| 2 | * Copyright 2016 Mylène Josserand | |
| 3 | * | |
| 4 | * Mylène Josserand <mylene.josserand@free-electrons.com> | |
| 5 | * | |
| 6 | * This file is dual-licensed: you can use it either under the terms | |
| 7 | * of the GPL or the X11 license, at your option. Note that this dual | |
| 8 | * licensing only applies to this file, and not this project as a | |
| 9 | * whole. | |
| 10 | * | |
| 11 | * a) This library is free software; you can redistribute it and/or | |
| 12 | * modify it under the terms of the GNU General Public License as | |
| 13 | * published by the Free Software Foundation; either version 2 of the | |
| 14 | * License, or (at your option) any later version. | |
| 15 | * | |
| 16 | * This library is distributed in the hope that it will be useful, | |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 19 | * GNU General Public License for more details. | |
| 20 | * | |
| 21 | * Or, alternatively, | |
| 22 | * | |
| 23 | * b) Permission is hereby granted, free of charge, to any person | |
| 24 | * obtaining a copy of this software and associated documentation | |
| 25 | * files (the "Software"), to deal in the Software without | |
| 26 | * restriction, including without limitation the rights to use, | |
| 27 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
| 28 | * sell copies of the Software, and to permit persons to whom the | |
| 29 | * Software is furnished to do so, subject to the following | |
| 30 | * conditions: | |
| 31 | * | |
| 32 | * The above copyright notice and this permission notice shall be | |
| 33 | * included in all copies or substantial portions of the Software. | |
| 34 | * | |
| 35 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 36 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
| 37 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 38 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
| 39 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
| 40 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
| 41 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 42 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 43 | */ | |
| 44 | ||
| 45 | #include <dt-bindings/clock/sun4i-a10-pll2.h> | |
| 46 | #include <dt-bindings/dma/sun4i-a10.h> | |
| 47 | #include <dt-bindings/pinctrl/sun4i-a10.h> | |
| 48 | ||
| 49 | / { | |
| 50 | interrupt-parent = <&intc>; | |
| 51 | #address-cells = <1>; | |
| 52 | #size-cells = <1>; | |
| 53 | ||
| 54 | cpus { | |
| 55 | #address-cells = <1>; | |
| 56 | #size-cells = <0>; | |
| 57 | ||
| 58 | cpu0: cpu@0 { | |
| 59 | device_type = "cpu"; | |
| 60 | compatible = "arm,cortex-a8"; | |
| 61 | reg = <0x0>; | |
| 62 | clocks = <&cpu>; | |
| 63 | }; | |
| 64 | }; | |
| 65 | ||
| 66 | clocks { | |
| 67 | #address-cells = <1>; | |
| 68 | #size-cells = <1>; | |
| 69 | ranges; | |
| 70 | ||
| 71 | /* | |
| 72 | * This is a dummy clock, to be used as placeholder on | |
| 73 | * other mux clocks when a specific parent clock is not | |
| 74 | * yet implemented. It should be dropped when the driver | |
| 75 | * is complete. | |
| 76 | */ | |
| 77 | dummy: dummy { | |
| 78 | #clock-cells = <0>; | |
| 79 | compatible = "fixed-clock"; | |
| 80 | clock-frequency = <0>; | |
| 81 | }; | |
| 82 | ||
| 83 | osc24M: clk@01c20050 { | |
| 84 | #clock-cells = <0>; | |
| 85 | compatible = "allwinner,sun4i-a10-osc-clk"; | |
| 86 | reg = <0x01c20050 0x4>; | |
| 87 | clock-frequency = <24000000>; | |
| 88 | clock-output-names = "osc24M"; | |
| 89 | }; | |
| 90 | ||
| 91 | osc3M: osc3M-clk { | |
| 92 | compatible = "fixed-factor-clock"; | |
| 93 | #clock-cells = <0>; | |
| 94 | clock-div = <8>; | |
| 95 | clock-mult = <1>; | |
| 96 | clocks = <&osc24M>; | |
| 97 | clock-output-names = "osc3M"; | |
| 98 | }; | |
| 99 | ||
| 100 | osc32k: clk@0 { | |
| 101 | #clock-cells = <0>; | |
| 102 | compatible = "fixed-clock"; | |
| 103 | clock-frequency = <32768>; | |
| 104 | clock-output-names = "osc32k"; | |
| 105 | }; | |
| 106 | ||
| 107 | pll1: clk@01c20000 { | |
| 108 | #clock-cells = <0>; | |
| 109 | compatible = "allwinner,sun4i-a10-pll1-clk"; | |
| 110 | reg = <0x01c20000 0x4>; | |
| 111 | clocks = <&osc24M>; | |
| 112 | clock-output-names = "pll1"; | |
| 113 | }; | |
| 114 | ||
| 115 | pll2: clk@01c20008 { | |
| 116 | #clock-cells = <1>; | |
| 117 | compatible = "allwinner,sun5i-a13-pll2-clk"; | |
| 118 | reg = <0x01c20008 0x8>; | |
| 119 | clocks = <&osc24M>; | |
| 120 | clock-output-names = "pll2-1x", "pll2-2x", | |
| 121 | "pll2-4x", "pll2-8x"; | |
| 122 | }; | |
| 123 | ||
| 124 | pll3: clk@01c20010 { | |
| 125 | #clock-cells = <0>; | |
| 126 | compatible = "allwinner,sun4i-a10-pll3-clk"; | |
| 127 | reg = <0x01c20010 0x4>; | |
| 128 | clocks = <&osc3M>; | |
| 129 | clock-output-names = "pll3"; | |
| 130 | }; | |
| 131 | ||
| 132 | pll3x2: pll3x2-clk { | |
| 133 | compatible = "allwinner,sun4i-a10-pll3-2x-clk"; | |
| 134 | #clock-cells = <0>; | |
| 135 | clock-div = <1>; | |
| 136 | clock-mult = <2>; | |
| 137 | clocks = <&pll3>; | |
| 138 | clock-output-names = "pll3-2x"; | |
| 139 | }; | |
| 140 | ||
| 141 | pll4: clk@01c20018 { | |
| 142 | #clock-cells = <0>; | |
| 143 | compatible = "allwinner,sun4i-a10-pll1-clk"; | |
| 144 | reg = <0x01c20018 0x4>; | |
| 145 | clocks = <&osc24M>; | |
| 146 | clock-output-names = "pll4"; | |
| 147 | }; | |
| 148 | ||
| 149 | pll5: clk@01c20020 { | |
| 150 | #clock-cells = <1>; | |
| 151 | compatible = "allwinner,sun4i-a10-pll5-clk"; | |
| 152 | reg = <0x01c20020 0x4>; | |
| 153 | clocks = <&osc24M>; | |
| 154 | clock-output-names = "pll5_ddr", "pll5_other"; | |
| 155 | }; | |
| 156 | ||
| 157 | pll6: clk@01c20028 { | |
| 158 | #clock-cells = <1>; | |
| 159 | compatible = "allwinner,sun4i-a10-pll6-clk"; | |
| 160 | reg = <0x01c20028 0x4>; | |
| 161 | clocks = <&osc24M>; | |
| 162 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
| 163 | }; | |
| 164 | ||
| 165 | pll7: clk@01c20030 { | |
| 166 | #clock-cells = <0>; | |
| 167 | compatible = "allwinner,sun4i-a10-pll3-clk"; | |
| 168 | reg = <0x01c20030 0x4>; | |
| 169 | clocks = <&osc3M>; | |
| 170 | clock-output-names = "pll7"; | |
| 171 | }; | |
| 172 | ||
| 173 | pll7x2: pll7x2-clk { | |
| 174 | compatible = "allwinner,sun4i-a10-pll3-2x-clk"; | |
| 175 | #clock-cells = <0>; | |
| 176 | clock-div = <1>; | |
| 177 | clock-mult = <2>; | |
| 178 | clocks = <&pll7>; | |
| 179 | clock-output-names = "pll7-2x"; | |
| 180 | }; | |
| 181 | ||
| 182 | /* dummy is 200M */ | |
| 183 | cpu: cpu@01c20054 { | |
| 184 | #clock-cells = <0>; | |
| 185 | compatible = "allwinner,sun4i-a10-cpu-clk"; | |
| 186 | reg = <0x01c20054 0x4>; | |
| 187 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
| 188 | clock-output-names = "cpu"; | |
| 189 | }; | |
| 190 | ||
| 191 | axi: axi@01c20054 { | |
| 192 | #clock-cells = <0>; | |
| 193 | compatible = "allwinner,sun4i-a10-axi-clk"; | |
| 194 | reg = <0x01c20054 0x4>; | |
| 195 | clocks = <&cpu>; | |
| 196 | clock-output-names = "axi"; | |
| 197 | }; | |
| 198 | ||
| 199 | ahb: ahb@01c20054 { | |
| 200 | #clock-cells = <0>; | |
| 201 | compatible = "allwinner,sun5i-a13-ahb-clk"; | |
| 202 | reg = <0x01c20054 0x4>; | |
| 203 | clocks = <&axi>, <&cpu>, <&pll6 1>; | |
| 204 | clock-output-names = "ahb"; | |
| 205 | /* | |
| 206 | * Use PLL6 as parent, instead of CPU/AXI | |
| 207 | * which has rate changes due to cpufreq | |
| 208 | */ | |
| 209 | assigned-clocks = <&ahb>; | |
| 210 | assigned-clock-parents = <&pll6 1>; | |
| 211 | }; | |
| 212 | ||
| 213 | apb0: apb0@01c20054 { | |
| 214 | #clock-cells = <0>; | |
| 215 | compatible = "allwinner,sun4i-a10-apb0-clk"; | |
| 216 | reg = <0x01c20054 0x4>; | |
| 217 | clocks = <&ahb>; | |
| 218 | clock-output-names = "apb0"; | |
| 219 | }; | |
| 220 | ||
| 221 | apb1: clk@01c20058 { | |
| 222 | #clock-cells = <0>; | |
| 223 | compatible = "allwinner,sun4i-a10-apb1-clk"; | |
| 224 | reg = <0x01c20058 0x4>; | |
| 225 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; | |
| 226 | clock-output-names = "apb1"; | |
| 227 | }; | |
| 228 | ||
| 229 | axi_gates: clk@01c2005c { | |
| 230 | #clock-cells = <1>; | |
| 231 | compatible = "allwinner,sun4i-a10-gates-clk"; | |
| 232 | reg = <0x01c2005c 0x4>; | |
| 233 | clocks = <&axi>; | |
| 234 | clock-indices = <0>; | |
| 235 | clock-output-names = "axi_dram"; | |
| 236 | }; | |
| 237 | ||
| 238 | ahb_gates: clk@01c20060 { | |
| 239 | #clock-cells = <1>; | |
| 240 | compatible = "allwinner,sun5i-a13-ahb-gates-clk"; | |
| 241 | reg = <0x01c20060 0x8>; | |
| 242 | clocks = <&ahb>; | |
| 243 | clock-indices = <0>, <1>, | |
| 244 | <2>, <5>, <6>, | |
| 245 | <7>, <8>, <9>, | |
| 246 | <10>, <13>, | |
| 247 | <14>, <17>, <20>, | |
| 248 | <21>, <22>, | |
| 249 | <28>, <32>, <34>, | |
| 250 | <36>, <40>, <44>, | |
| 251 | <46>, <51>, | |
| 252 | <52>; | |
| 253 | clock-output-names = "ahb_usbotg", "ahb_ehci", | |
| 254 | "ahb_ohci", "ahb_ss", "ahb_dma", | |
| 255 | "ahb_bist", "ahb_mmc0", "ahb_mmc1", | |
| 256 | "ahb_mmc2", "ahb_nand", | |
| 257 | "ahb_sdram", "ahb_emac", "ahb_spi0", | |
| 258 | "ahb_spi1", "ahb_spi2", | |
| 259 | "ahb_hstimer", "ahb_ve", "ahb_tve", | |
| 260 | "ahb_lcd", "ahb_csi", "ahb_de_be", | |
| 261 | "ahb_de_fe", "ahb_iep", | |
| 262 | "ahb_mali400"; | |
| 263 | }; | |
| 264 | ||
| 265 | apb0_gates: clk@01c20068 { | |
| 266 | #clock-cells = <1>; | |
| 267 | compatible = "allwinner,sun4i-a10-gates-clk"; | |
| 268 | reg = <0x01c20068 0x4>; | |
| 269 | clocks = <&apb0>; | |
| 270 | clock-indices = <0>, <3>, | |
| 271 | <5>, <6>; | |
| 272 | clock-output-names = "apb0_codec", "apb0_i2s0", | |
| 273 | "apb0_pio", "apb0_ir"; | |
| 274 | }; | |
| 275 | ||
| 276 | apb1_gates: clk@01c2006c { | |
| 277 | #clock-cells = <1>; | |
| 278 | compatible = "allwinner,sun4i-a10-gates-clk"; | |
| 279 | reg = <0x01c2006c 0x4>; | |
| 280 | clocks = <&apb1>; | |
| 281 | clock-indices = <0>, <1>, | |
| 282 | <2>, <17>, | |
| 283 | <18>, <19>; | |
| 284 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
| 285 | "apb1_i2c2", "apb1_uart1", | |
| 286 | "apb1_uart2", "apb1_uart3"; | |
| 287 | }; | |
| 288 | ||
| 289 | nand_clk: clk@01c20080 { | |
| 290 | #clock-cells = <0>; | |
| 291 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 292 | reg = <0x01c20080 0x4>; | |
| 293 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 294 | clock-output-names = "nand"; | |
| 295 | }; | |
| 296 | ||
| 297 | ms_clk: clk@01c20084 { | |
| 298 | #clock-cells = <0>; | |
| 299 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 300 | reg = <0x01c20084 0x4>; | |
| 301 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 302 | clock-output-names = "ms"; | |
| 303 | }; | |
| 304 | ||
| 305 | mmc0_clk: clk@01c20088 { | |
| 306 | #clock-cells = <1>; | |
| 307 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
| 308 | reg = <0x01c20088 0x4>; | |
| 309 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 310 | clock-output-names = "mmc0", | |
| 311 | "mmc0_output", | |
| 312 | "mmc0_sample"; | |
| 313 | }; | |
| 314 | ||
| 315 | mmc1_clk: clk@01c2008c { | |
| 316 | #clock-cells = <1>; | |
| 317 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
| 318 | reg = <0x01c2008c 0x4>; | |
| 319 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 320 | clock-output-names = "mmc1", | |
| 321 | "mmc1_output", | |
| 322 | "mmc1_sample"; | |
| 323 | }; | |
| 324 | ||
| 325 | mmc2_clk: clk@01c20090 { | |
| 326 | #clock-cells = <1>; | |
| 327 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
| 328 | reg = <0x01c20090 0x4>; | |
| 329 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 330 | clock-output-names = "mmc2", | |
| 331 | "mmc2_output", | |
| 332 | "mmc2_sample"; | |
| 333 | }; | |
| 334 | ||
| 335 | ts_clk: clk@01c20098 { | |
| 336 | #clock-cells = <0>; | |
| 337 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 338 | reg = <0x01c20098 0x4>; | |
| 339 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 340 | clock-output-names = "ts"; | |
| 341 | }; | |
| 342 | ||
| 343 | ss_clk: clk@01c2009c { | |
| 344 | #clock-cells = <0>; | |
| 345 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 346 | reg = <0x01c2009c 0x4>; | |
| 347 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 348 | clock-output-names = "ss"; | |
| 349 | }; | |
| 350 | ||
| 351 | spi0_clk: clk@01c200a0 { | |
| 352 | #clock-cells = <0>; | |
| 353 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 354 | reg = <0x01c200a0 0x4>; | |
| 355 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 356 | clock-output-names = "spi0"; | |
| 357 | }; | |
| 358 | ||
| 359 | spi1_clk: clk@01c200a4 { | |
| 360 | #clock-cells = <0>; | |
| 361 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 362 | reg = <0x01c200a4 0x4>; | |
| 363 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 364 | clock-output-names = "spi1"; | |
| 365 | }; | |
| 366 | ||
| 367 | spi2_clk: clk@01c200a8 { | |
| 368 | #clock-cells = <0>; | |
| 369 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 370 | reg = <0x01c200a8 0x4>; | |
| 371 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 372 | clock-output-names = "spi2"; | |
| 373 | }; | |
| 374 | ||
| 375 | ir0_clk: clk@01c200b0 { | |
| 376 | #clock-cells = <0>; | |
| 377 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 378 | reg = <0x01c200b0 0x4>; | |
| 379 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 380 | clock-output-names = "ir0"; | |
| 381 | }; | |
| 382 | ||
| 383 | i2s0_clk: clk@01c200b8 { | |
| 384 | #clock-cells = <0>; | |
| 385 | compatible = "allwinner,sun4i-a10-mod1-clk"; | |
| 386 | reg = <0x01c200b8 0x4>; | |
| 387 | clocks = <&pll2 SUN4I_A10_PLL2_8X>, | |
| 388 | <&pll2 SUN4I_A10_PLL2_4X>, | |
| 389 | <&pll2 SUN4I_A10_PLL2_2X>, | |
| 390 | <&pll2 SUN4I_A10_PLL2_1X>; | |
| 391 | clock-output-names = "i2s0"; | |
| 392 | }; | |
| 393 | ||
| 394 | spdif_clk: clk@01c200c0 { | |
| 395 | #clock-cells = <0>; | |
| 396 | compatible = "allwinner,sun4i-a10-mod1-clk"; | |
| 397 | reg = <0x01c200c0 0x4>; | |
| 398 | clocks = <&pll2 SUN4I_A10_PLL2_8X>, | |
| 399 | <&pll2 SUN4I_A10_PLL2_4X>, | |
| 400 | <&pll2 SUN4I_A10_PLL2_2X>, | |
| 401 | <&pll2 SUN4I_A10_PLL2_1X>; | |
| 402 | clock-output-names = "spdif"; | |
| 403 | }; | |
| 404 | ||
| 405 | usb_clk: clk@01c200cc { | |
| 406 | #clock-cells = <1>; | |
| 407 | #reset-cells = <1>; | |
| 408 | compatible = "allwinner,sun5i-a13-usb-clk"; | |
| 409 | reg = <0x01c200cc 0x4>; | |
| 410 | clocks = <&pll6 1>; | |
| 411 | clock-output-names = "usb_ohci0", "usb_phy"; | |
| 412 | }; | |
| 413 | ||
| 414 | dram_gates: clk@01c20100 { | |
| 415 | #clock-cells = <1>; | |
| 416 | compatible = "nextthing,gr8-dram-gates-clk", | |
| 417 | "allwinner,sun4i-a10-gates-clk"; | |
| 418 | reg = <0x01c20100 0x4>; | |
| 419 | clocks = <&pll5 0>; | |
| 420 | clock-indices = <0>, | |
| 421 | <1>, | |
| 422 | <25>, | |
| 423 | <26>, | |
| 424 | <29>, | |
| 425 | <31>; | |
| 426 | clock-output-names = "dram_ve", | |
| 427 | "dram_csi", | |
| 428 | "dram_de_fe", | |
| 429 | "dram_de_be", | |
| 430 | "dram_ace", | |
| 431 | "dram_iep"; | |
| 432 | }; | |
| 433 | ||
| 434 | de_be_clk: clk@01c20104 { | |
| 435 | #clock-cells = <0>; | |
| 436 | #reset-cells = <0>; | |
| 437 | compatible = "allwinner,sun4i-a10-display-clk"; | |
| 438 | reg = <0x01c20104 0x4>; | |
| 439 | clocks = <&pll3>, <&pll7>, <&pll5 1>; | |
| 440 | clock-output-names = "de-be"; | |
| 441 | }; | |
| 442 | ||
| 443 | de_fe_clk: clk@01c2010c { | |
| 444 | #clock-cells = <0>; | |
| 445 | #reset-cells = <0>; | |
| 446 | compatible = "allwinner,sun4i-a10-display-clk"; | |
| 447 | reg = <0x01c2010c 0x4>; | |
| 448 | clocks = <&pll3>, <&pll7>, <&pll5 1>; | |
| 449 | clock-output-names = "de-fe"; | |
| 450 | }; | |
| 451 | ||
| 452 | tcon_ch0_clk: clk@01c20118 { | |
| 453 | #clock-cells = <0>; | |
| 454 | #reset-cells = <1>; | |
| 455 | compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; | |
| 456 | reg = <0x01c20118 0x4>; | |
| 457 | clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; | |
| 458 | clock-output-names = "tcon-ch0-sclk"; | |
| 459 | }; | |
| 460 | ||
| 461 | tcon_ch1_clk: clk@01c2012c { | |
| 462 | #clock-cells = <0>; | |
| 463 | compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; | |
| 464 | reg = <0x01c2012c 0x4>; | |
| 465 | clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; | |
| 466 | clock-output-names = "tcon-ch1-sclk"; | |
| 467 | }; | |
| 468 | ||
| 469 | codec_clk: clk@01c20140 { | |
| 470 | #clock-cells = <0>; | |
| 471 | compatible = "allwinner,sun4i-a10-codec-clk"; | |
| 472 | reg = <0x01c20140 0x4>; | |
| 473 | clocks = <&pll2 SUN4I_A10_PLL2_1X>; | |
| 474 | clock-output-names = "codec"; | |
| 475 | }; | |
| 476 | ||
| 477 | mbus_clk: clk@01c2015c { | |
| 478 | #clock-cells = <0>; | |
| 479 | compatible = "allwinner,sun5i-a13-mbus-clk"; | |
| 480 | reg = <0x01c2015c 0x4>; | |
| 481 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 482 | clock-output-names = "mbus"; | |
| 483 | }; | |
| 484 | }; | |
| 485 | ||
| 486 | display-engine { | |
| 487 | compatible = "allwinner,sun5i-a13-display-engine"; | |
| 488 | allwinner,pipelines = <&fe0>; | |
| 489 | }; | |
| 490 | ||
| 491 | soc@01c00000 { | |
| 492 | compatible = "simple-bus"; | |
| 493 | #address-cells = <1>; | |
| 494 | #size-cells = <1>; | |
| 495 | ranges; | |
| 496 | ||
| 497 | sram-controller@01c00000 { | |
| 498 | compatible = "allwinner,sun4i-a10-sram-controller"; | |
| 499 | reg = <0x01c00000 0x30>; | |
| 500 | #address-cells = <1>; | |
| 501 | #size-cells = <1>; | |
| 502 | ranges; | |
| 503 | ||
| 504 | sram_a: sram@00000000 { | |
| 505 | compatible = "mmio-sram"; | |
| 506 | reg = <0x00000000 0xc000>; | |
| 507 | #address-cells = <1>; | |
| 508 | #size-cells = <1>; | |
| 509 | ranges = <0 0x00000000 0xc000>; | |
| 510 | }; | |
| 511 | ||
| 512 | sram_d: sram@00010000 { | |
| 513 | compatible = "mmio-sram"; | |
| 514 | reg = <0x00010000 0x1000>; | |
| 515 | #address-cells = <1>; | |
| 516 | #size-cells = <1>; | |
| 517 | ranges = <0 0x00010000 0x1000>; | |
| 518 | ||
| 519 | otg_sram: sram-section@0000 { | |
| 520 | compatible = "allwinner,sun4i-a10-sram-d"; | |
| 521 | reg = <0x0000 0x1000>; | |
| 522 | status = "disabled"; | |
| 523 | }; | |
| 524 | }; | |
| 525 | }; | |
| 526 | ||
| 527 | dma: dma-controller@01c02000 { | |
| 528 | compatible = "allwinner,sun4i-a10-dma"; | |
| 529 | reg = <0x01c02000 0x1000>; | |
| 530 | interrupts = <27>; | |
| 531 | clocks = <&ahb_gates 6>; | |
| 532 | #dma-cells = <2>; | |
| 533 | }; | |
| 534 | ||
| 535 | nfc: nand@01c03000 { | |
| 536 | compatible = "allwinner,sun4i-a10-nand"; | |
| 537 | reg = <0x01c03000 0x1000>; | |
| 538 | interrupts = <37>; | |
| 539 | clocks = <&ahb_gates 13>, <&nand_clk>; | |
| 540 | clock-names = "ahb", "mod"; | |
| 541 | dmas = <&dma SUN4I_DMA_DEDICATED 3>; | |
| 542 | dma-names = "rxtx"; | |
| 543 | status = "disabled"; | |
| 544 | #address-cells = <1>; | |
| 545 | #size-cells = <0>; | |
| 546 | }; | |
| 547 | ||
| 548 | spi0: spi@01c05000 { | |
| 549 | compatible = "allwinner,sun4i-a10-spi"; | |
| 550 | reg = <0x01c05000 0x1000>; | |
| 551 | interrupts = <10>; | |
| 552 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
| 553 | clock-names = "ahb", "mod"; | |
| 554 | dmas = <&dma SUN4I_DMA_DEDICATED 27>, | |
| 555 | <&dma SUN4I_DMA_DEDICATED 26>; | |
| 556 | dma-names = "rx", "tx"; | |
| 557 | status = "disabled"; | |
| 558 | #address-cells = <1>; | |
| 559 | #size-cells = <0>; | |
| 560 | }; | |
| 561 | ||
| 562 | spi1: spi@01c06000 { | |
| 563 | compatible = "allwinner,sun4i-a10-spi"; | |
| 564 | reg = <0x01c06000 0x1000>; | |
| 565 | interrupts = <11>; | |
| 566 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
| 567 | clock-names = "ahb", "mod"; | |
| 568 | dmas = <&dma SUN4I_DMA_DEDICATED 9>, | |
| 569 | <&dma SUN4I_DMA_DEDICATED 8>; | |
| 570 | dma-names = "rx", "tx"; | |
| 571 | status = "disabled"; | |
| 572 | #address-cells = <1>; | |
| 573 | #size-cells = <0>; | |
| 574 | }; | |
| 575 | ||
| 576 | tve0: tv-encoder@01c0a000 { | |
| 577 | compatible = "allwinner,sun4i-a10-tv-encoder"; | |
| 578 | reg = <0x01c0a000 0x1000>; | |
| 579 | clocks = <&ahb_gates 34>; | |
| 580 | resets = <&tcon_ch0_clk 0>; | |
| 581 | status = "disabled"; | |
| 582 | ||
| 583 | port { | |
| 584 | #address-cells = <1>; | |
| 585 | #size-cells = <0>; | |
| 586 | ||
| 587 | tve0_in_tcon0: endpoint@0 { | |
| 588 | reg = <0>; | |
| 589 | remote-endpoint = <&tcon0_out_tve0>; | |
| 590 | }; | |
| 591 | }; | |
| 592 | }; | |
| 593 | ||
| 594 | tcon0: lcd-controller@01c0c000 { | |
| 595 | compatible = "allwinner,sun5i-a13-tcon"; | |
| 596 | reg = <0x01c0c000 0x1000>; | |
| 597 | interrupts = <44>; | |
| 598 | resets = <&tcon_ch0_clk 1>; | |
| 599 | reset-names = "lcd"; | |
| 600 | clocks = <&ahb_gates 36>, | |
| 601 | <&tcon_ch0_clk>, | |
| 602 | <&tcon_ch1_clk>; | |
| 603 | clock-names = "ahb", | |
| 604 | "tcon-ch0", | |
| 605 | "tcon-ch1"; | |
| 606 | clock-output-names = "tcon-pixel-clock"; | |
| 607 | status = "disabled"; | |
| 608 | ||
| 609 | ports { | |
| 610 | #address-cells = <1>; | |
| 611 | #size-cells = <0>; | |
| 612 | ||
| 613 | tcon0_in: port@0 { | |
| 614 | #address-cells = <1>; | |
| 615 | #size-cells = <0>; | |
| 616 | reg = <0>; | |
| 617 | ||
| 618 | tcon0_in_be0: endpoint@0 { | |
| 619 | reg = <0>; | |
| 620 | remote-endpoint = <&be0_out_tcon0>; | |
| 621 | }; | |
| 622 | }; | |
| 623 | ||
| 624 | tcon0_out: port@1 { | |
| 625 | #address-cells = <1>; | |
| 626 | #size-cells = <0>; | |
| 627 | reg = <1>; | |
| 628 | ||
| 629 | tcon0_out_tve0: endpoint@1 { | |
| 630 | reg = <1>; | |
| 631 | remote-endpoint = <&tve0_in_tcon0>; | |
| 632 | }; | |
| 633 | }; | |
| 634 | }; | |
| 635 | }; | |
| 636 | ||
| 637 | mmc0: mmc@01c0f000 { | |
| 638 | compatible = "allwinner,sun5i-a13-mmc"; | |
| 639 | reg = <0x01c0f000 0x1000>; | |
| 640 | clocks = <&ahb_gates 8>, | |
| 641 | <&mmc0_clk 0>, | |
| 642 | <&mmc0_clk 1>, | |
| 643 | <&mmc0_clk 2>; | |
| 644 | clock-names = "ahb", | |
| 645 | "mmc", | |
| 646 | "output", | |
| 647 | "sample"; | |
| 648 | interrupts = <32>; | |
| 649 | status = "disabled"; | |
| 650 | #address-cells = <1>; | |
| 651 | #size-cells = <0>; | |
| 652 | }; | |
| 653 | ||
| 654 | mmc1: mmc@01c10000 { | |
| 655 | compatible = "allwinner,sun5i-a13-mmc"; | |
| 656 | reg = <0x01c10000 0x1000>; | |
| 657 | clocks = <&ahb_gates 9>, | |
| 658 | <&mmc1_clk 0>, | |
| 659 | <&mmc1_clk 1>, | |
| 660 | <&mmc1_clk 2>; | |
| 661 | clock-names = "ahb", | |
| 662 | "mmc", | |
| 663 | "output", | |
| 664 | "sample"; | |
| 665 | interrupts = <33>; | |
| 666 | status = "disabled"; | |
| 667 | #address-cells = <1>; | |
| 668 | #size-cells = <0>; | |
| 669 | }; | |
| 670 | ||
| 671 | mmc2: mmc@01c11000 { | |
| 672 | compatible = "allwinner,sun5i-a13-mmc"; | |
| 673 | reg = <0x01c11000 0x1000>; | |
| 674 | clocks = <&ahb_gates 10>, | |
| 675 | <&mmc2_clk 0>, | |
| 676 | <&mmc2_clk 1>, | |
| 677 | <&mmc2_clk 2>; | |
| 678 | clock-names = "ahb", | |
| 679 | "mmc", | |
| 680 | "output", | |
| 681 | "sample"; | |
| 682 | interrupts = <34>; | |
| 683 | status = "disabled"; | |
| 684 | #address-cells = <1>; | |
| 685 | #size-cells = <0>; | |
| 686 | }; | |
| 687 | ||
| 688 | usb_otg: usb@01c13000 { | |
| 689 | compatible = "allwinner,sun4i-a10-musb"; | |
| 690 | reg = <0x01c13000 0x0400>; | |
| 691 | clocks = <&ahb_gates 0>; | |
| 692 | interrupts = <38>; | |
| 693 | interrupt-names = "mc"; | |
| 694 | phys = <&usbphy 0>; | |
| 695 | phy-names = "usb"; | |
| 696 | extcon = <&usbphy 0>; | |
| 697 | allwinner,sram = <&otg_sram 1>; | |
| 698 | status = "disabled"; | |
| 699 | ||
| 700 | dr_mode = "otg"; | |
| 701 | }; | |
| 702 | ||
| 703 | usbphy: phy@01c13400 { | |
| 704 | #phy-cells = <1>; | |
| 705 | compatible = "allwinner,sun5i-a13-usb-phy"; | |
| 706 | reg = <0x01c13400 0x10 0x01c14800 0x4>; | |
| 707 | reg-names = "phy_ctrl", "pmu1"; | |
| 708 | clocks = <&usb_clk 8>; | |
| 709 | clock-names = "usb_phy"; | |
| 710 | resets = <&usb_clk 0>, <&usb_clk 1>; | |
| 711 | reset-names = "usb0_reset", "usb1_reset"; | |
| 712 | status = "disabled"; | |
| 713 | }; | |
| 714 | ||
| 715 | ehci0: usb@01c14000 { | |
| 716 | compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; | |
| 717 | reg = <0x01c14000 0x100>; | |
| 718 | interrupts = <39>; | |
| 719 | clocks = <&ahb_gates 1>; | |
| 720 | phys = <&usbphy 1>; | |
| 721 | phy-names = "usb"; | |
| 722 | status = "disabled"; | |
| 723 | }; | |
| 724 | ||
| 725 | ohci0: usb@01c14400 { | |
| 726 | compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; | |
| 727 | reg = <0x01c14400 0x100>; | |
| 728 | interrupts = <40>; | |
| 729 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
| 730 | phys = <&usbphy 1>; | |
| 731 | phy-names = "usb"; | |
| 732 | status = "disabled"; | |
| 733 | }; | |
| 734 | ||
| 735 | spi2: spi@01c17000 { | |
| 736 | compatible = "allwinner,sun4i-a10-spi"; | |
| 737 | reg = <0x01c17000 0x1000>; | |
| 738 | interrupts = <12>; | |
| 739 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
| 740 | clock-names = "ahb", "mod"; | |
| 741 | dmas = <&dma SUN4I_DMA_DEDICATED 29>, | |
| 742 | <&dma SUN4I_DMA_DEDICATED 28>; | |
| 743 | dma-names = "rx", "tx"; | |
| 744 | status = "disabled"; | |
| 745 | #address-cells = <1>; | |
| 746 | #size-cells = <0>; | |
| 747 | }; | |
| 748 | ||
| 749 | intc: interrupt-controller@01c20400 { | |
| 750 | compatible = "allwinner,sun4i-a10-ic"; | |
| 751 | reg = <0x01c20400 0x400>; | |
| 752 | interrupt-controller; | |
| 753 | #interrupt-cells = <1>; | |
| 754 | }; | |
| 755 | ||
| 756 | pio: pinctrl@01c20800 { | |
| 757 | compatible = "nextthing,gr8-pinctrl"; | |
| 758 | reg = <0x01c20800 0x400>; | |
| 759 | interrupts = <28>; | |
| 760 | clocks = <&apb0_gates 5>; | |
| 761 | gpio-controller; | |
| 762 | interrupt-controller; | |
| 763 | #interrupt-cells = <3>; | |
| 764 | #gpio-cells = <3>; | |
| 765 | ||
| 766 | i2c0_pins_a: i2c0@0 { | |
| 767 | allwinner,pins = "PB0", "PB1"; | |
| 768 | allwinner,function = "i2c0"; | |
| 769 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 770 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 771 | }; | |
| 772 | ||
| 773 | i2c1_pins_a: i2c1@0 { | |
| 774 | allwinner,pins = "PB15", "PB16"; | |
| 775 | allwinner,function = "i2c1"; | |
| 776 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 777 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 778 | }; | |
| 779 | ||
| 780 | i2c2_pins_a: i2c2@0 { | |
| 781 | allwinner,pins = "PB17", "PB18"; | |
| 782 | allwinner,function = "i2c2"; | |
| 783 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 784 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 785 | }; | |
| 786 | ||
| 787 | i2s0_data_pins_a: i2s0-data@0 { | |
| 788 | allwinner,pins = "PB6", "PB7", "PB8", "PB9"; | |
| 789 | allwinner,function = "i2s0"; | |
| 790 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 791 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 792 | }; | |
| 793 | ||
| 794 | i2s0_mclk_pins_a: i2s0-mclk@0 { | |
| e900146c | 795 | allwinner,pins = "PB5"; |
| e8f4351a MJ |
796 | allwinner,function = "i2s0"; |
| 797 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 798 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 799 | }; | |
| 800 | ||
| 801 | ir0_rx_pins_a: ir0@0 { | |
| 802 | allwinner,pins = "PB4"; | |
| 803 | allwinner,function = "ir0"; | |
| 804 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 805 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 806 | }; | |
| 807 | ||
| 808 | lcd_rgb666_pins: lcd-rgb666@0 { | |
| 809 | allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", | |
| 810 | "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", | |
| 811 | "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", | |
| 812 | "PD24", "PD25", "PD26", "PD27"; | |
| 813 | allwinner,function = "lcd0"; | |
| 814 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 815 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 816 | }; | |
| 817 | ||
| 818 | mmc0_pins_a: mmc0@0 { | |
| 819 | allwinner,pins = "PF0", "PF1", "PF2", "PF3", | |
| 820 | "PF4", "PF5"; | |
| 821 | allwinner,function = "mmc0"; | |
| 822 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; | |
| 823 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 824 | }; | |
| 825 | ||
| 826 | nand_pins_a: nand-base0@0 { | |
| 827 | allwinner,pins = "PC0", "PC1", "PC2", | |
| 828 | "PC5", "PC8", "PC9", "PC10", | |
| 829 | "PC11", "PC12", "PC13", "PC14", | |
| 830 | "PC15"; | |
| 831 | allwinner,function = "nand0"; | |
| 832 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 833 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 834 | }; | |
| 835 | ||
| 836 | nand_cs0_pins_a: nand-cs@0 { | |
| 837 | allwinner,pins = "PC4"; | |
| 838 | allwinner,function = "nand0"; | |
| 839 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 840 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 841 | }; | |
| 842 | ||
| 843 | nand_rb0_pins_a: nand-rb@0 { | |
| 844 | allwinner,pins = "PC6"; | |
| 845 | allwinner,function = "nand0"; | |
| 846 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 847 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 848 | }; | |
| 849 | ||
| 850 | pwm0_pins_a: pwm0@0 { | |
| 851 | allwinner,pins = "PB2"; | |
| 852 | allwinner,function = "pwm0"; | |
| 853 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 854 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 855 | }; | |
| 856 | ||
| aade6b90 MR |
857 | pwm1_pins: pwm1 { |
| 858 | allwinner,pins = "PG13"; | |
| 859 | allwinner,function = "pwm1"; | |
| 860 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 861 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 862 | }; | |
| 863 | ||
| e8f4351a MJ |
864 | spdif_tx_pins_a: spdif@0 { |
| 865 | allwinner,pins = "PB10"; | |
| 866 | allwinner,function = "spdif"; | |
| 867 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 868 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
| 869 | }; | |
| 870 | ||
| 871 | uart1_pins_a: uart1@1 { | |
| 872 | allwinner,pins = "PG3", "PG4"; | |
| 873 | allwinner,function = "uart1"; | |
| 874 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 875 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 876 | }; | |
| 877 | ||
| 878 | uart1_cts_rts_pins_a: uart1-cts-rts@0 { | |
| 879 | allwinner,pins = "PG5", "PG6"; | |
| 880 | allwinner,function = "uart1"; | |
| 881 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 882 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 883 | }; | |
| 7c432442 MR |
884 | |
| 885 | uart2_pins_a: uart2@1 { | |
| 886 | allwinner,pins = "PD2", "PD3"; | |
| 887 | allwinner,function = "uart2"; | |
| 888 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 889 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 890 | }; | |
| 891 | ||
| 892 | uart2_cts_rts_pins_a: uart2-cts-rts@0 { | |
| 893 | allwinner,pins = "PD4", "PD5"; | |
| 894 | allwinner,function = "uart2"; | |
| 895 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 896 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 897 | }; | |
| 15df8ad9 MR |
898 | |
| 899 | uart3_pins_a: uart3@1 { | |
| 900 | allwinner,pins = "PG9", "PG10"; | |
| 901 | allwinner,function = "uart3"; | |
| 902 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 903 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 904 | }; | |
| 905 | ||
| 906 | uart3_cts_rts_pins_a: uart3-cts-rts@0 { | |
| 907 | allwinner,pins = "PG11", "PG12"; | |
| 908 | allwinner,function = "uart3"; | |
| 909 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 910 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 911 | }; | |
| e8f4351a MJ |
912 | }; |
| 913 | ||
| 914 | pwm: pwm@01c20e00 { | |
| 915 | compatible = "allwinner,sun5i-a10s-pwm"; | |
| 916 | reg = <0x01c20e00 0xc>; | |
| 917 | clocks = <&osc24M>; | |
| 918 | #pwm-cells = <3>; | |
| 919 | status = "disabled"; | |
| 920 | }; | |
| 921 | ||
| 922 | timer@01c20c00 { | |
| 923 | compatible = "allwinner,sun4i-a10-timer"; | |
| 924 | reg = <0x01c20c00 0x90>; | |
| 925 | interrupts = <22>; | |
| 926 | clocks = <&osc24M>; | |
| 927 | }; | |
| 928 | ||
| 929 | wdt: watchdog@01c20c90 { | |
| 930 | compatible = "allwinner,sun4i-a10-wdt"; | |
| 931 | reg = <0x01c20c90 0x10>; | |
| 932 | }; | |
| 933 | ||
| 934 | spdif: spdif@01c21000 { | |
| 935 | #sound-dai-cells = <0>; | |
| 936 | compatible = "allwinner,sun4i-a10-spdif"; | |
| 937 | reg = <0x01c21000 0x400>; | |
| 938 | interrupts = <13>; | |
| 939 | clocks = <&apb0_gates 1>, <&spdif_clk>; | |
| 940 | clock-names = "apb", "spdif"; | |
| 941 | dmas = <&dma SUN4I_DMA_NORMAL 2>, | |
| 942 | <&dma SUN4I_DMA_NORMAL 2>; | |
| 943 | dma-names = "rx", "tx"; | |
| 944 | status = "disabled"; | |
| 945 | }; | |
| 946 | ||
| 947 | ir0: ir@01c21800 { | |
| 948 | compatible = "allwinner,sun4i-a10-ir"; | |
| 949 | clocks = <&apb0_gates 6>, <&ir0_clk>; | |
| 950 | clock-names = "apb", "ir"; | |
| 951 | interrupts = <5>; | |
| 952 | reg = <0x01c21800 0x40>; | |
| 953 | status = "disabled"; | |
| 954 | }; | |
| 955 | ||
| 956 | i2s0: i2s@01c22400 { | |
| 957 | #sound-dai-cells = <0>; | |
| 958 | compatible = "allwinner,sun4i-a10-i2s"; | |
| 959 | reg = <0x01c22400 0x400>; | |
| 960 | interrupts = <16>; | |
| 961 | clocks = <&apb0_gates 3>, <&i2s0_clk>; | |
| 962 | clock-names = "apb", "mod"; | |
| 963 | dmas = <&dma SUN4I_DMA_NORMAL 3>, | |
| 964 | <&dma SUN4I_DMA_NORMAL 3>; | |
| 965 | dma-names = "rx", "tx"; | |
| 966 | status = "disabled"; | |
| 967 | }; | |
| 968 | ||
| 969 | lradc: lradc@01c22800 { | |
| 970 | compatible = "allwinner,sun4i-a10-lradc-keys"; | |
| 971 | reg = <0x01c22800 0x100>; | |
| 972 | interrupts = <31>; | |
| 973 | status = "disabled"; | |
| 974 | }; | |
| 975 | ||
| 976 | codec: codec@01c22c00 { | |
| 977 | #sound-dai-cells = <0>; | |
| 978 | compatible = "allwinner,sun4i-a10-codec"; | |
| 979 | reg = <0x01c22c00 0x40>; | |
| 980 | interrupts = <30>; | |
| 981 | clocks = <&apb0_gates 0>, <&codec_clk>; | |
| 982 | clock-names = "apb", "codec"; | |
| 983 | dmas = <&dma SUN4I_DMA_NORMAL 19>, | |
| 984 | <&dma SUN4I_DMA_NORMAL 19>; | |
| 985 | dma-names = "rx", "tx"; | |
| 986 | status = "disabled"; | |
| 987 | }; | |
| 988 | ||
| 989 | rtp: rtp@01c25000 { | |
| 990 | compatible = "allwinner,sun5i-a13-ts"; | |
| 991 | reg = <0x01c25000 0x100>; | |
| 992 | interrupts = <29>; | |
| 993 | #thermal-sensor-cells = <0>; | |
| 994 | }; | |
| 995 | ||
| 996 | uart1: serial@01c28400 { | |
| 997 | compatible = "snps,dw-apb-uart"; | |
| 998 | reg = <0x01c28400 0x400>; | |
| 999 | interrupts = <2>; | |
| 1000 | reg-shift = <2>; | |
| 1001 | reg-io-width = <4>; | |
| 1002 | clocks = <&apb1_gates 17>; | |
| 1003 | status = "disabled"; | |
| 1004 | }; | |
| 1005 | ||
| 1006 | uart2: serial@01c28800 { | |
| 1007 | compatible = "snps,dw-apb-uart"; | |
| 1008 | reg = <0x01c28800 0x400>; | |
| 1009 | interrupts = <3>; | |
| 1010 | reg-shift = <2>; | |
| 1011 | reg-io-width = <4>; | |
| 1012 | clocks = <&apb1_gates 18>; | |
| 1013 | status = "disabled"; | |
| 1014 | }; | |
| 1015 | ||
| 95f4b4f4 MR |
1016 | uart3: serial@01c28c00 { |
| 1017 | compatible = "snps,dw-apb-uart"; | |
| 1018 | reg = <0x01c28c00 0x400>; | |
| 1019 | interrupts = <4>; | |
| 1020 | reg-shift = <2>; | |
| 1021 | reg-io-width = <4>; | |
| 1022 | clocks = <&apb1_gates 19>; | |
| 1023 | status = "disabled"; | |
| 1024 | }; | |
| 1025 | ||
| e8f4351a MJ |
1026 | i2c0: i2c@01c2ac00 { |
| 1027 | compatible = "allwinner,sun4i-a10-i2c"; | |
| 1028 | reg = <0x01c2ac00 0x400>; | |
| 1029 | interrupts = <7>; | |
| 1030 | clocks = <&apb1_gates 0>; | |
| 1031 | status = "disabled"; | |
| 1032 | #address-cells = <1>; | |
| 1033 | #size-cells = <0>; | |
| 1034 | }; | |
| 1035 | ||
| 1036 | i2c1: i2c@01c2b000 { | |
| 1037 | compatible = "allwinner,sun4i-a10-i2c"; | |
| 1038 | reg = <0x01c2b000 0x400>; | |
| 1039 | interrupts = <8>; | |
| 1040 | clocks = <&apb1_gates 1>; | |
| 1041 | status = "disabled"; | |
| 1042 | #address-cells = <1>; | |
| 1043 | #size-cells = <0>; | |
| 1044 | }; | |
| 1045 | ||
| 1046 | i2c2: i2c@01c2b400 { | |
| 1047 | compatible = "allwinner,sun4i-a10-i2c"; | |
| 1048 | reg = <0x01c2b400 0x400>; | |
| 1049 | interrupts = <9>; | |
| 1050 | clocks = <&apb1_gates 2>; | |
| 1051 | status = "disabled"; | |
| 1052 | #address-cells = <1>; | |
| 1053 | #size-cells = <0>; | |
| 1054 | }; | |
| 1055 | ||
| 1056 | timer@01c60000 { | |
| 1057 | compatible = "allwinner,sun5i-a13-hstimer"; | |
| 1058 | reg = <0x01c60000 0x1000>; | |
| 1059 | interrupts = <82>, <83>; | |
| 1060 | clocks = <&ahb_gates 28>; | |
| 1061 | }; | |
| 1062 | ||
| 1063 | fe0: display-frontend@01e00000 { | |
| 1064 | compatible = "allwinner,sun5i-a13-display-frontend"; | |
| 1065 | reg = <0x01e00000 0x20000>; | |
| 1066 | interrupts = <47>; | |
| 1067 | clocks = <&ahb_gates 46>, <&de_fe_clk>, | |
| 1068 | <&dram_gates 25>; | |
| 1069 | clock-names = "ahb", "mod", | |
| 1070 | "ram"; | |
| 1071 | resets = <&de_fe_clk>; | |
| 1072 | status = "disabled"; | |
| 1073 | ||
| 1074 | ports { | |
| 1075 | #address-cells = <1>; | |
| 1076 | #size-cells = <0>; | |
| 1077 | ||
| 1078 | fe0_out: port@1 { | |
| 1079 | #address-cells = <1>; | |
| 1080 | #size-cells = <0>; | |
| 1081 | reg = <1>; | |
| 1082 | ||
| 1083 | fe0_out_be0: endpoint@0 { | |
| 1084 | reg = <0>; | |
| 1085 | remote-endpoint = <&be0_in_fe0>; | |
| 1086 | }; | |
| 1087 | }; | |
| 1088 | }; | |
| 1089 | }; | |
| 1090 | ||
| 1091 | be0: display-backend@01e60000 { | |
| 1092 | compatible = "allwinner,sun5i-a13-display-backend"; | |
| 1093 | reg = <0x01e60000 0x10000>; | |
| 1094 | clocks = <&ahb_gates 44>, <&de_be_clk>, | |
| 1095 | <&dram_gates 26>; | |
| 1096 | clock-names = "ahb", "mod", | |
| 1097 | "ram"; | |
| 1098 | resets = <&de_be_clk>; | |
| 1099 | status = "disabled"; | |
| 1100 | ||
| 1101 | assigned-clocks = <&de_be_clk>; | |
| 1102 | assigned-clock-rates = <300000000>; | |
| 1103 | ||
| 1104 | ports { | |
| 1105 | #address-cells = <1>; | |
| 1106 | #size-cells = <0>; | |
| 1107 | ||
| 1108 | be0_in: port@0 { | |
| 1109 | #address-cells = <1>; | |
| 1110 | #size-cells = <0>; | |
| 1111 | reg = <0>; | |
| 1112 | ||
| 1113 | be0_in_fe0: endpoint@0 { | |
| 1114 | reg = <0>; | |
| 1115 | remote-endpoint = <&fe0_out_be0>; | |
| 1116 | }; | |
| 1117 | }; | |
| 1118 | ||
| 1119 | be0_out: port@1 { | |
| 1120 | #address-cells = <1>; | |
| 1121 | #size-cells = <0>; | |
| 1122 | reg = <1>; | |
| 1123 | ||
| 1124 | be0_out_tcon0: endpoint@0 { | |
| 1125 | reg = <0>; | |
| 1126 | remote-endpoint = <&tcon0_in_be0>; | |
| 1127 | }; | |
| 1128 | }; | |
| 1129 | }; | |
| 1130 | }; | |
| 1131 | }; | |
| 1132 | }; |