[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / sun5i.dtsi

/*
 * Copyright 2012-2015 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton.dtsi"

#include <dt-bindings/clock/sun5i-ccu.h>
#include <dt-bindings/dma/sun4i-a10.h>
#include <dt-bindings/reset/sun5i-ccu.h>

/ {
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0x0>;
			clocks = <&ccu CLK_CPU>;
		};
	};

	chosen {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		framebuffer@0 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0";
			clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
				 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
			status = "disabled";
		};

		framebuffer@1 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0-tve0";
			clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
				 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
				 <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
			status = "disabled";
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc24M: clk@1c20050 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		osc32k: clk@0 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};
	};

	soc@1c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		sram-controller@1c00000 {
			compatible = "allwinner,sun4i-a10-sram-controller";
			reg = <0x01c00000 0x30>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			sram_a: sram@0 {
				compatible = "mmio-sram";
				reg = <0x00000000 0xc000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00000000 0xc000>;
			};

			emac_sram: sram-section@8000 {
				compatible = "allwinner,sun4i-a10-sram-a3-a4";
				reg = <0x8000 0x4000>;
				status = "disabled";
			};

			sram_d: sram@10000 {
				compatible = "mmio-sram";
				reg = <0x00010000 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00010000 0x1000>;

				otg_sram: sram-section@0 {
					compatible = "allwinner,sun4i-a10-sram-d";
					reg = <0x0000 0x1000>;
					status = "disabled";
				};
			};
		};

		dma: dma-controller@1c02000 {
			compatible = "allwinner,sun4i-a10-dma";
			reg = <0x01c02000 0x1000>;
			interrupts = <27>;
			clocks = <&ccu CLK_AHB_DMA>;
			#dma-cells = <2>;
		};

		nfc: nand@1c03000 {
			compatible = "allwinner,sun4i-a10-nand";
			reg = <0x01c03000 0x1000>;
			interrupts = <37>;
			clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 3>;
			dma-names = "rxtx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi0: spi@1c05000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c05000 0x1000>;
			interrupts = <10>;
			clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 27>,
			       <&dma SUN4I_DMA_DEDICATED 26>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@1c06000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c06000 0x1000>;
			interrupts = <11>;
			clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 9>,
			       <&dma SUN4I_DMA_DEDICATED 8>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		tve0: tv-encoder@1c0a000 {
			compatible = "allwinner,sun4i-a10-tv-encoder";
			reg = <0x01c0a000 0x1000>;
			clocks = <&ccu CLK_AHB_TVE>;
			resets = <&ccu RST_TVE>;
			status = "disabled";

			port {
				#address-cells = <1>;
				#size-cells = <0>;

				tve0_in_tcon0: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&tcon0_out_tve0>;
				};
			};
		};

		emac: ethernet@1c0b000 {
			compatible = "allwinner,sun4i-a10-emac";
			reg = <0x01c0b000 0x1000>;
			interrupts = <55>;
			clocks = <&ccu CLK_AHB_EMAC>;
			allwinner,sram = <&emac_sram 1>;
			status = "disabled";
		};

		mdio: mdio@1c0b080 {
			compatible = "allwinner,sun4i-a10-mdio";
			reg = <0x01c0b080 0x14>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		tcon0: lcd-controller@1c0c000 {
			compatible = "allwinner,sun5i-a13-tcon";
			reg = <0x01c0c000 0x1000>;
			interrupts = <44>;
			resets = <&ccu RST_LCD>;
			reset-names = "lcd";
			clocks = <&ccu CLK_AHB_LCD>,
				 <&ccu CLK_TCON_CH0>,
				 <&ccu CLK_TCON_CH1>;
			clock-names = "ahb",
				      "tcon-ch0",
				      "tcon-ch1";
			clock-output-names = "tcon-pixel-clock";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				tcon0_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					tcon0_in_be0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&be0_out_tcon0>;
					};
				};

				tcon0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					tcon0_out_tve0: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&tve0_in_tcon0>;
						allwinner,tcon-channel = <1>;
					};
				};
			};
		};

		mmc0: mmc@1c0f000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c0f000 0x1000>;
			clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
			clock-names = "ahb", "mmc";
			interrupts = <32>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc1: mmc@1c10000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c10000 0x1000>;
			clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
			clock-names = "ahb", "mmc";
			interrupts = <33>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc2: mmc@1c11000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c11000 0x1000>;
			clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
			clock-names = "ahb", "mmc";
			interrupts = <34>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		usb_otg: usb@1c13000 {
			compatible = "allwinner,sun4i-a10-musb";
			reg = <0x01c13000 0x0400>;
			clocks = <&ccu CLK_AHB_OTG>;
			interrupts = <38>;
			interrupt-names = "mc";
			phys = <&usbphy 0>;
			phy-names = "usb";
			extcon = <&usbphy 0>;
			allwinner,sram = <&otg_sram 1>;
			status = "disabled";
		};

		usbphy: phy@1c13400 {
			#phy-cells = <1>;
			compatible = "allwinner,sun5i-a13-usb-phy";
			reg = <0x01c13400 0x10 0x01c14800 0x4>;
			reg-names = "phy_ctrl", "pmu1";
			clocks = <&ccu CLK_USB_PHY0>;
			clock-names = "usb_phy";
			resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
			reset-names = "usb0_reset", "usb1_reset";
			status = "disabled";
		};

		ehci0: usb@1c14000 {
			compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
			reg = <0x01c14000 0x100>;
			interrupts = <39>;
			clocks = <&ccu CLK_AHB_EHCI>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci0: usb@1c14400 {
			compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
			reg = <0x01c14400 0x100>;
			interrupts = <40>;
			clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		crypto: crypto-engine@1c15000 {
			compatible = "allwinner,sun5i-a13-crypto",
				     "allwinner,sun4i-a10-crypto";
			reg = <0x01c15000 0x1000>;
			interrupts = <54>;
			clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
			clock-names = "ahb", "mod";
		};

		spi2: spi@1c17000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c17000 0x1000>;
			interrupts = <12>;
			clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 29>,
			       <&dma SUN4I_DMA_DEDICATED 28>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		ccu: clock@1c20000 {
			reg = <0x01c20000 0x400>;
			clocks = <&osc24M>, <&osc32k>;
			clock-names = "hosc", "losc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		intc: interrupt-controller@1c20400 {
			compatible = "allwinner,sun4i-a10-ic";
			reg = <0x01c20400 0x400>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		pio: pinctrl@1c20800 {
			reg = <0x01c20800 0x400>;
			interrupts = <28>;
			clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
			clock-names = "apb", "hosc", "losc";
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <3>;
			#gpio-cells = <3>;

			emac_pins_a: emac0@0 {
				pins = "PD6", "PD7", "PD10",
				       "PD11", "PD12", "PD13", "PD14",
				       "PD15", "PD18", "PD19", "PD20",
				       "PD21", "PD22", "PD23", "PD24",
				       "PD25", "PD26", "PD27";
				function = "emac";
			};

			i2c0_pins_a: i2c0@0 {
				pins = "PB0", "PB1";
				function = "i2c0";
			};

			i2c1_pins_a: i2c1@0 {
				pins = "PB15", "PB16";
				function = "i2c1";
			};

			i2c2_pins_a: i2c2@0 {
				pins = "PB17", "PB18";
				function = "i2c2";
			};

			ir0_rx_pins_a: ir0@0 {
				pins = "PB4";
				function = "ir0";
			};

			lcd_rgb565_pins: lcd_rgb565@0 {
				pins = "PD3", "PD4", "PD5", "PD6", "PD7",
						 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
						 "PD19", "PD20", "PD21", "PD22", "PD23",
						 "PD24", "PD25", "PD26", "PD27";
				function = "lcd0";
			};

			lcd_rgb666_pins: lcd_rgb666@0 {
				pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
				       "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
				       "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
				       "PD24", "PD25", "PD26", "PD27";
				function = "lcd0";
			};

			mmc0_pins_a: mmc0@0 {
				pins = "PF0", "PF1", "PF2", "PF3",
				       "PF4", "PF5";
				function = "mmc0";
				drive-strength = <30>;
				bias-pull-up;
			};

			mmc2_pins_a: mmc2@0 {
				pins = "PC6", "PC7", "PC8", "PC9",
				       "PC10", "PC11", "PC12", "PC13",
				       "PC14", "PC15";
				function = "mmc2";
				drive-strength = <30>;
				bias-pull-up;
			};

			mmc2_4bit_pins_a: mmc2-4bit@0 {
				pins = "PC6", "PC7", "PC8", "PC9",
				       "PC10", "PC11";
				function = "mmc2";
				drive-strength = <30>;
				bias-pull-up;
			};

			nand_pins_a: nand-base0@0 {
				pins = "PC0", "PC1", "PC2",
				       "PC5", "PC8", "PC9", "PC10",
				       "PC11", "PC12", "PC13", "PC14",
				       "PC15";
				function = "nand0";
			};

			nand_cs0_pins_a: nand-cs@0 {
				pins = "PC4";
				function = "nand0";
			};

			nand_rb0_pins_a: nand-rb@0 {
				pins = "PC6";
				function = "nand0";
			};

			spi2_pins_a: spi2@0 {
				pins = "PE1", "PE2", "PE3";
				function = "spi2";
			};

			spi2_cs0_pins_a: spi2-cs0@0 {
				pins = "PE0";
				function = "spi2";
			};

			uart1_pins_a: uart1@0 {
				pins = "PE10", "PE11";
				function = "uart1";
			};

			uart1_pins_b: uart1@1 {
				pins = "PG3", "PG4";
				function = "uart1";
			};

			uart2_pins_a: uart2@0 {
				pins = "PD2", "PD3";
				function = "uart2";
			};

			uart2_cts_rts_pins_a: uart2-cts-rts@0 {
				pins = "PD4", "PD5";
				function = "uart2";
			};

			uart3_pins_a: uart3@0 {
				pins = "PG9", "PG10";
				function = "uart3";
			};

			uart3_cts_rts_pins_a: uart3-cts-rts@0 {
				pins = "PG11", "PG12";
				function = "uart3";
			};

			pwm0_pins: pwm0 {
				pins = "PB2";
				function = "pwm";
			};
		};

		timer@1c20c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x01c20c00 0x90>;
			interrupts = <22>;
			clocks = <&ccu CLK_HOSC>;
		};

		wdt: watchdog@1c20c90 {
			compatible = "allwinner,sun4i-a10-wdt";
			reg = <0x01c20c90 0x10>;
		};

		ir0: ir@1c21800 {
			compatible = "allwinner,sun4i-a10-ir";
			clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
			clock-names = "apb", "ir";
			interrupts = <5>;
			reg = <0x01c21800 0x40>;
			status = "disabled";
		};

		lradc: lradc@1c22800 {
			compatible = "allwinner,sun4i-a10-lradc-keys";
			reg = <0x01c22800 0x100>;
			interrupts = <31>;
			status = "disabled";
		};

		codec: codec@1c22c00 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sun4i-a10-codec";
			reg = <0x01c22c00 0x40>;
			interrupts = <30>;
			clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
			clock-names = "apb", "codec";
			dmas = <&dma SUN4I_DMA_NORMAL 19>,
			       <&dma SUN4I_DMA_NORMAL 19>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		sid: eeprom@1c23800 {
			compatible = "allwinner,sun4i-a10-sid";
			reg = <0x01c23800 0x10>;
		};

		rtp: rtp@1c25000 {
			compatible = "allwinner,sun5i-a13-ts";
			reg = <0x01c25000 0x100>;
			interrupts = <29>;
			#thermal-sensor-cells = <0>;
		};

		uart0: serial@1c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_APB1_UART0>;
			status = "disabled";
		};

		uart1: serial@1c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <2>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_APB1_UART1>;
			status = "disabled";
		};

		uart2: serial@1c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <3>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_APB1_UART2>;
			status = "disabled";
		};

		uart3: serial@1c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_APB1_UART3>;
			status = "disabled";
		};

		i2c0: i2c@1c2ac00 {
			compatible = "allwinner,sun4i-a10-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <7>;
			clocks = <&ccu CLK_APB1_I2C0>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@1c2b000 {
			compatible = "allwinner,sun4i-a10-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <8>;
			clocks = <&ccu CLK_APB1_I2C1>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@1c2b400 {
			compatible = "allwinner,sun4i-a10-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <9>;
			clocks = <&ccu CLK_APB1_I2C2>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		timer@1c60000 {
			compatible = "allwinner,sun5i-a13-hstimer";
			reg = <0x01c60000 0x1000>;
			interrupts = <82>, <83>;
			clocks = <&ccu CLK_AHB_HSTIMER>;
		};

		fe0: display-frontend@1e00000 {
			compatible = "allwinner,sun5i-a13-display-frontend";
			reg = <0x01e00000 0x20000>;
			interrupts = <47>;
			clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
				 <&ccu CLK_DRAM_DE_FE>;
			clock-names = "ahb", "mod",
				      "ram";
			resets = <&ccu RST_DE_FE>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				fe0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					fe0_out_be0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&be0_in_fe0>;
					};
				};
			};
		};

		be0: display-backend@1e60000 {
			compatible = "allwinner,sun5i-a13-display-backend";
			reg = <0x01e60000 0x10000>;
			interrupts = <47>;
			clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
				 <&ccu CLK_DRAM_DE_BE>;
			clock-names = "ahb", "mod",
				      "ram";
			resets = <&ccu RST_DE_BE>;
			status = "disabled";

			assigned-clocks = <&ccu CLK_DE_BE>;
			assigned-clock-rates = <300000000>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				be0_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					be0_in_fe0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&fe0_out_be0>;
					};
				};

				be0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					be0_out_tcon0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&tcon0_in_be0>;
					};
				};
			};
		};
	};
};
Commit	Line	Data
fbfa7367 MR	1	/*
	2	* Copyright 2012-2015 Maxime Ripard
	3	*
	4	* Maxime Ripard <maxime.ripard@free-electrons.com>
	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
	11	* a) This library is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This library is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
fbfa7367 MR	21	* Or, alternatively,
	22	*
	23	* b) Permission is hereby granted, free of charge, to any person
	24	* obtaining a copy of this software and associated documentation
	25	* files (the "Software"), to deal in the Software without
	26	* restriction, including without limitation the rights to use,
	27	* copy, modify, merge, publish, distribute, sublicense, and/or
	28	* sell copies of the Software, and to permit persons to whom the
	29	* Software is furnished to do so, subject to the following
	30	* conditions:
	31	*
	32	* The above copyright notice and this permission notice shall be
	33	* included in all copies or substantial portions of the Software.
	34	*
	35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	37	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	38	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	39	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	41	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	42	* OTHER DEALINGS IN THE SOFTWARE.
	43	*/
	44
	45	#include "skeleton.dtsi"
	46
98a59a0f	47	#include <dt-bindings/clock/sun5i-ccu.h>
fbfa7367	48	#include <dt-bindings/dma/sun4i-a10.h>
98a59a0f	49	#include <dt-bindings/reset/sun5i-ccu.h>
fbfa7367 MR	50
	51	/ {
	52	interrupt-parent = <&intc>;
	53
	54	cpus {
	55	#address-cells = <1>;
	56	#size-cells = <0>;
	57
	58	cpu0: cpu@0 {
	59	device_type = "cpu";
	60	compatible = "arm,cortex-a8";
	61	reg = <0x0>;
98a59a0f	62	clocks = <&ccu CLK_CPU>;
fbfa7367 MR	63	};
	64	};
	65
85870196 MR	66	chosen {
	67	#address-cells = <1>;
	68	#size-cells = <1>;
	69	ranges;
	70
	71	framebuffer@0 {
	72	compatible = "allwinner,simple-framebuffer",
	73	"simple-framebuffer";
	74	allwinner,pipeline = "de_be0-lcd0";
	75	clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
	76	<&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
	77	status = "disabled";
	78	};
78f6d982 MR	79
	80	framebuffer@1 {
	81	compatible = "allwinner,simple-framebuffer",
	82	"simple-framebuffer";
	83	allwinner,pipeline = "de_be0-lcd0-tve0";
	84	clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
	85	<&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
	86	<&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
	87	status = "disabled";
	88	};
85870196 MR	89	};
85870196 MR	90
fbfa7367 MR	91	clocks {
	92	#address-cells = <1>;
	93	#size-cells = <1>;
	94	ranges;
	95
8dccafaa	96	osc24M: clk@1c20050 {
fbfa7367	97	#clock-cells = <0>;
98a59a0f	98	compatible = "fixed-clock";
fbfa7367 MR	99	clock-frequency = <24000000>;
	100	clock-output-names = "osc24M";
	101	};
	102
	103	osc32k: clk@0 {
	104	#clock-cells = <0>;
	105	compatible = "fixed-clock";
	106	clock-frequency = <32768>;
	107	clock-output-names = "osc32k";
	108	};
fbfa7367 MR	109	};
fbfa7367 MR	110
8dccafaa	111	soc@1c00000 {
fbfa7367 MR	112	compatible = "simple-bus";
	113	#address-cells = <1>;
	114	#size-cells = <1>;
	115	ranges;
	116
8dccafaa	117	sram-controller@1c00000 {
00f69ba9 MR	118	compatible = "allwinner,sun4i-a10-sram-controller";
	119	reg = <0x01c00000 0x30>;
	120	#address-cells = <1>;
	121	#size-cells = <1>;
	122	ranges;
	123
8dccafaa	124	sram_a: sram@0 {
00f69ba9 MR	125	compatible = "mmio-sram";
	126	reg = <0x00000000 0xc000>;
	127	#address-cells = <1>;
	128	#size-cells = <1>;
	129	ranges = <0 0x00000000 0xc000>;
	130	};
	131
78f6d982 MR	132	emac_sram: sram-section@8000 {
	133	compatible = "allwinner,sun4i-a10-sram-a3-a4";
	134	reg = <0x8000 0x4000>;
	135	status = "disabled";
	136	};
	137
8dccafaa	138	sram_d: sram@10000 {
00f69ba9 MR	139	compatible = "mmio-sram";
	140	reg = <0x00010000 0x1000>;
	141	#address-cells = <1>;
	142	#size-cells = <1>;
	143	ranges = <0 0x00010000 0x1000>;
	144
8dccafaa	145	otg_sram: sram-section@0 {
00f69ba9 MR	146	compatible = "allwinner,sun4i-a10-sram-d";
	147	reg = <0x0000 0x1000>;
	148	status = "disabled";
	149	};
	150	};
	151	};
	152
8dccafaa	153	dma: dma-controller@1c02000 {
fbfa7367 MR	154	compatible = "allwinner,sun4i-a10-dma";
	155	reg = <0x01c02000 0x1000>;
	156	interrupts = <27>;
98a59a0f	157	clocks = <&ccu CLK_AHB_DMA>;
fbfa7367 MR	158	#dma-cells = <2>;
	159	};
	160
8dccafaa	161	nfc: nand@1c03000 {
1f4ce3b6 MR	162	compatible = "allwinner,sun4i-a10-nand";
	163	reg = <0x01c03000 0x1000>;
	164	interrupts = <37>;
	165	clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
	166	clock-names = "ahb", "mod";
	167	dmas = <&dma SUN4I_DMA_DEDICATED 3>;
	168	dma-names = "rxtx";
	169	status = "disabled";
	170	#address-cells = <1>;
	171	#size-cells = <0>;
	172	};
	173
8dccafaa	174	spi0: spi@1c05000 {
fbfa7367 MR	175	compatible = "allwinner,sun4i-a10-spi";
	176	reg = <0x01c05000 0x1000>;
	177	interrupts = <10>;
98a59a0f	178	clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
fbfa7367 MR	179	clock-names = "ahb", "mod";
	180	dmas = <&dma SUN4I_DMA_DEDICATED 27>,
	181	<&dma SUN4I_DMA_DEDICATED 26>;
	182	dma-names = "rx", "tx";
	183	status = "disabled";
	184	#address-cells = <1>;
	185	#size-cells = <0>;
	186	};
	187
8dccafaa	188	spi1: spi@1c06000 {
fbfa7367 MR	189	compatible = "allwinner,sun4i-a10-spi";
	190	reg = <0x01c06000 0x1000>;
	191	interrupts = <11>;
98a59a0f	192	clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
fbfa7367 MR	193	clock-names = "ahb", "mod";
	194	dmas = <&dma SUN4I_DMA_DEDICATED 9>,
	195	<&dma SUN4I_DMA_DEDICATED 8>;
	196	dma-names = "rx", "tx";
	197	status = "disabled";
	198	#address-cells = <1>;
	199	#size-cells = <0>;
	200	};
	201
8dccafaa	202	tve0: tv-encoder@1c0a000 {
bea13693 MR	203	compatible = "allwinner,sun4i-a10-tv-encoder";
	204	reg = <0x01c0a000 0x1000>;
	205	clocks = <&ccu CLK_AHB_TVE>;
	206	resets = <&ccu RST_TVE>;
	207	status = "disabled";
	208
	209	port {
	210	#address-cells = <1>;
	211	#size-cells = <0>;
	212
	213	tve0_in_tcon0: endpoint@0 {
	214	reg = <0>;
	215	remote-endpoint = <&tcon0_out_tve0>;
	216	};
	217	};
	218	};
	219
8dccafaa	220	emac: ethernet@1c0b000 {
78f6d982 MR	221	compatible = "allwinner,sun4i-a10-emac";
	222	reg = <0x01c0b000 0x1000>;
	223	interrupts = <55>;
	224	clocks = <&ccu CLK_AHB_EMAC>;
	225	allwinner,sram = <&emac_sram 1>;
	226	status = "disabled";
	227	};
	228
8dccafaa	229	mdio: mdio@1c0b080 {
78f6d982 MR	230	compatible = "allwinner,sun4i-a10-mdio";
	231	reg = <0x01c0b080 0x14>;
	232	status = "disabled";
	233	#address-cells = <1>;
	234	#size-cells = <0>;
	235	};
	236
8dccafaa	237	tcon0: lcd-controller@1c0c000 {
85870196 MR	238	compatible = "allwinner,sun5i-a13-tcon";
	239	reg = <0x01c0c000 0x1000>;
	240	interrupts = <44>;
	241	resets = <&ccu RST_LCD>;
	242	reset-names = "lcd";
	243	clocks = <&ccu CLK_AHB_LCD>,
	244	<&ccu CLK_TCON_CH0>,
	245	<&ccu CLK_TCON_CH1>;
	246	clock-names = "ahb",
	247	"tcon-ch0",
	248	"tcon-ch1";
	249	clock-output-names = "tcon-pixel-clock";
	250	status = "disabled";
	251
	252	ports {
	253	#address-cells = <1>;
	254	#size-cells = <0>;
	255
	256	tcon0_in: port@0 {
	257	#address-cells = <1>;
	258	#size-cells = <0>;
	259	reg = <0>;
	260
	261	tcon0_in_be0: endpoint@0 {
	262	reg = <0>;
	263	remote-endpoint = <&be0_out_tcon0>;
	264	};
	265	};
	266
	267	tcon0_out: port@1 {
	268	#address-cells = <1>;
	269	#size-cells = <0>;
	270	reg = <1>;
bea13693 MR	271
	272	tcon0_out_tve0: endpoint@1 {
	273	reg = <1>;
	274	remote-endpoint = <&tve0_in_tcon0>;
0d2c6f02	275	allwinner,tcon-channel = <1>;
bea13693	276	};
85870196 MR	277	};
	278	};
	279	};
	280
8dccafaa	281	mmc0: mmc@1c0f000 {
fbfa7367 MR	282	compatible = "allwinner,sun5i-a13-mmc";
fbfa7367 MR	283	reg = <0x01c0f000 0x1000>;
98a59a0f MR	284	clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
98a59a0f MR	285	clock-names = "ahb", "mmc";
fbfa7367 MR	286	interrupts = <32>;
fbfa7367 MR	287	status = "disabled";
4c1bb9c3 HG	288	#address-cells = <1>;
4c1bb9c3 HG	289	#size-cells = <0>;
fbfa7367 MR	290	};
fbfa7367 MR	291
8dccafaa	292	mmc1: mmc@1c10000 {
fbfa7367 MR	293	compatible = "allwinner,sun5i-a13-mmc";
fbfa7367 MR	294	reg = <0x01c10000 0x1000>;
98a59a0f MR	295	clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
98a59a0f MR	296	clock-names = "ahb", "mmc";
fbfa7367 MR	297	interrupts = <33>;
fbfa7367 MR	298	status = "disabled";
4c1bb9c3 HG	299	#address-cells = <1>;
4c1bb9c3 HG	300	#size-cells = <0>;
fbfa7367 MR	301	};
fbfa7367 MR	302
8dccafaa	303	mmc2: mmc@1c11000 {
fbfa7367 MR	304	compatible = "allwinner,sun5i-a13-mmc";
fbfa7367 MR	305	reg = <0x01c11000 0x1000>;
98a59a0f MR	306	clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
98a59a0f MR	307	clock-names = "ahb", "mmc";
fbfa7367 MR	308	interrupts = <34>;
fbfa7367 MR	309	status = "disabled";
4c1bb9c3 HG	310	#address-cells = <1>;
4c1bb9c3 HG	311	#size-cells = <0>;
fbfa7367 MR	312	};
fbfa7367 MR	313
8dccafaa	314	usb_otg: usb@1c13000 {
482f178c HG	315	compatible = "allwinner,sun4i-a10-musb";
482f178c HG	316	reg = <0x01c13000 0x0400>;
98a59a0f	317	clocks = <&ccu CLK_AHB_OTG>;
482f178c HG	318	interrupts = <38>;
	319	interrupt-names = "mc";
	320	phys = <&usbphy 0>;
	321	phy-names = "usb";
	322	extcon = <&usbphy 0>;
	323	allwinner,sram = <&otg_sram 1>;
	324	status = "disabled";
	325	};
	326
8dccafaa	327	usbphy: phy@1c13400 {
fbfa7367 MR	328	#phy-cells = <1>;
	329	compatible = "allwinner,sun5i-a13-usb-phy";
	330	reg = <0x01c13400 0x10 0x01c14800 0x4>;
	331	reg-names = "phy_ctrl", "pmu1";
98a59a0f	332	clocks = <&ccu CLK_USB_PHY0>;
fbfa7367	333	clock-names = "usb_phy";
98a59a0f	334	resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
fbfa7367 MR	335	reset-names = "usb0_reset", "usb1_reset";
	336	status = "disabled";
	337	};
	338
8dccafaa	339	ehci0: usb@1c14000 {
3727ed3b	340	compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
fbfa7367 MR	341	reg = <0x01c14000 0x100>;
fbfa7367 MR	342	interrupts = <39>;
98a59a0f	343	clocks = <&ccu CLK_AHB_EHCI>;
fbfa7367 MR	344	phys = <&usbphy 1>;
	345	phy-names = "usb";
	346	status = "disabled";
	347	};
	348
8dccafaa	349	ohci0: usb@1c14400 {
3727ed3b	350	compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
fbfa7367 MR	351	reg = <0x01c14400 0x100>;
fbfa7367 MR	352	interrupts = <40>;
98a59a0f	353	clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
fbfa7367 MR	354	phys = <&usbphy 1>;
	355	phy-names = "usb";
	356	status = "disabled";
	357	};
	358
8dccafaa	359	crypto: crypto-engine@1c15000 {
e1679f09 AT	360	compatible = "allwinner,sun5i-a13-crypto",
	361	"allwinner,sun4i-a10-crypto";
	362	reg = <0x01c15000 0x1000>;
	363	interrupts = <54>;
	364	clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
	365	clock-names = "ahb", "mod";
	366	};
	367
8dccafaa	368	spi2: spi@1c17000 {
fbfa7367 MR	369	compatible = "allwinner,sun4i-a10-spi";
	370	reg = <0x01c17000 0x1000>;
	371	interrupts = <12>;
98a59a0f	372	clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
fbfa7367 MR	373	clock-names = "ahb", "mod";
	374	dmas = <&dma SUN4I_DMA_DEDICATED 29>,
	375	<&dma SUN4I_DMA_DEDICATED 28>;
	376	dma-names = "rx", "tx";
	377	status = "disabled";
	378	#address-cells = <1>;
	379	#size-cells = <0>;
	380	};
	381
8dccafaa	382	ccu: clock@1c20000 {
98a59a0f MR	383	reg = <0x01c20000 0x400>;
	384	clocks = <&osc24M>, <&osc32k>;
	385	clock-names = "hosc", "losc";
	386	#clock-cells = <1>;
	387	#reset-cells = <1>;
	388	};
	389
8dccafaa	390	intc: interrupt-controller@1c20400 {
fbfa7367 MR	391	compatible = "allwinner,sun4i-a10-ic";
	392	reg = <0x01c20400 0x400>;
	393	interrupt-controller;
	394	#interrupt-cells = <1>;
	395	};
	396
8dccafaa	397	pio: pinctrl@1c20800 {
fbfa7367 MR	398	reg = <0x01c20800 0x400>;
fbfa7367 MR	399	interrupts = <28>;
98a59a0f	400	clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
be7bc6b9	401	clock-names = "apb", "hosc", "losc";
fbfa7367 MR	402	gpio-controller;
fbfa7367 MR	403	interrupt-controller;
b03e0816	404	#interrupt-cells = <3>;
fbfa7367	405	#gpio-cells = <3>;
51fbba42	406
78f6d982 MR	407	emac_pins_a: emac0@0 {
	408	pins = "PD6", "PD7", "PD10",
	409	"PD11", "PD12", "PD13", "PD14",
	410	"PD15", "PD18", "PD19", "PD20",
	411	"PD21", "PD22", "PD23", "PD24",
	412	"PD25", "PD26", "PD27";
	413	function = "emac";
	414	};
	415
51fbba42	416	i2c0_pins_a: i2c0@0 {
1edcd36f MR	417	pins = "PB0", "PB1";
1edcd36f MR	418	function = "i2c0";
51fbba42 MR	419	};
	420
	421	i2c1_pins_a: i2c1@0 {
1edcd36f MR	422	pins = "PB15", "PB16";
1edcd36f MR	423	function = "i2c1";
51fbba42 MR	424	};
	425
	426	i2c2_pins_a: i2c2@0 {
1edcd36f MR	427	pins = "PB17", "PB18";
1edcd36f MR	428	function = "i2c2";
51fbba42 MR	429	};
51fbba42 MR	430
1f4ce3b6 MR	431	ir0_rx_pins_a: ir0@0 {
	432	pins = "PB4";
	433	function = "ir0";
	434	};
	435
60a47e43	436	lcd_rgb565_pins: lcd_rgb565@0 {
1edcd36f	437	pins = "PD3", "PD4", "PD5", "PD6", "PD7",
60a47e43 MR	438	"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
	439	"PD19", "PD20", "PD21", "PD22", "PD23",
	440	"PD24", "PD25", "PD26", "PD27";
1edcd36f	441	function = "lcd0";
60a47e43 MR	442	};
60a47e43 MR	443
85870196 MR	444	lcd_rgb666_pins: lcd_rgb666@0 {
	445	pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
	446	"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
	447	"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
	448	"PD24", "PD25", "PD26", "PD27";
	449	function = "lcd0";
	450	};
	451
51fbba42	452	mmc0_pins_a: mmc0@0 {
1edcd36f MR	453	pins = "PF0", "PF1", "PF2", "PF3",
	454	"PF4", "PF5";
	455	function = "mmc0";
	456	drive-strength = <30>;
80ee72e7	457	bias-pull-up;
51fbba42	458	};
e1fe9f8c HG	459
e1fe9f8c HG	460	mmc2_pins_a: mmc2@0 {
1edcd36f MR	461	pins = "PC6", "PC7", "PC8", "PC9",
	462	"PC10", "PC11", "PC12", "PC13",
	463	"PC14", "PC15";
	464	function = "mmc2";
	465	drive-strength = <30>;
	466	bias-pull-up;
e1fe9f8c	467	};
6ef8c8bf	468
e6c5bfea IZ	469	mmc2_4bit_pins_a: mmc2-4bit@0 {
	470	pins = "PC6", "PC7", "PC8", "PC9",
	471	"PC10", "PC11";
	472	function = "mmc2";
	473	drive-strength = <30>;
	474	bias-pull-up;
	475	};
	476
1f4ce3b6 MR	477	nand_pins_a: nand-base0@0 {
	478	pins = "PC0", "PC1", "PC2",
	479	"PC5", "PC8", "PC9", "PC10",
	480	"PC11", "PC12", "PC13", "PC14",
	481	"PC15";
	482	function = "nand0";
	483	};
	484
	485	nand_cs0_pins_a: nand-cs@0 {
	486	pins = "PC4";
	487	function = "nand0";
	488	};
	489
	490	nand_rb0_pins_a: nand-rb@0 {
	491	pins = "PC6";
	492	function = "nand0";
	493	};
	494
9255fb6c	495	spi2_pins_a: spi2@0 {
1edcd36f MR	496	pins = "PE1", "PE2", "PE3";
1edcd36f MR	497	function = "spi2";
9255fb6c MR	498	};
	499
	500	spi2_cs0_pins_a: spi2-cs0@0 {
1edcd36f MR	501	pins = "PE0";
1edcd36f MR	502	function = "spi2";
9255fb6c MR	503	};
9255fb6c MR	504
85870196 MR	505	uart1_pins_a: uart1@0 {
	506	pins = "PE10", "PE11";
	507	function = "uart1";
	508	};
	509
	510	uart1_pins_b: uart1@1 {
	511	pins = "PG3", "PG4";
	512	function = "uart1";
	513	};
	514
bab86b94 MR	515	uart2_pins_a: uart2@0 {
	516	pins = "PD2", "PD3";
	517	function = "uart2";
	518	};
	519
	520	uart2_cts_rts_pins_a: uart2-cts-rts@0 {
	521	pins = "PD4", "PD5";
	522	function = "uart2";
	523	};
	524
6ef8c8bf	525	uart3_pins_a: uart3@0 {
1edcd36f MR	526	pins = "PG9", "PG10";
1edcd36f MR	527	function = "uart3";
eeea0fa3 MR	528	};
eeea0fa3 MR	529
e6f50b22	530	uart3_cts_rts_pins_a: uart3-cts-rts@0 {
1edcd36f MR	531	pins = "PG11", "PG12";
1edcd36f MR	532	function = "uart3";
6ef8c8bf	533	};
bb390193 HG	534
bb390193 HG	535	pwm0_pins: pwm0 {
1edcd36f MR	536	pins = "PB2";
1edcd36f MR	537	function = "pwm";
bb390193	538	};
fbfa7367 MR	539	};
fbfa7367 MR	540
8dccafaa	541	timer@1c20c00 {
fbfa7367 MR	542	compatible = "allwinner,sun4i-a10-timer";
	543	reg = <0x01c20c00 0x90>;
	544	interrupts = <22>;
98a59a0f	545	clocks = <&ccu CLK_HOSC>;
fbfa7367 MR	546	};
fbfa7367 MR	547
8dccafaa	548	wdt: watchdog@1c20c90 {
fbfa7367 MR	549	compatible = "allwinner,sun4i-a10-wdt";
	550	reg = <0x01c20c90 0x10>;
	551	};
	552
8dccafaa	553	ir0: ir@1c21800 {
1f4ce3b6 MR	554	compatible = "allwinner,sun4i-a10-ir";
	555	clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
	556	clock-names = "apb", "ir";
	557	interrupts = <5>;
	558	reg = <0x01c21800 0x40>;
	559	status = "disabled";
	560	};
	561
8dccafaa	562	lradc: lradc@1c22800 {
fbfa7367 MR	563	compatible = "allwinner,sun4i-a10-lradc-keys";
	564	reg = <0x01c22800 0x100>;
	565	interrupts = <31>;
	566	status = "disabled";
	567	};
	568
8dccafaa	569	codec: codec@1c22c00 {
44cdcfc2 MR	570	#sound-dai-cells = <0>;
	571	compatible = "allwinner,sun4i-a10-codec";
	572	reg = <0x01c22c00 0x40>;
	573	interrupts = <30>;
98a59a0f	574	clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
44cdcfc2 MR	575	clock-names = "apb", "codec";
	576	dmas = <&dma SUN4I_DMA_NORMAL 19>,
	577	<&dma SUN4I_DMA_NORMAL 19>;
	578	dma-names = "rx", "tx";
	579	status = "disabled";
	580	};
	581
8dccafaa	582	sid: eeprom@1c23800 {
fbfa7367 MR	583	compatible = "allwinner,sun4i-a10-sid";
	584	reg = <0x01c23800 0x10>;
	585	};
	586
8dccafaa	587	rtp: rtp@1c25000 {
8bf1b9b3	588	compatible = "allwinner,sun5i-a13-ts";
fbfa7367 MR	589	reg = <0x01c25000 0x100>;
	590	interrupts = <29>;
	591	#thermal-sensor-cells = <0>;
	592	};
	593
8dccafaa	594	uart0: serial@1c28000 {
78f6d982 MR	595	compatible = "snps,dw-apb-uart";
	596	reg = <0x01c28000 0x400>;
	597	interrupts = <1>;
	598	reg-shift = <2>;
	599	reg-io-width = <4>;
	600	clocks = <&ccu CLK_APB1_UART0>;
	601	status = "disabled";
	602	};
	603
8dccafaa	604	uart1: serial@1c28400 {
fbfa7367 MR	605	compatible = "snps,dw-apb-uart";
	606	reg = <0x01c28400 0x400>;
	607	interrupts = <2>;
	608	reg-shift = <2>;
	609	reg-io-width = <4>;
98a59a0f	610	clocks = <&ccu CLK_APB1_UART1>;
fbfa7367 MR	611	status = "disabled";
	612	};
	613
8dccafaa	614	uart2: serial@1c28800 {
78f6d982 MR	615	compatible = "snps,dw-apb-uart";
	616	reg = <0x01c28800 0x400>;
	617	interrupts = <3>;
	618	reg-shift = <2>;
	619	reg-io-width = <4>;
	620	clocks = <&ccu CLK_APB1_UART2>;
	621	status = "disabled";
	622	};
	623
8dccafaa	624	uart3: serial@1c28c00 {
fbfa7367 MR	625	compatible = "snps,dw-apb-uart";
	626	reg = <0x01c28c00 0x400>;
	627	interrupts = <4>;
	628	reg-shift = <2>;
	629	reg-io-width = <4>;
98a59a0f	630	clocks = <&ccu CLK_APB1_UART3>;
fbfa7367 MR	631	status = "disabled";
	632	};
	633
8dccafaa	634	i2c0: i2c@1c2ac00 {
fbfa7367 MR	635	compatible = "allwinner,sun4i-a10-i2c";
	636	reg = <0x01c2ac00 0x400>;
	637	interrupts = <7>;
98a59a0f	638	clocks = <&ccu CLK_APB1_I2C0>;
fbfa7367 MR	639	status = "disabled";
	640	#address-cells = <1>;
	641	#size-cells = <0>;
	642	};
	643
8dccafaa	644	i2c1: i2c@1c2b000 {
fbfa7367 MR	645	compatible = "allwinner,sun4i-a10-i2c";
	646	reg = <0x01c2b000 0x400>;
	647	interrupts = <8>;
98a59a0f	648	clocks = <&ccu CLK_APB1_I2C1>;
fbfa7367 MR	649	status = "disabled";
	650	#address-cells = <1>;
	651	#size-cells = <0>;
	652	};
	653
8dccafaa	654	i2c2: i2c@1c2b400 {
fbfa7367 MR	655	compatible = "allwinner,sun4i-a10-i2c";
	656	reg = <0x01c2b400 0x400>;
	657	interrupts = <9>;
98a59a0f	658	clocks = <&ccu CLK_APB1_I2C2>;
fbfa7367 MR	659	status = "disabled";
	660	#address-cells = <1>;
	661	#size-cells = <0>;
	662	};
	663
8dccafaa	664	timer@1c60000 {
fbfa7367 MR	665	compatible = "allwinner,sun5i-a13-hstimer";
	666	reg = <0x01c60000 0x1000>;
	667	interrupts = <82>, <83>;
98a59a0f	668	clocks = <&ccu CLK_AHB_HSTIMER>;
fbfa7367	669	};
85870196	670
8dccafaa	671	fe0: display-frontend@1e00000 {
85870196 MR	672	compatible = "allwinner,sun5i-a13-display-frontend";
	673	reg = <0x01e00000 0x20000>;
	674	interrupts = <47>;
	675	clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
	676	<&ccu CLK_DRAM_DE_FE>;
	677	clock-names = "ahb", "mod",
	678	"ram";
	679	resets = <&ccu RST_DE_FE>;
	680	status = "disabled";
	681
	682	ports {
	683	#address-cells = <1>;
	684	#size-cells = <0>;
	685
	686	fe0_out: port@1 {
	687	#address-cells = <1>;
	688	#size-cells = <0>;
	689	reg = <1>;
	690
	691	fe0_out_be0: endpoint@0 {
	692	reg = <0>;
	693	remote-endpoint = <&be0_in_fe0>;
	694	};
	695	};
	696	};
	697	};
	698
8dccafaa	699	be0: display-backend@1e60000 {
85870196 MR	700	compatible = "allwinner,sun5i-a13-display-backend";
85870196 MR	701	reg = <0x01e60000 0x10000>;
69e3a946	702	interrupts = <47>;
85870196 MR	703	clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
	704	<&ccu CLK_DRAM_DE_BE>;
	705	clock-names = "ahb", "mod",
	706	"ram";
	707	resets = <&ccu RST_DE_BE>;
	708	status = "disabled";
	709
	710	assigned-clocks = <&ccu CLK_DE_BE>;
	711	assigned-clock-rates = <300000000>;
	712
	713	ports {
	714	#address-cells = <1>;
	715	#size-cells = <0>;
	716
	717	be0_in: port@0 {
	718	#address-cells = <1>;
	719	#size-cells = <0>;
	720	reg = <0>;
	721
	722	be0_in_fe0: endpoint@0 {
	723	reg = <0>;
	724	remote-endpoint = <&fe0_out_be0>;
	725	};
	726	};
	727
	728	be0_out: port@1 {
	729	#address-cells = <1>;
	730	#size-cells = <0>;
	731	reg = <1>;
	732
	733	be0_out_tcon0: endpoint@0 {
	734	reg = <0>;
	735	remote-endpoint = <&tcon0_in_be0>;
	736	};
	737	};
	738	};
	739	};
fbfa7367 MR	740	};
fbfa7367 MR	741	};