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fbfa7367 MR |
1 | /* |
2 | * Copyright 2012-2015 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
6 | * This file is dual-licensed: you can use it either under the terms | |
7 | * of the GPL or the X11 license, at your option. Note that this dual | |
8 | * licensing only applies to this file, and not this project as a | |
9 | * whole. | |
10 | * | |
11 | * a) This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of the | |
14 | * License, or (at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
fbfa7367 MR |
21 | * Or, alternatively, |
22 | * | |
23 | * b) Permission is hereby granted, free of charge, to any person | |
24 | * obtaining a copy of this software and associated documentation | |
25 | * files (the "Software"), to deal in the Software without | |
26 | * restriction, including without limitation the rights to use, | |
27 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
28 | * sell copies of the Software, and to permit persons to whom the | |
29 | * Software is furnished to do so, subject to the following | |
30 | * conditions: | |
31 | * | |
32 | * The above copyright notice and this permission notice shall be | |
33 | * included in all copies or substantial portions of the Software. | |
34 | * | |
35 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
36 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
37 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
38 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
39 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
40 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
41 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
42 | * OTHER DEALINGS IN THE SOFTWARE. | |
43 | */ | |
44 | ||
45 | #include "skeleton.dtsi" | |
46 | ||
47 | #include <dt-bindings/dma/sun4i-a10.h> | |
48 | #include <dt-bindings/pinctrl/sun4i-a10.h> | |
49 | ||
50 | / { | |
51 | interrupt-parent = <&intc>; | |
52 | ||
53 | cpus { | |
54 | #address-cells = <1>; | |
55 | #size-cells = <0>; | |
56 | ||
57 | cpu0: cpu@0 { | |
58 | device_type = "cpu"; | |
59 | compatible = "arm,cortex-a8"; | |
60 | reg = <0x0>; | |
61 | clocks = <&cpu>; | |
62 | }; | |
63 | }; | |
64 | ||
65 | clocks { | |
66 | #address-cells = <1>; | |
67 | #size-cells = <1>; | |
68 | ranges; | |
69 | ||
70 | /* | |
71 | * This is a dummy clock, to be used as placeholder on | |
72 | * other mux clocks when a specific parent clock is not | |
73 | * yet implemented. It should be dropped when the driver | |
74 | * is complete. | |
75 | */ | |
76 | dummy: dummy { | |
77 | #clock-cells = <0>; | |
78 | compatible = "fixed-clock"; | |
79 | clock-frequency = <0>; | |
80 | }; | |
81 | ||
82 | osc24M: clk@01c20050 { | |
83 | #clock-cells = <0>; | |
84 | compatible = "allwinner,sun4i-a10-osc-clk"; | |
85 | reg = <0x01c20050 0x4>; | |
86 | clock-frequency = <24000000>; | |
87 | clock-output-names = "osc24M"; | |
88 | }; | |
89 | ||
90 | osc32k: clk@0 { | |
91 | #clock-cells = <0>; | |
92 | compatible = "fixed-clock"; | |
93 | clock-frequency = <32768>; | |
94 | clock-output-names = "osc32k"; | |
95 | }; | |
96 | ||
97 | pll1: clk@01c20000 { | |
98 | #clock-cells = <0>; | |
99 | compatible = "allwinner,sun4i-a10-pll1-clk"; | |
100 | reg = <0x01c20000 0x4>; | |
101 | clocks = <&osc24M>; | |
102 | clock-output-names = "pll1"; | |
103 | }; | |
104 | ||
105 | pll4: clk@01c20018 { | |
106 | #clock-cells = <0>; | |
107 | compatible = "allwinner,sun4i-a10-pll1-clk"; | |
108 | reg = <0x01c20018 0x4>; | |
109 | clocks = <&osc24M>; | |
110 | clock-output-names = "pll4"; | |
111 | }; | |
112 | ||
113 | pll5: clk@01c20020 { | |
114 | #clock-cells = <1>; | |
115 | compatible = "allwinner,sun4i-a10-pll5-clk"; | |
116 | reg = <0x01c20020 0x4>; | |
117 | clocks = <&osc24M>; | |
118 | clock-output-names = "pll5_ddr", "pll5_other"; | |
119 | }; | |
120 | ||
121 | pll6: clk@01c20028 { | |
122 | #clock-cells = <1>; | |
123 | compatible = "allwinner,sun4i-a10-pll6-clk"; | |
124 | reg = <0x01c20028 0x4>; | |
125 | clocks = <&osc24M>; | |
126 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
127 | }; | |
128 | ||
129 | /* dummy is 200M */ | |
130 | cpu: cpu@01c20054 { | |
131 | #clock-cells = <0>; | |
132 | compatible = "allwinner,sun4i-a10-cpu-clk"; | |
133 | reg = <0x01c20054 0x4>; | |
134 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
135 | clock-output-names = "cpu"; | |
136 | }; | |
137 | ||
138 | axi: axi@01c20054 { | |
139 | #clock-cells = <0>; | |
140 | compatible = "allwinner,sun4i-a10-axi-clk"; | |
141 | reg = <0x01c20054 0x4>; | |
142 | clocks = <&cpu>; | |
143 | clock-output-names = "axi"; | |
144 | }; | |
145 | ||
146 | ahb: ahb@01c20054 { | |
147 | #clock-cells = <0>; | |
2186df37 | 148 | compatible = "allwinner,sun5i-a13-ahb-clk"; |
fbfa7367 | 149 | reg = <0x01c20054 0x4>; |
2186df37 | 150 | clocks = <&axi>, <&cpu>, <&pll6 1>; |
fbfa7367 | 151 | clock-output-names = "ahb"; |
2186df37 CYT |
152 | /* |
153 | * Use PLL6 as parent, instead of CPU/AXI | |
154 | * which has rate changes due to cpufreq | |
155 | */ | |
156 | assigned-clocks = <&ahb>; | |
157 | assigned-clock-parents = <&pll6 1>; | |
fbfa7367 MR |
158 | }; |
159 | ||
160 | apb0: apb0@01c20054 { | |
161 | #clock-cells = <0>; | |
162 | compatible = "allwinner,sun4i-a10-apb0-clk"; | |
163 | reg = <0x01c20054 0x4>; | |
164 | clocks = <&ahb>; | |
165 | clock-output-names = "apb0"; | |
166 | }; | |
167 | ||
168 | apb1: clk@01c20058 { | |
169 | #clock-cells = <0>; | |
170 | compatible = "allwinner,sun4i-a10-apb1-clk"; | |
171 | reg = <0x01c20058 0x4>; | |
172 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; | |
173 | clock-output-names = "apb1"; | |
174 | }; | |
175 | ||
176 | axi_gates: clk@01c2005c { | |
177 | #clock-cells = <1>; | |
178 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; | |
179 | reg = <0x01c2005c 0x4>; | |
180 | clocks = <&axi>; | |
181 | clock-output-names = "axi_dram"; | |
182 | }; | |
183 | ||
184 | nand_clk: clk@01c20080 { | |
185 | #clock-cells = <0>; | |
186 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
187 | reg = <0x01c20080 0x4>; | |
188 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
189 | clock-output-names = "nand"; | |
190 | }; | |
191 | ||
192 | ms_clk: clk@01c20084 { | |
193 | #clock-cells = <0>; | |
194 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
195 | reg = <0x01c20084 0x4>; | |
196 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
197 | clock-output-names = "ms"; | |
198 | }; | |
199 | ||
200 | mmc0_clk: clk@01c20088 { | |
201 | #clock-cells = <1>; | |
202 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
203 | reg = <0x01c20088 0x4>; | |
204 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
205 | clock-output-names = "mmc0", | |
206 | "mmc0_output", | |
207 | "mmc0_sample"; | |
208 | }; | |
209 | ||
210 | mmc1_clk: clk@01c2008c { | |
211 | #clock-cells = <1>; | |
212 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
213 | reg = <0x01c2008c 0x4>; | |
214 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
215 | clock-output-names = "mmc1", | |
216 | "mmc1_output", | |
217 | "mmc1_sample"; | |
218 | }; | |
219 | ||
220 | mmc2_clk: clk@01c20090 { | |
221 | #clock-cells = <1>; | |
222 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
223 | reg = <0x01c20090 0x4>; | |
224 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
225 | clock-output-names = "mmc2", | |
226 | "mmc2_output", | |
227 | "mmc2_sample"; | |
228 | }; | |
229 | ||
230 | ts_clk: clk@01c20098 { | |
231 | #clock-cells = <0>; | |
232 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
233 | reg = <0x01c20098 0x4>; | |
234 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
235 | clock-output-names = "ts"; | |
236 | }; | |
237 | ||
238 | ss_clk: clk@01c2009c { | |
239 | #clock-cells = <0>; | |
240 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
241 | reg = <0x01c2009c 0x4>; | |
242 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
243 | clock-output-names = "ss"; | |
244 | }; | |
245 | ||
246 | spi0_clk: clk@01c200a0 { | |
247 | #clock-cells = <0>; | |
248 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
249 | reg = <0x01c200a0 0x4>; | |
250 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
251 | clock-output-names = "spi0"; | |
252 | }; | |
253 | ||
254 | spi1_clk: clk@01c200a4 { | |
255 | #clock-cells = <0>; | |
256 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
257 | reg = <0x01c200a4 0x4>; | |
258 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
259 | clock-output-names = "spi1"; | |
260 | }; | |
261 | ||
262 | spi2_clk: clk@01c200a8 { | |
263 | #clock-cells = <0>; | |
264 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
265 | reg = <0x01c200a8 0x4>; | |
266 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
267 | clock-output-names = "spi2"; | |
268 | }; | |
269 | ||
270 | ir0_clk: clk@01c200b0 { | |
271 | #clock-cells = <0>; | |
272 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
273 | reg = <0x01c200b0 0x4>; | |
274 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
275 | clock-output-names = "ir0"; | |
276 | }; | |
277 | ||
278 | usb_clk: clk@01c200cc { | |
279 | #clock-cells = <1>; | |
8358aada | 280 | #reset-cells = <1>; |
fbfa7367 MR |
281 | compatible = "allwinner,sun5i-a13-usb-clk"; |
282 | reg = <0x01c200cc 0x4>; | |
283 | clocks = <&pll6 1>; | |
284 | clock-output-names = "usb_ohci0", "usb_phy"; | |
285 | }; | |
286 | ||
287 | mbus_clk: clk@01c2015c { | |
288 | #clock-cells = <0>; | |
289 | compatible = "allwinner,sun5i-a13-mbus-clk"; | |
290 | reg = <0x01c2015c 0x4>; | |
291 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
292 | clock-output-names = "mbus"; | |
293 | }; | |
294 | }; | |
295 | ||
296 | soc@01c00000 { | |
297 | compatible = "simple-bus"; | |
298 | #address-cells = <1>; | |
299 | #size-cells = <1>; | |
300 | ranges; | |
301 | ||
302 | dma: dma-controller@01c02000 { | |
303 | compatible = "allwinner,sun4i-a10-dma"; | |
304 | reg = <0x01c02000 0x1000>; | |
305 | interrupts = <27>; | |
306 | clocks = <&ahb_gates 6>; | |
307 | #dma-cells = <2>; | |
308 | }; | |
309 | ||
310 | spi0: spi@01c05000 { | |
311 | compatible = "allwinner,sun4i-a10-spi"; | |
312 | reg = <0x01c05000 0x1000>; | |
313 | interrupts = <10>; | |
314 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
315 | clock-names = "ahb", "mod"; | |
316 | dmas = <&dma SUN4I_DMA_DEDICATED 27>, | |
317 | <&dma SUN4I_DMA_DEDICATED 26>; | |
318 | dma-names = "rx", "tx"; | |
319 | status = "disabled"; | |
320 | #address-cells = <1>; | |
321 | #size-cells = <0>; | |
322 | }; | |
323 | ||
324 | spi1: spi@01c06000 { | |
325 | compatible = "allwinner,sun4i-a10-spi"; | |
326 | reg = <0x01c06000 0x1000>; | |
327 | interrupts = <11>; | |
328 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
329 | clock-names = "ahb", "mod"; | |
330 | dmas = <&dma SUN4I_DMA_DEDICATED 9>, | |
331 | <&dma SUN4I_DMA_DEDICATED 8>; | |
332 | dma-names = "rx", "tx"; | |
333 | status = "disabled"; | |
334 | #address-cells = <1>; | |
335 | #size-cells = <0>; | |
336 | }; | |
337 | ||
338 | mmc0: mmc@01c0f000 { | |
339 | compatible = "allwinner,sun5i-a13-mmc"; | |
340 | reg = <0x01c0f000 0x1000>; | |
341 | clocks = <&ahb_gates 8>, | |
342 | <&mmc0_clk 0>, | |
343 | <&mmc0_clk 1>, | |
344 | <&mmc0_clk 2>; | |
345 | clock-names = "ahb", | |
346 | "mmc", | |
347 | "output", | |
348 | "sample"; | |
349 | interrupts = <32>; | |
350 | status = "disabled"; | |
4c1bb9c3 HG |
351 | #address-cells = <1>; |
352 | #size-cells = <0>; | |
fbfa7367 MR |
353 | }; |
354 | ||
355 | mmc1: mmc@01c10000 { | |
356 | compatible = "allwinner,sun5i-a13-mmc"; | |
357 | reg = <0x01c10000 0x1000>; | |
358 | clocks = <&ahb_gates 9>, | |
359 | <&mmc1_clk 0>, | |
360 | <&mmc1_clk 1>, | |
361 | <&mmc1_clk 2>; | |
362 | clock-names = "ahb", | |
363 | "mmc", | |
364 | "output", | |
365 | "sample"; | |
366 | interrupts = <33>; | |
367 | status = "disabled"; | |
4c1bb9c3 HG |
368 | #address-cells = <1>; |
369 | #size-cells = <0>; | |
fbfa7367 MR |
370 | }; |
371 | ||
372 | mmc2: mmc@01c11000 { | |
373 | compatible = "allwinner,sun5i-a13-mmc"; | |
374 | reg = <0x01c11000 0x1000>; | |
375 | clocks = <&ahb_gates 10>, | |
376 | <&mmc2_clk 0>, | |
377 | <&mmc2_clk 1>, | |
378 | <&mmc2_clk 2>; | |
379 | clock-names = "ahb", | |
380 | "mmc", | |
381 | "output", | |
382 | "sample"; | |
383 | interrupts = <34>; | |
384 | status = "disabled"; | |
4c1bb9c3 HG |
385 | #address-cells = <1>; |
386 | #size-cells = <0>; | |
fbfa7367 MR |
387 | }; |
388 | ||
389 | usbphy: phy@01c13400 { | |
390 | #phy-cells = <1>; | |
391 | compatible = "allwinner,sun5i-a13-usb-phy"; | |
392 | reg = <0x01c13400 0x10 0x01c14800 0x4>; | |
393 | reg-names = "phy_ctrl", "pmu1"; | |
394 | clocks = <&usb_clk 8>; | |
395 | clock-names = "usb_phy"; | |
396 | resets = <&usb_clk 0>, <&usb_clk 1>; | |
397 | reset-names = "usb0_reset", "usb1_reset"; | |
398 | status = "disabled"; | |
399 | }; | |
400 | ||
401 | ehci0: usb@01c14000 { | |
3727ed3b | 402 | compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; |
fbfa7367 MR |
403 | reg = <0x01c14000 0x100>; |
404 | interrupts = <39>; | |
405 | clocks = <&ahb_gates 1>; | |
406 | phys = <&usbphy 1>; | |
407 | phy-names = "usb"; | |
408 | status = "disabled"; | |
409 | }; | |
410 | ||
411 | ohci0: usb@01c14400 { | |
3727ed3b | 412 | compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; |
fbfa7367 MR |
413 | reg = <0x01c14400 0x100>; |
414 | interrupts = <40>; | |
415 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
416 | phys = <&usbphy 1>; | |
417 | phy-names = "usb"; | |
418 | status = "disabled"; | |
419 | }; | |
420 | ||
421 | spi2: spi@01c17000 { | |
422 | compatible = "allwinner,sun4i-a10-spi"; | |
423 | reg = <0x01c17000 0x1000>; | |
424 | interrupts = <12>; | |
425 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
426 | clock-names = "ahb", "mod"; | |
427 | dmas = <&dma SUN4I_DMA_DEDICATED 29>, | |
428 | <&dma SUN4I_DMA_DEDICATED 28>; | |
429 | dma-names = "rx", "tx"; | |
430 | status = "disabled"; | |
431 | #address-cells = <1>; | |
432 | #size-cells = <0>; | |
433 | }; | |
434 | ||
435 | intc: interrupt-controller@01c20400 { | |
436 | compatible = "allwinner,sun4i-a10-ic"; | |
437 | reg = <0x01c20400 0x400>; | |
438 | interrupt-controller; | |
439 | #interrupt-cells = <1>; | |
440 | }; | |
441 | ||
442 | pio: pinctrl@01c20800 { | |
443 | reg = <0x01c20800 0x400>; | |
444 | interrupts = <28>; | |
445 | clocks = <&apb0_gates 5>; | |
446 | gpio-controller; | |
447 | interrupt-controller; | |
448 | #interrupt-cells = <2>; | |
449 | #size-cells = <0>; | |
450 | #gpio-cells = <3>; | |
51fbba42 MR |
451 | |
452 | i2c0_pins_a: i2c0@0 { | |
453 | allwinner,pins = "PB0", "PB1"; | |
454 | allwinner,function = "i2c0"; | |
455 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
456 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
457 | }; | |
458 | ||
459 | i2c1_pins_a: i2c1@0 { | |
460 | allwinner,pins = "PB15", "PB16"; | |
461 | allwinner,function = "i2c1"; | |
462 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
463 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
464 | }; | |
465 | ||
466 | i2c2_pins_a: i2c2@0 { | |
467 | allwinner,pins = "PB17", "PB18"; | |
468 | allwinner,function = "i2c2"; | |
469 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
470 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
471 | }; | |
472 | ||
473 | mmc0_pins_a: mmc0@0 { | |
d8cacaa3 MR |
474 | allwinner,pins = "PF0", "PF1", "PF2", "PF3", |
475 | "PF4", "PF5"; | |
51fbba42 MR |
476 | allwinner,function = "mmc0"; |
477 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; | |
478 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
479 | }; | |
e1fe9f8c HG |
480 | |
481 | mmc2_pins_a: mmc2@0 { | |
482 | allwinner,pins = "PC6", "PC7", "PC8", "PC9", | |
483 | "PC10", "PC11", "PC12", "PC13", | |
484 | "PC14", "PC15"; | |
485 | allwinner,function = "mmc2"; | |
486 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; | |
487 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
488 | }; | |
fbfa7367 MR |
489 | }; |
490 | ||
491 | timer@01c20c00 { | |
492 | compatible = "allwinner,sun4i-a10-timer"; | |
493 | reg = <0x01c20c00 0x90>; | |
494 | interrupts = <22>; | |
495 | clocks = <&osc24M>; | |
496 | }; | |
497 | ||
498 | wdt: watchdog@01c20c90 { | |
499 | compatible = "allwinner,sun4i-a10-wdt"; | |
500 | reg = <0x01c20c90 0x10>; | |
501 | }; | |
502 | ||
503 | lradc: lradc@01c22800 { | |
504 | compatible = "allwinner,sun4i-a10-lradc-keys"; | |
505 | reg = <0x01c22800 0x100>; | |
506 | interrupts = <31>; | |
507 | status = "disabled"; | |
508 | }; | |
509 | ||
510 | sid: eeprom@01c23800 { | |
511 | compatible = "allwinner,sun4i-a10-sid"; | |
512 | reg = <0x01c23800 0x10>; | |
513 | }; | |
514 | ||
515 | rtp: rtp@01c25000 { | |
8bf1b9b3 | 516 | compatible = "allwinner,sun5i-a13-ts"; |
fbfa7367 MR |
517 | reg = <0x01c25000 0x100>; |
518 | interrupts = <29>; | |
519 | #thermal-sensor-cells = <0>; | |
520 | }; | |
521 | ||
522 | uart1: serial@01c28400 { | |
523 | compatible = "snps,dw-apb-uart"; | |
524 | reg = <0x01c28400 0x400>; | |
525 | interrupts = <2>; | |
526 | reg-shift = <2>; | |
527 | reg-io-width = <4>; | |
528 | clocks = <&apb1_gates 17>; | |
529 | status = "disabled"; | |
530 | }; | |
531 | ||
532 | uart3: serial@01c28c00 { | |
533 | compatible = "snps,dw-apb-uart"; | |
534 | reg = <0x01c28c00 0x400>; | |
535 | interrupts = <4>; | |
536 | reg-shift = <2>; | |
537 | reg-io-width = <4>; | |
538 | clocks = <&apb1_gates 19>; | |
539 | status = "disabled"; | |
540 | }; | |
541 | ||
542 | i2c0: i2c@01c2ac00 { | |
543 | compatible = "allwinner,sun4i-a10-i2c"; | |
544 | reg = <0x01c2ac00 0x400>; | |
545 | interrupts = <7>; | |
546 | clocks = <&apb1_gates 0>; | |
547 | status = "disabled"; | |
548 | #address-cells = <1>; | |
549 | #size-cells = <0>; | |
550 | }; | |
551 | ||
552 | i2c1: i2c@01c2b000 { | |
553 | compatible = "allwinner,sun4i-a10-i2c"; | |
554 | reg = <0x01c2b000 0x400>; | |
555 | interrupts = <8>; | |
556 | clocks = <&apb1_gates 1>; | |
557 | status = "disabled"; | |
558 | #address-cells = <1>; | |
559 | #size-cells = <0>; | |
560 | }; | |
561 | ||
562 | i2c2: i2c@01c2b400 { | |
563 | compatible = "allwinner,sun4i-a10-i2c"; | |
564 | reg = <0x01c2b400 0x400>; | |
565 | interrupts = <9>; | |
566 | clocks = <&apb1_gates 2>; | |
567 | status = "disabled"; | |
568 | #address-cells = <1>; | |
569 | #size-cells = <0>; | |
570 | }; | |
571 | ||
572 | timer@01c60000 { | |
573 | compatible = "allwinner,sun5i-a13-hstimer"; | |
574 | reg = <0x01c60000 0x1000>; | |
575 | interrupts = <82>, <83>; | |
576 | clocks = <&ahb_gates 28>; | |
577 | }; | |
578 | }; | |
579 | }; |