[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / sun5i.dtsi

/*
 * Copyright 2012-2015 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton.dtsi"

#include <dt-bindings/clock/sun5i-ccu.h>
#include <dt-bindings/dma/sun4i-a10.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <dt-bindings/reset/sun5i-ccu.h>

/ {
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0x0>;
			clocks = <&ccu CLK_CPU>;
		};
	};

	chosen {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		framebuffer@0 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0";
			clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
				 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
			status = "disabled";
		};

		framebuffer@1 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0-tve0";
			clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
				 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
				 <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
			status = "disabled";
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc24M: clk@01c20050 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		osc32k: clk@0 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		sram-controller@01c00000 {
			compatible = "allwinner,sun4i-a10-sram-controller";
			reg = <0x01c00000 0x30>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			sram_a: sram@00000000 {
				compatible = "mmio-sram";
				reg = <0x00000000 0xc000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00000000 0xc000>;
			};

			emac_sram: sram-section@8000 {
				compatible = "allwinner,sun4i-a10-sram-a3-a4";
				reg = <0x8000 0x4000>;
				status = "disabled";
			};

			sram_d: sram@00010000 {
				compatible = "mmio-sram";
				reg = <0x00010000 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00010000 0x1000>;

				otg_sram: sram-section@0000 {
					compatible = "allwinner,sun4i-a10-sram-d";
					reg = <0x0000 0x1000>;
					status = "disabled";
				};
			};
		};

		dma: dma-controller@01c02000 {
			compatible = "allwinner,sun4i-a10-dma";
			reg = <0x01c02000 0x1000>;
			interrupts = <27>;
			clocks = <&ccu CLK_AHB_DMA>;
			#dma-cells = <2>;
		};

		spi0: spi@01c05000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c05000 0x1000>;
			interrupts = <10>;
			clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 27>,
			       <&dma SUN4I_DMA_DEDICATED 26>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@01c06000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c06000 0x1000>;
			interrupts = <11>;
			clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 9>,
			       <&dma SUN4I_DMA_DEDICATED 8>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		emac: ethernet@01c0b000 {
			compatible = "allwinner,sun4i-a10-emac";
			reg = <0x01c0b000 0x1000>;
			interrupts = <55>;
			clocks = <&ccu CLK_AHB_EMAC>;
			allwinner,sram = <&emac_sram 1>;
			status = "disabled";
		};

		mdio: mdio@01c0b080 {
			compatible = "allwinner,sun4i-a10-mdio";
			reg = <0x01c0b080 0x14>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		tcon0: lcd-controller@01c0c000 {
			compatible = "allwinner,sun5i-a13-tcon";
			reg = <0x01c0c000 0x1000>;
			interrupts = <44>;
			resets = <&ccu RST_LCD>;
			reset-names = "lcd";
			clocks = <&ccu CLK_AHB_LCD>,
				 <&ccu CLK_TCON_CH0>,
				 <&ccu CLK_TCON_CH1>;
			clock-names = "ahb",
				      "tcon-ch0",
				      "tcon-ch1";
			clock-output-names = "tcon-pixel-clock";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				tcon0_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					tcon0_in_be0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&be0_out_tcon0>;
					};
				};

				tcon0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;
				};
			};
		};

		mmc0: mmc@01c0f000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c0f000 0x1000>;
			clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
			clock-names = "ahb", "mmc";
			interrupts = <32>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc1: mmc@01c10000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c10000 0x1000>;
			clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
			clock-names = "ahb", "mmc";
			interrupts = <33>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc2: mmc@01c11000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c11000 0x1000>;
			clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
			clock-names = "ahb", "mmc";
			interrupts = <34>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		usb_otg: usb@01c13000 {
			compatible = "allwinner,sun4i-a10-musb";
			reg = <0x01c13000 0x0400>;
			clocks = <&ccu CLK_AHB_OTG>;
			interrupts = <38>;
			interrupt-names = "mc";
			phys = <&usbphy 0>;
			phy-names = "usb";
			extcon = <&usbphy 0>;
			allwinner,sram = <&otg_sram 1>;
			status = "disabled";
		};

		usbphy: phy@01c13400 {
			#phy-cells = <1>;
			compatible = "allwinner,sun5i-a13-usb-phy";
			reg = <0x01c13400 0x10 0x01c14800 0x4>;
			reg-names = "phy_ctrl", "pmu1";
			clocks = <&ccu CLK_USB_PHY0>;
			clock-names = "usb_phy";
			resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
			reset-names = "usb0_reset", "usb1_reset";
			status = "disabled";
		};

		ehci0: usb@01c14000 {
			compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
			reg = <0x01c14000 0x100>;
			interrupts = <39>;
			clocks = <&ccu CLK_AHB_EHCI>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci0: usb@01c14400 {
			compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
			reg = <0x01c14400 0x100>;
			interrupts = <40>;
			clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		spi2: spi@01c17000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c17000 0x1000>;
			interrupts = <12>;
			clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 29>,
			       <&dma SUN4I_DMA_DEDICATED 28>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		ccu: clock@01c20000 {
			reg = <0x01c20000 0x400>;
			clocks = <&osc24M>, <&osc32k>;
			clock-names = "hosc", "losc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		intc: interrupt-controller@01c20400 {
			compatible = "allwinner,sun4i-a10-ic";
			reg = <0x01c20400 0x400>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		pio: pinctrl@01c20800 {
			reg = <0x01c20800 0x400>;
			interrupts = <28>;
			clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
			clock-names = "apb", "hosc", "losc";
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <3>;
			#gpio-cells = <3>;

			emac_pins_a: emac0@0 {
				pins = "PD6", "PD7", "PD10",
				       "PD11", "PD12", "PD13", "PD14",
				       "PD15", "PD18", "PD19", "PD20",
				       "PD21", "PD22", "PD23", "PD24",
				       "PD25", "PD26", "PD27";
				function = "emac";
			};

			i2c0_pins_a: i2c0@0 {
				pins = "PB0", "PB1";
				function = "i2c0";
			};

			i2c1_pins_a: i2c1@0 {
				pins = "PB15", "PB16";
				function = "i2c1";
			};

			i2c2_pins_a: i2c2@0 {
				pins = "PB17", "PB18";
				function = "i2c2";
			};

			lcd_rgb565_pins: lcd_rgb565@0 {
				pins = "PD3", "PD4", "PD5", "PD6", "PD7",
						 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
						 "PD19", "PD20", "PD21", "PD22", "PD23",
						 "PD24", "PD25", "PD26", "PD27";
				function = "lcd0";
			};

			lcd_rgb666_pins: lcd_rgb666@0 {
				pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
				       "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
				       "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
				       "PD24", "PD25", "PD26", "PD27";
				function = "lcd0";
			};

			mmc0_pins_a: mmc0@0 {
				pins = "PF0", "PF1", "PF2", "PF3",
				       "PF4", "PF5";
				function = "mmc0";
				drive-strength = <30>;
				bias-pull-up;
			};

			mmc2_pins_a: mmc2@0 {
				pins = "PC6", "PC7", "PC8", "PC9",
				       "PC10", "PC11", "PC12", "PC13",
				       "PC14", "PC15";
				function = "mmc2";
				drive-strength = <30>;
				bias-pull-up;
			};

			mmc2_4bit_pins_a: mmc2-4bit@0 {
				pins = "PC6", "PC7", "PC8", "PC9",
				       "PC10", "PC11";
				function = "mmc2";
				drive-strength = <30>;
				bias-pull-up;
			};

			spi2_pins_a: spi2@0 {
				pins = "PE1", "PE2", "PE3";
				function = "spi2";
			};

			spi2_cs0_pins_a: spi2-cs0@0 {
				pins = "PE0";
				function = "spi2";
			};

			uart1_pins_a: uart1@0 {
				pins = "PE10", "PE11";
				function = "uart1";
			};

			uart1_pins_b: uart1@1 {
				pins = "PG3", "PG4";
				function = "uart1";
			};

			uart2_pins_a: uart2@0 {
				pins = "PD2", "PD3";
				function = "uart2";
			};

			uart2_cts_rts_pins_a: uart2-cts-rts@0 {
				pins = "PD4", "PD5";
				function = "uart2";
			};

			uart3_pins_a: uart3@0 {
				pins = "PG9", "PG10";
				function = "uart3";
			};

			uart3_cts_rts_pins_a: uart3-cts-rts@0 {
				pins = "PG11", "PG12";
				function = "uart3";
			};

			pwm0_pins: pwm0 {
				pins = "PB2";
				function = "pwm";
			};
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x01c20c00 0x90>;
			interrupts = <22>;
			clocks = <&ccu CLK_HOSC>;
		};

		wdt: watchdog@01c20c90 {
			compatible = "allwinner,sun4i-a10-wdt";
			reg = <0x01c20c90 0x10>;
		};

		lradc: lradc@01c22800 {
			compatible = "allwinner,sun4i-a10-lradc-keys";
			reg = <0x01c22800 0x100>;
			interrupts = <31>;
			status = "disabled";
		};

		codec: codec@01c22c00 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sun4i-a10-codec";
			reg = <0x01c22c00 0x40>;
			interrupts = <30>;
			clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
			clock-names = "apb", "codec";
			dmas = <&dma SUN4I_DMA_NORMAL 19>,
			       <&dma SUN4I_DMA_NORMAL 19>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		sid: eeprom@01c23800 {
			compatible = "allwinner,sun4i-a10-sid";
			reg = <0x01c23800 0x10>;
		};

		rtp: rtp@01c25000 {
			compatible = "allwinner,sun5i-a13-ts";
			reg = <0x01c25000 0x100>;
			interrupts = <29>;
			#thermal-sensor-cells = <0>;
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_APB1_UART0>;
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <2>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_APB1_UART1>;
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <3>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_APB1_UART2>;
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_APB1_UART3>;
			status = "disabled";
		};

		i2c0: i2c@01c2ac00 {
			compatible = "allwinner,sun4i-a10-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <7>;
			clocks = <&ccu CLK_APB1_I2C0>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@01c2b000 {
			compatible = "allwinner,sun4i-a10-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <8>;
			clocks = <&ccu CLK_APB1_I2C1>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@01c2b400 {
			compatible = "allwinner,sun4i-a10-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <9>;
			clocks = <&ccu CLK_APB1_I2C2>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		timer@01c60000 {
			compatible = "allwinner,sun5i-a13-hstimer";
			reg = <0x01c60000 0x1000>;
			interrupts = <82>, <83>;
			clocks = <&ccu CLK_AHB_HSTIMER>;
		};

		fe0: display-frontend@01e00000 {
			compatible = "allwinner,sun5i-a13-display-frontend";
			reg = <0x01e00000 0x20000>;
			interrupts = <47>;
			clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
				 <&ccu CLK_DRAM_DE_FE>;
			clock-names = "ahb", "mod",
				      "ram";
			resets = <&ccu RST_DE_FE>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				fe0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					fe0_out_be0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&be0_in_fe0>;
					};
				};
			};
		};

		be0: display-backend@01e60000 {
			compatible = "allwinner,sun5i-a13-display-backend";
			reg = <0x01e60000 0x10000>;
			clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
				 <&ccu CLK_DRAM_DE_BE>;
			clock-names = "ahb", "mod",
				      "ram";
			resets = <&ccu RST_DE_BE>;
			status = "disabled";

			assigned-clocks = <&ccu CLK_DE_BE>;
			assigned-clock-rates = <300000000>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				be0_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					be0_in_fe0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&fe0_out_be0>;
					};
				};

				be0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					be0_out_tcon0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&tcon0_in_be0>;
					};
				};
			};
		};
	};
};
Commit	Line	Data
fbfa7367 MR	1	/*
	2	* Copyright 2012-2015 Maxime Ripard
	3	*
	4	* Maxime Ripard <maxime.ripard@free-electrons.com>
	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
	11	* a) This library is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This library is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
fbfa7367 MR	21	* Or, alternatively,
	22	*
	23	* b) Permission is hereby granted, free of charge, to any person
	24	* obtaining a copy of this software and associated documentation
	25	* files (the "Software"), to deal in the Software without
	26	* restriction, including without limitation the rights to use,
	27	* copy, modify, merge, publish, distribute, sublicense, and/or
	28	* sell copies of the Software, and to permit persons to whom the
	29	* Software is furnished to do so, subject to the following
	30	* conditions:
	31	*
	32	* The above copyright notice and this permission notice shall be
	33	* included in all copies or substantial portions of the Software.
	34	*
	35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	37	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	38	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	39	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	41	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	42	* OTHER DEALINGS IN THE SOFTWARE.
	43	*/
	44
	45	#include "skeleton.dtsi"
	46
98a59a0f	47	#include <dt-bindings/clock/sun5i-ccu.h>
fbfa7367 MR	48	#include <dt-bindings/dma/sun4i-a10.h>
fbfa7367 MR	49	#include <dt-bindings/pinctrl/sun4i-a10.h>
98a59a0f	50	#include <dt-bindings/reset/sun5i-ccu.h>
fbfa7367 MR	51
	52	/ {
	53	interrupt-parent = <&intc>;
	54
	55	cpus {
	56	#address-cells = <1>;
	57	#size-cells = <0>;
	58
	59	cpu0: cpu@0 {
	60	device_type = "cpu";
	61	compatible = "arm,cortex-a8";
	62	reg = <0x0>;
98a59a0f	63	clocks = <&ccu CLK_CPU>;
fbfa7367 MR	64	};
	65	};
	66
85870196 MR	67	chosen {
	68	#address-cells = <1>;
	69	#size-cells = <1>;
	70	ranges;
	71
	72	framebuffer@0 {
	73	compatible = "allwinner,simple-framebuffer",
	74	"simple-framebuffer";
	75	allwinner,pipeline = "de_be0-lcd0";
	76	clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
	77	<&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
	78	status = "disabled";
	79	};
78f6d982 MR	80
	81	framebuffer@1 {
	82	compatible = "allwinner,simple-framebuffer",
	83	"simple-framebuffer";
	84	allwinner,pipeline = "de_be0-lcd0-tve0";
	85	clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
	86	<&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
	87	<&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
	88	status = "disabled";
	89	};
85870196 MR	90	};
85870196 MR	91
fbfa7367 MR	92	clocks {
	93	#address-cells = <1>;
	94	#size-cells = <1>;
	95	ranges;
	96
fbfa7367 MR	97	osc24M: clk@01c20050 {
fbfa7367 MR	98	#clock-cells = <0>;
98a59a0f	99	compatible = "fixed-clock";
fbfa7367 MR	100	clock-frequency = <24000000>;
	101	clock-output-names = "osc24M";
	102	};
	103
	104	osc32k: clk@0 {
	105	#clock-cells = <0>;
	106	compatible = "fixed-clock";
	107	clock-frequency = <32768>;
	108	clock-output-names = "osc32k";
	109	};
fbfa7367 MR	110	};
	111
	112	soc@01c00000 {
	113	compatible = "simple-bus";
	114	#address-cells = <1>;
	115	#size-cells = <1>;
	116	ranges;
	117
00f69ba9 MR	118	sram-controller@01c00000 {
	119	compatible = "allwinner,sun4i-a10-sram-controller";
	120	reg = <0x01c00000 0x30>;
	121	#address-cells = <1>;
	122	#size-cells = <1>;
	123	ranges;
	124
	125	sram_a: sram@00000000 {
	126	compatible = "mmio-sram";
	127	reg = <0x00000000 0xc000>;
	128	#address-cells = <1>;
	129	#size-cells = <1>;
	130	ranges = <0 0x00000000 0xc000>;
	131	};
	132
78f6d982 MR	133	emac_sram: sram-section@8000 {
	134	compatible = "allwinner,sun4i-a10-sram-a3-a4";
	135	reg = <0x8000 0x4000>;
	136	status = "disabled";
	137	};
	138
00f69ba9 MR	139	sram_d: sram@00010000 {
	140	compatible = "mmio-sram";
	141	reg = <0x00010000 0x1000>;
	142	#address-cells = <1>;
	143	#size-cells = <1>;
	144	ranges = <0 0x00010000 0x1000>;
	145
	146	otg_sram: sram-section@0000 {
	147	compatible = "allwinner,sun4i-a10-sram-d";
	148	reg = <0x0000 0x1000>;
	149	status = "disabled";
	150	};
	151	};
	152	};
	153
fbfa7367 MR	154	dma: dma-controller@01c02000 {
	155	compatible = "allwinner,sun4i-a10-dma";
	156	reg = <0x01c02000 0x1000>;
	157	interrupts = <27>;
98a59a0f	158	clocks = <&ccu CLK_AHB_DMA>;
fbfa7367 MR	159	#dma-cells = <2>;
	160	};
	161
	162	spi0: spi@01c05000 {
	163	compatible = "allwinner,sun4i-a10-spi";
	164	reg = <0x01c05000 0x1000>;
	165	interrupts = <10>;
98a59a0f	166	clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
fbfa7367 MR	167	clock-names = "ahb", "mod";
	168	dmas = <&dma SUN4I_DMA_DEDICATED 27>,
	169	<&dma SUN4I_DMA_DEDICATED 26>;
	170	dma-names = "rx", "tx";
	171	status = "disabled";
	172	#address-cells = <1>;
	173	#size-cells = <0>;
	174	};
	175
	176	spi1: spi@01c06000 {
	177	compatible = "allwinner,sun4i-a10-spi";
	178	reg = <0x01c06000 0x1000>;
	179	interrupts = <11>;
98a59a0f	180	clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
fbfa7367 MR	181	clock-names = "ahb", "mod";
	182	dmas = <&dma SUN4I_DMA_DEDICATED 9>,
	183	<&dma SUN4I_DMA_DEDICATED 8>;
	184	dma-names = "rx", "tx";
	185	status = "disabled";
	186	#address-cells = <1>;
	187	#size-cells = <0>;
	188	};
	189
78f6d982 MR	190	emac: ethernet@01c0b000 {
	191	compatible = "allwinner,sun4i-a10-emac";
	192	reg = <0x01c0b000 0x1000>;
	193	interrupts = <55>;
	194	clocks = <&ccu CLK_AHB_EMAC>;
	195	allwinner,sram = <&emac_sram 1>;
	196	status = "disabled";
	197	};
	198
	199	mdio: mdio@01c0b080 {
	200	compatible = "allwinner,sun4i-a10-mdio";
	201	reg = <0x01c0b080 0x14>;
	202	status = "disabled";
	203	#address-cells = <1>;
	204	#size-cells = <0>;
	205	};
	206
85870196 MR	207	tcon0: lcd-controller@01c0c000 {
	208	compatible = "allwinner,sun5i-a13-tcon";
	209	reg = <0x01c0c000 0x1000>;
	210	interrupts = <44>;
	211	resets = <&ccu RST_LCD>;
	212	reset-names = "lcd";
	213	clocks = <&ccu CLK_AHB_LCD>,
	214	<&ccu CLK_TCON_CH0>,
	215	<&ccu CLK_TCON_CH1>;
	216	clock-names = "ahb",
	217	"tcon-ch0",
	218	"tcon-ch1";
	219	clock-output-names = "tcon-pixel-clock";
	220	status = "disabled";
	221
	222	ports {
	223	#address-cells = <1>;
	224	#size-cells = <0>;
	225
	226	tcon0_in: port@0 {
	227	#address-cells = <1>;
	228	#size-cells = <0>;
	229	reg = <0>;
	230
	231	tcon0_in_be0: endpoint@0 {
	232	reg = <0>;
	233	remote-endpoint = <&be0_out_tcon0>;
	234	};
	235	};
	236
	237	tcon0_out: port@1 {
	238	#address-cells = <1>;
	239	#size-cells = <0>;
	240	reg = <1>;
	241	};
	242	};
	243	};
	244
fbfa7367 MR	245	mmc0: mmc@01c0f000 {
	246	compatible = "allwinner,sun5i-a13-mmc";
	247	reg = <0x01c0f000 0x1000>;
98a59a0f MR	248	clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
98a59a0f MR	249	clock-names = "ahb", "mmc";
fbfa7367 MR	250	interrupts = <32>;
fbfa7367 MR	251	status = "disabled";
4c1bb9c3 HG	252	#address-cells = <1>;
4c1bb9c3 HG	253	#size-cells = <0>;
fbfa7367 MR	254	};
	255
	256	mmc1: mmc@01c10000 {
	257	compatible = "allwinner,sun5i-a13-mmc";
	258	reg = <0x01c10000 0x1000>;
98a59a0f MR	259	clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
98a59a0f MR	260	clock-names = "ahb", "mmc";
fbfa7367 MR	261	interrupts = <33>;
fbfa7367 MR	262	status = "disabled";
4c1bb9c3 HG	263	#address-cells = <1>;
4c1bb9c3 HG	264	#size-cells = <0>;
fbfa7367 MR	265	};
	266
	267	mmc2: mmc@01c11000 {
	268	compatible = "allwinner,sun5i-a13-mmc";
	269	reg = <0x01c11000 0x1000>;
98a59a0f MR	270	clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
98a59a0f MR	271	clock-names = "ahb", "mmc";
fbfa7367 MR	272	interrupts = <34>;
fbfa7367 MR	273	status = "disabled";
4c1bb9c3 HG	274	#address-cells = <1>;
4c1bb9c3 HG	275	#size-cells = <0>;
fbfa7367 MR	276	};
fbfa7367 MR	277
482f178c HG	278	usb_otg: usb@01c13000 {
	279	compatible = "allwinner,sun4i-a10-musb";
	280	reg = <0x01c13000 0x0400>;
98a59a0f	281	clocks = <&ccu CLK_AHB_OTG>;
482f178c HG	282	interrupts = <38>;
	283	interrupt-names = "mc";
	284	phys = <&usbphy 0>;
	285	phy-names = "usb";
	286	extcon = <&usbphy 0>;
	287	allwinner,sram = <&otg_sram 1>;
	288	status = "disabled";
	289	};
	290
fbfa7367 MR	291	usbphy: phy@01c13400 {
	292	#phy-cells = <1>;
	293	compatible = "allwinner,sun5i-a13-usb-phy";
	294	reg = <0x01c13400 0x10 0x01c14800 0x4>;
	295	reg-names = "phy_ctrl", "pmu1";
98a59a0f	296	clocks = <&ccu CLK_USB_PHY0>;
fbfa7367	297	clock-names = "usb_phy";
98a59a0f	298	resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
fbfa7367 MR	299	reset-names = "usb0_reset", "usb1_reset";
	300	status = "disabled";
	301	};
	302
	303	ehci0: usb@01c14000 {
3727ed3b	304	compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
fbfa7367 MR	305	reg = <0x01c14000 0x100>;
fbfa7367 MR	306	interrupts = <39>;
98a59a0f	307	clocks = <&ccu CLK_AHB_EHCI>;
fbfa7367 MR	308	phys = <&usbphy 1>;
	309	phy-names = "usb";
	310	status = "disabled";
	311	};
	312
	313	ohci0: usb@01c14400 {
3727ed3b	314	compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
fbfa7367 MR	315	reg = <0x01c14400 0x100>;
fbfa7367 MR	316	interrupts = <40>;
98a59a0f	317	clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
fbfa7367 MR	318	phys = <&usbphy 1>;
	319	phy-names = "usb";
	320	status = "disabled";
	321	};
	322
	323	spi2: spi@01c17000 {
	324	compatible = "allwinner,sun4i-a10-spi";
	325	reg = <0x01c17000 0x1000>;
	326	interrupts = <12>;
98a59a0f	327	clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
fbfa7367 MR	328	clock-names = "ahb", "mod";
	329	dmas = <&dma SUN4I_DMA_DEDICATED 29>,
	330	<&dma SUN4I_DMA_DEDICATED 28>;
	331	dma-names = "rx", "tx";
	332	status = "disabled";
	333	#address-cells = <1>;
	334	#size-cells = <0>;
	335	};
	336
98a59a0f MR	337	ccu: clock@01c20000 {
	338	reg = <0x01c20000 0x400>;
	339	clocks = <&osc24M>, <&osc32k>;
	340	clock-names = "hosc", "losc";
	341	#clock-cells = <1>;
	342	#reset-cells = <1>;
	343	};
	344
fbfa7367 MR	345	intc: interrupt-controller@01c20400 {
	346	compatible = "allwinner,sun4i-a10-ic";
	347	reg = <0x01c20400 0x400>;
	348	interrupt-controller;
	349	#interrupt-cells = <1>;
	350	};
	351
	352	pio: pinctrl@01c20800 {
	353	reg = <0x01c20800 0x400>;
	354	interrupts = <28>;
98a59a0f	355	clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
be7bc6b9	356	clock-names = "apb", "hosc", "losc";
fbfa7367 MR	357	gpio-controller;
fbfa7367 MR	358	interrupt-controller;
b03e0816	359	#interrupt-cells = <3>;
fbfa7367	360	#gpio-cells = <3>;
51fbba42	361
78f6d982 MR	362	emac_pins_a: emac0@0 {
	363	pins = "PD6", "PD7", "PD10",
	364	"PD11", "PD12", "PD13", "PD14",
	365	"PD15", "PD18", "PD19", "PD20",
	366	"PD21", "PD22", "PD23", "PD24",
	367	"PD25", "PD26", "PD27";
	368	function = "emac";
	369	};
	370
51fbba42	371	i2c0_pins_a: i2c0@0 {
1edcd36f MR	372	pins = "PB0", "PB1";
1edcd36f MR	373	function = "i2c0";
51fbba42 MR	374	};
	375
	376	i2c1_pins_a: i2c1@0 {
1edcd36f MR	377	pins = "PB15", "PB16";
1edcd36f MR	378	function = "i2c1";
51fbba42 MR	379	};
	380
	381	i2c2_pins_a: i2c2@0 {
1edcd36f MR	382	pins = "PB17", "PB18";
1edcd36f MR	383	function = "i2c2";
51fbba42 MR	384	};
51fbba42 MR	385
60a47e43	386	lcd_rgb565_pins: lcd_rgb565@0 {
1edcd36f	387	pins = "PD3", "PD4", "PD5", "PD6", "PD7",
60a47e43 MR	388	"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
	389	"PD19", "PD20", "PD21", "PD22", "PD23",
	390	"PD24", "PD25", "PD26", "PD27";
1edcd36f	391	function = "lcd0";
60a47e43 MR	392	};
60a47e43 MR	393
85870196 MR	394	lcd_rgb666_pins: lcd_rgb666@0 {
	395	pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
	396	"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
	397	"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
	398	"PD24", "PD25", "PD26", "PD27";
	399	function = "lcd0";
	400	};
	401
51fbba42	402	mmc0_pins_a: mmc0@0 {
1edcd36f MR	403	pins = "PF0", "PF1", "PF2", "PF3",
	404	"PF4", "PF5";
	405	function = "mmc0";
	406	drive-strength = <30>;
80ee72e7	407	bias-pull-up;
51fbba42	408	};
e1fe9f8c HG	409
e1fe9f8c HG	410	mmc2_pins_a: mmc2@0 {
1edcd36f MR	411	pins = "PC6", "PC7", "PC8", "PC9",
	412	"PC10", "PC11", "PC12", "PC13",
	413	"PC14", "PC15";
	414	function = "mmc2";
	415	drive-strength = <30>;
	416	bias-pull-up;
e1fe9f8c	417	};
6ef8c8bf	418
e6c5bfea IZ	419	mmc2_4bit_pins_a: mmc2-4bit@0 {
	420	pins = "PC6", "PC7", "PC8", "PC9",
	421	"PC10", "PC11";
	422	function = "mmc2";
	423	drive-strength = <30>;
	424	bias-pull-up;
	425	};
	426
9255fb6c	427	spi2_pins_a: spi2@0 {
1edcd36f MR	428	pins = "PE1", "PE2", "PE3";
1edcd36f MR	429	function = "spi2";
9255fb6c MR	430	};
	431
	432	spi2_cs0_pins_a: spi2-cs0@0 {
1edcd36f MR	433	pins = "PE0";
1edcd36f MR	434	function = "spi2";
9255fb6c MR	435	};
9255fb6c MR	436
85870196 MR	437	uart1_pins_a: uart1@0 {
	438	pins = "PE10", "PE11";
	439	function = "uart1";
	440	};
	441
	442	uart1_pins_b: uart1@1 {
	443	pins = "PG3", "PG4";
	444	function = "uart1";
	445	};
	446
bab86b94 MR	447	uart2_pins_a: uart2@0 {
	448	pins = "PD2", "PD3";
	449	function = "uart2";
	450	};
	451
	452	uart2_cts_rts_pins_a: uart2-cts-rts@0 {
	453	pins = "PD4", "PD5";
	454	function = "uart2";
	455	};
	456
6ef8c8bf	457	uart3_pins_a: uart3@0 {
1edcd36f MR	458	pins = "PG9", "PG10";
1edcd36f MR	459	function = "uart3";
eeea0fa3 MR	460	};
eeea0fa3 MR	461
e6f50b22	462	uart3_cts_rts_pins_a: uart3-cts-rts@0 {
1edcd36f MR	463	pins = "PG11", "PG12";
1edcd36f MR	464	function = "uart3";
6ef8c8bf	465	};
bb390193 HG	466
bb390193 HG	467	pwm0_pins: pwm0 {
1edcd36f MR	468	pins = "PB2";
1edcd36f MR	469	function = "pwm";
bb390193	470	};
fbfa7367 MR	471	};
	472
	473	timer@01c20c00 {
	474	compatible = "allwinner,sun4i-a10-timer";
	475	reg = <0x01c20c00 0x90>;
	476	interrupts = <22>;
98a59a0f	477	clocks = <&ccu CLK_HOSC>;
fbfa7367 MR	478	};
	479
	480	wdt: watchdog@01c20c90 {
	481	compatible = "allwinner,sun4i-a10-wdt";
	482	reg = <0x01c20c90 0x10>;
	483	};
	484
	485	lradc: lradc@01c22800 {
	486	compatible = "allwinner,sun4i-a10-lradc-keys";
	487	reg = <0x01c22800 0x100>;
	488	interrupts = <31>;
	489	status = "disabled";
	490	};
	491
44cdcfc2 MR	492	codec: codec@01c22c00 {
	493	#sound-dai-cells = <0>;
	494	compatible = "allwinner,sun4i-a10-codec";
	495	reg = <0x01c22c00 0x40>;
	496	interrupts = <30>;
98a59a0f	497	clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
44cdcfc2 MR	498	clock-names = "apb", "codec";
	499	dmas = <&dma SUN4I_DMA_NORMAL 19>,
	500	<&dma SUN4I_DMA_NORMAL 19>;
	501	dma-names = "rx", "tx";
	502	status = "disabled";
	503	};
	504
fbfa7367 MR	505	sid: eeprom@01c23800 {
	506	compatible = "allwinner,sun4i-a10-sid";
	507	reg = <0x01c23800 0x10>;
	508	};
	509
	510	rtp: rtp@01c25000 {
8bf1b9b3	511	compatible = "allwinner,sun5i-a13-ts";
fbfa7367 MR	512	reg = <0x01c25000 0x100>;
	513	interrupts = <29>;
	514	#thermal-sensor-cells = <0>;
	515	};
	516
78f6d982 MR	517	uart0: serial@01c28000 {
	518	compatible = "snps,dw-apb-uart";
	519	reg = <0x01c28000 0x400>;
	520	interrupts = <1>;
	521	reg-shift = <2>;
	522	reg-io-width = <4>;
	523	clocks = <&ccu CLK_APB1_UART0>;
	524	status = "disabled";
	525	};
	526
fbfa7367 MR	527	uart1: serial@01c28400 {
	528	compatible = "snps,dw-apb-uart";
	529	reg = <0x01c28400 0x400>;
	530	interrupts = <2>;
	531	reg-shift = <2>;
	532	reg-io-width = <4>;
98a59a0f	533	clocks = <&ccu CLK_APB1_UART1>;
fbfa7367 MR	534	status = "disabled";
	535	};
	536
78f6d982 MR	537	uart2: serial@01c28800 {
	538	compatible = "snps,dw-apb-uart";
	539	reg = <0x01c28800 0x400>;
	540	interrupts = <3>;
	541	reg-shift = <2>;
	542	reg-io-width = <4>;
	543	clocks = <&ccu CLK_APB1_UART2>;
	544	status = "disabled";
	545	};
	546
fbfa7367 MR	547	uart3: serial@01c28c00 {
	548	compatible = "snps,dw-apb-uart";
	549	reg = <0x01c28c00 0x400>;
	550	interrupts = <4>;
	551	reg-shift = <2>;
	552	reg-io-width = <4>;
98a59a0f	553	clocks = <&ccu CLK_APB1_UART3>;
fbfa7367 MR	554	status = "disabled";
	555	};
	556
	557	i2c0: i2c@01c2ac00 {
	558	compatible = "allwinner,sun4i-a10-i2c";
	559	reg = <0x01c2ac00 0x400>;
	560	interrupts = <7>;
98a59a0f	561	clocks = <&ccu CLK_APB1_I2C0>;
fbfa7367 MR	562	status = "disabled";
	563	#address-cells = <1>;
	564	#size-cells = <0>;
	565	};
	566
	567	i2c1: i2c@01c2b000 {
	568	compatible = "allwinner,sun4i-a10-i2c";
	569	reg = <0x01c2b000 0x400>;
	570	interrupts = <8>;
98a59a0f	571	clocks = <&ccu CLK_APB1_I2C1>;
fbfa7367 MR	572	status = "disabled";
	573	#address-cells = <1>;
	574	#size-cells = <0>;
	575	};
	576
	577	i2c2: i2c@01c2b400 {
	578	compatible = "allwinner,sun4i-a10-i2c";
	579	reg = <0x01c2b400 0x400>;
	580	interrupts = <9>;
98a59a0f	581	clocks = <&ccu CLK_APB1_I2C2>;
fbfa7367 MR	582	status = "disabled";
	583	#address-cells = <1>;
	584	#size-cells = <0>;
	585	};
	586
	587	timer@01c60000 {
	588	compatible = "allwinner,sun5i-a13-hstimer";
	589	reg = <0x01c60000 0x1000>;
	590	interrupts = <82>, <83>;
98a59a0f	591	clocks = <&ccu CLK_AHB_HSTIMER>;
fbfa7367	592	};
85870196 MR	593
	594	fe0: display-frontend@01e00000 {
	595	compatible = "allwinner,sun5i-a13-display-frontend";
	596	reg = <0x01e00000 0x20000>;
	597	interrupts = <47>;
	598	clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
	599	<&ccu CLK_DRAM_DE_FE>;
	600	clock-names = "ahb", "mod",
	601	"ram";
	602	resets = <&ccu RST_DE_FE>;
	603	status = "disabled";
	604
	605	ports {
	606	#address-cells = <1>;
	607	#size-cells = <0>;
	608
	609	fe0_out: port@1 {
	610	#address-cells = <1>;
	611	#size-cells = <0>;
	612	reg = <1>;
	613
	614	fe0_out_be0: endpoint@0 {
	615	reg = <0>;
	616	remote-endpoint = <&be0_in_fe0>;
	617	};
	618	};
	619	};
	620	};
	621
	622	be0: display-backend@01e60000 {
	623	compatible = "allwinner,sun5i-a13-display-backend";
	624	reg = <0x01e60000 0x10000>;
	625	clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
	626	<&ccu CLK_DRAM_DE_BE>;
	627	clock-names = "ahb", "mod",
	628	"ram";
	629	resets = <&ccu RST_DE_BE>;
	630	status = "disabled";
	631
	632	assigned-clocks = <&ccu CLK_DE_BE>;
	633	assigned-clock-rates = <300000000>;
	634
	635	ports {
	636	#address-cells = <1>;
	637	#size-cells = <0>;
	638
	639	be0_in: port@0 {
	640	#address-cells = <1>;
	641	#size-cells = <0>;
	642	reg = <0>;
	643
	644	be0_in_fe0: endpoint@0 {
	645	reg = <0>;
	646	remote-endpoint = <&fe0_out_be0>;
	647	};
	648	};
	649
	650	be0_out: port@1 {
	651	#address-cells = <1>;
	652	#size-cells = <0>;
	653	reg = <1>;
	654
	655	be0_out_tcon0: endpoint@0 {
	656	reg = <0>;
657	remote-endpoint = <&tcon0_in_be0>;
658	};
659	};
660	};
661	};
fbfa7367 MR	662	};
fbfa7367 MR	663	};