]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blame - arch/arm/boot/dts/sun5i.dtsi
projects / mirror_ubuntu-eoan-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: dts: add vendor prefix for cubietech
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / sun5i.dtsi
CommitLineData
fbfa7367
MR		 1/*
2 * Copyright 2012-2015 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this library; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50#include "skeleton.dtsi"
51
52#include <dt-bindings/dma/sun4i-a10.h>
53#include <dt-bindings/pinctrl/sun4i-a10.h>
54
55/ {
56 interrupt-parent = <&intc>;
57
58 cpus {
59 #address-cells = <1>;
60 #size-cells = <0>;
61
62 cpu0: cpu@0 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a8";
65 reg = <0x0>;
66 clocks = <&cpu>;
67 };
68 };
69
70 clocks {
71 #address-cells = <1>;
72 #size-cells = <1>;
73 ranges;
74
75 /*
76 * This is a dummy clock, to be used as placeholder on
77 * other mux clocks when a specific parent clock is not
78 * yet implemented. It should be dropped when the driver
79 * is complete.
80 */
81 dummy: dummy {
82 #clock-cells = <0>;
83 compatible = "fixed-clock";
84 clock-frequency = <0>;
85 };
86
87 osc24M: clk@01c20050 {
88 #clock-cells = <0>;
89 compatible = "allwinner,sun4i-a10-osc-clk";
90 reg = <0x01c20050 0x4>;
91 clock-frequency = <24000000>;
92 clock-output-names = "osc24M";
93 };
94
95 osc32k: clk@0 {
96 #clock-cells = <0>;
97 compatible = "fixed-clock";
98 clock-frequency = <32768>;
99 clock-output-names = "osc32k";
100 };
101
102 pll1: clk@01c20000 {
103 #clock-cells = <0>;
104 compatible = "allwinner,sun4i-a10-pll1-clk";
105 reg = <0x01c20000 0x4>;
106 clocks = <&osc24M>;
107 clock-output-names = "pll1";
108 };
109
110 pll4: clk@01c20018 {
111 #clock-cells = <0>;
112 compatible = "allwinner,sun4i-a10-pll1-clk";
113 reg = <0x01c20018 0x4>;
114 clocks = <&osc24M>;
115 clock-output-names = "pll4";
116 };
117
118 pll5: clk@01c20020 {
119 #clock-cells = <1>;
120 compatible = "allwinner,sun4i-a10-pll5-clk";
121 reg = <0x01c20020 0x4>;
122 clocks = <&osc24M>;
123 clock-output-names = "pll5_ddr", "pll5_other";
124 };
125
126 pll6: clk@01c20028 {
127 #clock-cells = <1>;
128 compatible = "allwinner,sun4i-a10-pll6-clk";
129 reg = <0x01c20028 0x4>;
130 clocks = <&osc24M>;
131 clock-output-names = "pll6_sata", "pll6_other", "pll6";
132 };
133
134 /* dummy is 200M */
135 cpu: cpu@01c20054 {
136 #clock-cells = <0>;
137 compatible = "allwinner,sun4i-a10-cpu-clk";
138 reg = <0x01c20054 0x4>;
139 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
140 clock-output-names = "cpu";
141 };
142
143 axi: axi@01c20054 {
144 #clock-cells = <0>;
145 compatible = "allwinner,sun4i-a10-axi-clk";
146 reg = <0x01c20054 0x4>;
147 clocks = <&cpu>;
148 clock-output-names = "axi";
149 };
150
151 ahb: ahb@01c20054 {
152 #clock-cells = <0>;
153 compatible = "allwinner,sun4i-a10-ahb-clk";
154 reg = <0x01c20054 0x4>;
155 clocks = <&axi>;
156 clock-output-names = "ahb";
157 };
158
159 apb0: apb0@01c20054 {
160 #clock-cells = <0>;
161 compatible = "allwinner,sun4i-a10-apb0-clk";
162 reg = <0x01c20054 0x4>;
163 clocks = <&ahb>;
164 clock-output-names = "apb0";
165 };
166
167 apb1: clk@01c20058 {
168 #clock-cells = <0>;
169 compatible = "allwinner,sun4i-a10-apb1-clk";
170 reg = <0x01c20058 0x4>;
171 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
172 clock-output-names = "apb1";
173 };
174
175 axi_gates: clk@01c2005c {
176 #clock-cells = <1>;
177 compatible = "allwinner,sun4i-a10-axi-gates-clk";
178 reg = <0x01c2005c 0x4>;
179 clocks = <&axi>;
180 clock-output-names = "axi_dram";
181 };
182
183 nand_clk: clk@01c20080 {
184 #clock-cells = <0>;
185 compatible = "allwinner,sun4i-a10-mod0-clk";
186 reg = <0x01c20080 0x4>;
187 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
188 clock-output-names = "nand";
189 };
190
191 ms_clk: clk@01c20084 {
192 #clock-cells = <0>;
193 compatible = "allwinner,sun4i-a10-mod0-clk";
194 reg = <0x01c20084 0x4>;
195 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
196 clock-output-names = "ms";
197 };
198
199 mmc0_clk: clk@01c20088 {
200 #clock-cells = <1>;
201 compatible = "allwinner,sun4i-a10-mmc-clk";
202 reg = <0x01c20088 0x4>;
203 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
204 clock-output-names = "mmc0",
205 "mmc0_output",
206 "mmc0_sample";
207 };
208
209 mmc1_clk: clk@01c2008c {
210 #clock-cells = <1>;
211 compatible = "allwinner,sun4i-a10-mmc-clk";
212 reg = <0x01c2008c 0x4>;
213 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
214 clock-output-names = "mmc1",
215 "mmc1_output",
216 "mmc1_sample";
217 };
218
219 mmc2_clk: clk@01c20090 {
220 #clock-cells = <1>;
221 compatible = "allwinner,sun4i-a10-mmc-clk";
222 reg = <0x01c20090 0x4>;
223 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
224 clock-output-names = "mmc2",
225 "mmc2_output",
226 "mmc2_sample";
227 };
228
229 ts_clk: clk@01c20098 {
230 #clock-cells = <0>;
231 compatible = "allwinner,sun4i-a10-mod0-clk";
232 reg = <0x01c20098 0x4>;
233 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
234 clock-output-names = "ts";
235 };
236
237 ss_clk: clk@01c2009c {
238 #clock-cells = <0>;
239 compatible = "allwinner,sun4i-a10-mod0-clk";
240 reg = <0x01c2009c 0x4>;
241 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
242 clock-output-names = "ss";
243 };
244
245 spi0_clk: clk@01c200a0 {
246 #clock-cells = <0>;
247 compatible = "allwinner,sun4i-a10-mod0-clk";
248 reg = <0x01c200a0 0x4>;
249 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
250 clock-output-names = "spi0";
251 };
252
253 spi1_clk: clk@01c200a4 {
254 #clock-cells = <0>;
255 compatible = "allwinner,sun4i-a10-mod0-clk";
256 reg = <0x01c200a4 0x4>;
257 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
258 clock-output-names = "spi1";
259 };
260
261 spi2_clk: clk@01c200a8 {
262 #clock-cells = <0>;
263 compatible = "allwinner,sun4i-a10-mod0-clk";
264 reg = <0x01c200a8 0x4>;
265 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
266 clock-output-names = "spi2";
267 };
268
269 ir0_clk: clk@01c200b0 {
270 #clock-cells = <0>;
271 compatible = "allwinner,sun4i-a10-mod0-clk";
272 reg = <0x01c200b0 0x4>;
273 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
274 clock-output-names = "ir0";
275 };
276
277 usb_clk: clk@01c200cc {
278 #clock-cells = <1>;
279 #reset-cells = <1>;
280 compatible = "allwinner,sun5i-a13-usb-clk";
281 reg = <0x01c200cc 0x4>;
282 clocks = <&pll6 1>;
283 clock-output-names = "usb_ohci0", "usb_phy";
284 };
285
286 mbus_clk: clk@01c2015c {
287 #clock-cells = <0>;
288 compatible = "allwinner,sun5i-a13-mbus-clk";
289 reg = <0x01c2015c 0x4>;
290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
291 clock-output-names = "mbus";
292 };
293 };
294
295 soc@01c00000 {
296 compatible = "simple-bus";
297 #address-cells = <1>;
298 #size-cells = <1>;
299 ranges;
300
301 dma: dma-controller@01c02000 {
302 compatible = "allwinner,sun4i-a10-dma";
303 reg = <0x01c02000 0x1000>;
304 interrupts = <27>;
305 clocks = <&ahb_gates 6>;
306 #dma-cells = <2>;
307 };
308
309 spi0: spi@01c05000 {
310 compatible = "allwinner,sun4i-a10-spi";
311 reg = <0x01c05000 0x1000>;
312 interrupts = <10>;
313 clocks = <&ahb_gates 20>, <&spi0_clk>;
314 clock-names = "ahb", "mod";
315 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
316 <&dma SUN4I_DMA_DEDICATED 26>;
317 dma-names = "rx", "tx";
318 status = "disabled";
319 #address-cells = <1>;
320 #size-cells = <0>;
321 };
322
323 spi1: spi@01c06000 {
324 compatible = "allwinner,sun4i-a10-spi";
325 reg = <0x01c06000 0x1000>;
326 interrupts = <11>;
327 clocks = <&ahb_gates 21>, <&spi1_clk>;
328 clock-names = "ahb", "mod";
329 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
330 <&dma SUN4I_DMA_DEDICATED 8>;
331 dma-names = "rx", "tx";
332 status = "disabled";
333 #address-cells = <1>;
334 #size-cells = <0>;
335 };
336
337 mmc0: mmc@01c0f000 {
338 compatible = "allwinner,sun5i-a13-mmc";
339 reg = <0x01c0f000 0x1000>;
340 clocks = <&ahb_gates 8>,
341 <&mmc0_clk 0>,
342 <&mmc0_clk 1>,
343 <&mmc0_clk 2>;
344 clock-names = "ahb",
345 "mmc",
346 "output",
347 "sample";
348 interrupts = <32>;
349 status = "disabled";
350 };
351
352 mmc1: mmc@01c10000 {
353 compatible = "allwinner,sun5i-a13-mmc";
354 reg = <0x01c10000 0x1000>;
355 clocks = <&ahb_gates 9>,
356 <&mmc1_clk 0>,
357 <&mmc1_clk 1>,
358 <&mmc1_clk 2>;
359 clock-names = "ahb",
360 "mmc",
361 "output",
362 "sample";
363 interrupts = <33>;
364 status = "disabled";
365 };
366
367 mmc2: mmc@01c11000 {
368 compatible = "allwinner,sun5i-a13-mmc";
369 reg = <0x01c11000 0x1000>;
370 clocks = <&ahb_gates 10>,
371 <&mmc2_clk 0>,
372 <&mmc2_clk 1>,
373 <&mmc2_clk 2>;
374 clock-names = "ahb",
375 "mmc",
376 "output",
377 "sample";
378 interrupts = <34>;
379 status = "disabled";
380 };
381
382 usbphy: phy@01c13400 {
383 #phy-cells = <1>;
384 compatible = "allwinner,sun5i-a13-usb-phy";
385 reg = <0x01c13400 0x10 0x01c14800 0x4>;
386 reg-names = "phy_ctrl", "pmu1";
387 clocks = <&usb_clk 8>;
388 clock-names = "usb_phy";
389 resets = <&usb_clk 0>, <&usb_clk 1>;
390 reset-names = "usb0_reset", "usb1_reset";
391 status = "disabled";
392 };
393
394 ehci0: usb@01c14000 {
3727ed3b 395 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
fbfa7367
MR		 396 reg = <0x01c14000 0x100>;
397 interrupts = <39>;
398 clocks = <&ahb_gates 1>;
399 phys = <&usbphy 1>;
400 phy-names = "usb";
401 status = "disabled";
402 };
403
404 ohci0: usb@01c14400 {
3727ed3b 405 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
fbfa7367
MR		 406 reg = <0x01c14400 0x100>;
407 interrupts = <40>;
408 clocks = <&usb_clk 6>, <&ahb_gates 2>;
409 phys = <&usbphy 1>;
410 phy-names = "usb";
411 status = "disabled";
412 };
413
414 spi2: spi@01c17000 {
415 compatible = "allwinner,sun4i-a10-spi";
416 reg = <0x01c17000 0x1000>;
417 interrupts = <12>;
418 clocks = <&ahb_gates 22>, <&spi2_clk>;
419 clock-names = "ahb", "mod";
420 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
421 <&dma SUN4I_DMA_DEDICATED 28>;
422 dma-names = "rx", "tx";
423 status = "disabled";
424 #address-cells = <1>;
425 #size-cells = <0>;
426 };
427
428 intc: interrupt-controller@01c20400 {
429 compatible = "allwinner,sun4i-a10-ic";
430 reg = <0x01c20400 0x400>;
431 interrupt-controller;
432 #interrupt-cells = <1>;
433 };
434
435 pio: pinctrl@01c20800 {
436 reg = <0x01c20800 0x400>;
437 interrupts = <28>;
438 clocks = <&apb0_gates 5>;
439 gpio-controller;
440 interrupt-controller;
441 #interrupt-cells = <2>;
442 #size-cells = <0>;
443 #gpio-cells = <3>;
51fbba42
MR		 444
445 i2c0_pins_a: i2c0@0 {
446 allwinner,pins = "PB0", "PB1";
447 allwinner,function = "i2c0";
448 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
449 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
450 };
451
452 i2c1_pins_a: i2c1@0 {
453 allwinner,pins = "PB15", "PB16";
454 allwinner,function = "i2c1";
455 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
456 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
457 };
458
459 i2c2_pins_a: i2c2@0 {
460 allwinner,pins = "PB17", "PB18";
461 allwinner,function = "i2c2";
462 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
463 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
464 };
465
466 mmc0_pins_a: mmc0@0 {
467 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
468 allwinner,function = "mmc0";
469 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
470 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
471 };
e1fe9f8c
HG		 472
473 mmc2_pins_a: mmc2@0 {
474 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
475 "PC10", "PC11", "PC12", "PC13",
476 "PC14", "PC15";
477 allwinner,function = "mmc2";
478 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
479 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
480 };
fbfa7367
MR		 481 };
482
483 timer@01c20c00 {
484 compatible = "allwinner,sun4i-a10-timer";
485 reg = <0x01c20c00 0x90>;
486 interrupts = <22>;
487 clocks = <&osc24M>;
488 };
489
490 wdt: watchdog@01c20c90 {
491 compatible = "allwinner,sun4i-a10-wdt";
492 reg = <0x01c20c90 0x10>;
493 };
494
495 lradc: lradc@01c22800 {
496 compatible = "allwinner,sun4i-a10-lradc-keys";
497 reg = <0x01c22800 0x100>;
498 interrupts = <31>;
499 status = "disabled";
500 };
501
502 sid: eeprom@01c23800 {
503 compatible = "allwinner,sun4i-a10-sid";
504 reg = <0x01c23800 0x10>;
505 };
506
507 rtp: rtp@01c25000 {
508 compatible = "allwinner,sun4i-a10-ts";
509 reg = <0x01c25000 0x100>;
510 interrupts = <29>;
511 #thermal-sensor-cells = <0>;
512 };
513
514 uart1: serial@01c28400 {
515 compatible = "snps,dw-apb-uart";
516 reg = <0x01c28400 0x400>;
517 interrupts = <2>;
518 reg-shift = <2>;
519 reg-io-width = <4>;
520 clocks = <&apb1_gates 17>;
521 status = "disabled";
522 };
523
524 uart3: serial@01c28c00 {
525 compatible = "snps,dw-apb-uart";
526 reg = <0x01c28c00 0x400>;
527 interrupts = <4>;
528 reg-shift = <2>;
529 reg-io-width = <4>;
530 clocks = <&apb1_gates 19>;
531 status = "disabled";
532 };
533
534 i2c0: i2c@01c2ac00 {
535 compatible = "allwinner,sun4i-a10-i2c";
536 reg = <0x01c2ac00 0x400>;
537 interrupts = <7>;
538 clocks = <&apb1_gates 0>;
539 status = "disabled";
540 #address-cells = <1>;
541 #size-cells = <0>;
542 };
543
544 i2c1: i2c@01c2b000 {
545 compatible = "allwinner,sun4i-a10-i2c";
546 reg = <0x01c2b000 0x400>;
547 interrupts = <8>;
548 clocks = <&apb1_gates 1>;
549 status = "disabled";
550 #address-cells = <1>;
551 #size-cells = <0>;
552 };
553
554 i2c2: i2c@01c2b400 {
555 compatible = "allwinner,sun4i-a10-i2c";
556 reg = <0x01c2b400 0x400>;
557 interrupts = <9>;
558 clocks = <&apb1_gates 2>;
559 status = "disabled";
560 #address-cells = <1>;
561 #size-cells = <0>;
562 };
563
564 timer@01c60000 {
565 compatible = "allwinner,sun5i-a13-hstimer";
566 reg = <0x01c60000 0x1000>;
567 interrupts = <82>, <83>;
568 clocks = <&ahb_gates 28>;
569 };
570 };
571};
Ubuntu Eoan Linux kernel mirror