projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 8aed3b31 MR |
1 | /* |
| 2 | * Copyright 2013 Maxime Ripard | |
| 3 | * | |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
| 5 | * | |
| 6 | * The code contained herein is licensed under the GNU General Public | |
| 7 | * License. You may obtain a copy of the GNU General Public License | |
| 8 | * Version 2 or later at the following locations: | |
| 9 | * | |
| 10 | * http://www.opensource.org/licenses/gpl-license.html | |
| 11 | * http://www.gnu.org/copyleft/gpl.html | |
| 12 | */ | |
| 13 | ||
| 14 | /include/ "skeleton.dtsi" | |
| 15 | ||
| 16 | / { | |
| 17 | interrupt-parent = <&gic>; | |
| 18 | ||
| 19 | cpus { | |
| 20 | #address-cells = <1>; | |
| 21 | #size-cells = <0>; | |
| 22 | ||
| 23 | cpu@0 { | |
| 24 | compatible = "arm,cortex-a7"; | |
| 25 | device_type = "cpu"; | |
| 26 | reg = <0>; | |
| 27 | }; | |
| 28 | ||
| 29 | cpu@1 { | |
| 30 | compatible = "arm,cortex-a7"; | |
| 31 | device_type = "cpu"; | |
| 32 | reg = <1>; | |
| 33 | }; | |
| 34 | ||
| 35 | cpu@2 { | |
| 36 | compatible = "arm,cortex-a7"; | |
| 37 | device_type = "cpu"; | |
| 38 | reg = <2>; | |
| 39 | }; | |
| 40 | ||
| 41 | cpu@3 { | |
| 42 | compatible = "arm,cortex-a7"; | |
| 43 | device_type = "cpu"; | |
| 44 | reg = <3>; | |
| 45 | }; | |
| 46 | }; | |
| 47 | ||
| 48 | memory { | |
| 49 | reg = <0x40000000 0x80000000>; | |
| 50 | }; | |
| 51 | ||
| 52 | clocks { | |
| 53 | #address-cells = <1>; | |
| 54 | #size-cells = <0>; | |
| 55 | ||
| 56 | osc: oscillator { | |
| 57 | #clock-cells = <0>; | |
| 58 | compatible = "fixed-clock"; | |
| 59 | clock-frequency = <24000000>; | |
| 60 | }; | |
| 61 | }; | |
| 62 | ||
| 63 | soc@01c00000 { | |
| 64 | compatible = "simple-bus"; | |
| 65 | #address-cells = <1>; | |
| 66 | #size-cells = <1>; | |
| 67 | ranges; | |
| 68 | ||
| 140e1721 MR |
69 | pio: pinctrl@01c20800 { |
| 70 | compatible = "allwinner,sun6i-a31-pinctrl"; | |
| 71 | reg = <0x01c20800 0x400>; | |
| 72 | interrupts = <0 11 1>, <0 15 1>, <0 16 1>, <0 17 1>; | |
| 73 | clocks = <&osc>; | |
| 74 | gpio-controller; | |
| 75 | interrupt-controller; | |
| 76 | #address-cells = <1>; | |
| 77 | #size-cells = <0>; | |
| 78 | #gpio-cells = <3>; | |
| ab4238cd MR |
79 | |
| 80 | uart0_pins_a: uart0@0 { | |
| 81 | allwinner,pins = "PH20", "PH21"; | |
| 82 | allwinner,function = "uart0"; | |
| 83 | allwinner,drive = <0>; | |
| 84 | allwinner,pull = <0>; | |
| 85 | }; | |
| 140e1721 MR |
86 | }; |
| 87 | ||
| 8aed3b31 MR |
88 | timer@01c20c00 { |
| 89 | compatible = "allwinner,sun4i-timer"; | |
| 90 | reg = <0x01c20c00 0xa0>; | |
| 91 | interrupts = <0 18 1>, | |
| 92 | <0 19 1>, | |
| 93 | <0 20 1>, | |
| 94 | <0 21 1>, | |
| 95 | <0 22 1>; | |
| 96 | clocks = <&osc>; | |
| 97 | }; | |
| 98 | ||
| 99 | wdt1: watchdog@01c20ca0 { | |
| 100 | compatible = "allwinner,sun6i-wdt"; | |
| 101 | reg = <0x01c20ca0 0x20>; | |
| 102 | }; | |
| 103 | ||
| 104 | uart0: serial@01c28000 { | |
| 105 | compatible = "snps,dw-apb-uart"; | |
| 106 | reg = <0x01c28000 0x400>; | |
| 107 | interrupts = <0 0 1>; | |
| 108 | reg-shift = <2>; | |
| 109 | reg-io-width = <4>; | |
| 110 | clocks = <&osc>; | |
| 111 | status = "disabled"; | |
| 112 | }; | |
| 113 | ||
| 114 | uart1: serial@01c28400 { | |
| 115 | compatible = "snps,dw-apb-uart"; | |
| 116 | reg = <0x01c28400 0x400>; | |
| 117 | interrupts = <0 1 1>; | |
| 118 | reg-shift = <2>; | |
| 119 | reg-io-width = <4>; | |
| 120 | clocks = <&osc>; | |
| 121 | status = "disabled"; | |
| 122 | }; | |
| 123 | ||
| 124 | uart2: serial@01c28800 { | |
| 125 | compatible = "snps,dw-apb-uart"; | |
| 126 | reg = <0x01c28800 0x400>; | |
| 127 | interrupts = <0 2 1>; | |
| 128 | reg-shift = <2>; | |
| 129 | reg-io-width = <4>; | |
| 130 | clocks = <&osc>; | |
| 131 | status = "disabled"; | |
| 132 | }; | |
| 133 | ||
| 134 | uart3: serial@01c28c00 { | |
| 135 | compatible = "snps,dw-apb-uart"; | |
| 136 | reg = <0x01c28c00 0x400>; | |
| 137 | interrupts = <0 3 1>; | |
| 138 | reg-shift = <2>; | |
| 139 | reg-io-width = <4>; | |
| 140 | clocks = <&osc>; | |
| 141 | status = "disabled"; | |
| 142 | }; | |
| 143 | ||
| 144 | uart4: serial@01c29000 { | |
| 145 | compatible = "snps,dw-apb-uart"; | |
| 146 | reg = <0x01c29000 0x400>; | |
| 147 | interrupts = <0 4 1>; | |
| 148 | reg-shift = <2>; | |
| 149 | reg-io-width = <4>; | |
| 150 | clocks = <&osc>; | |
| 151 | status = "disabled"; | |
| 152 | }; | |
| 153 | ||
| 154 | uart5: serial@01c29400 { | |
| 155 | compatible = "snps,dw-apb-uart"; | |
| 156 | reg = <0x01c29400 0x400>; | |
| 157 | interrupts = <0 5 1>; | |
| 158 | reg-shift = <2>; | |
| 159 | reg-io-width = <4>; | |
| 160 | clocks = <&osc>; | |
| 161 | status = "disabled"; | |
| 162 | }; | |
| 163 | ||
| 164 | gic: interrupt-controller@01c81000 { | |
| 165 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
| 166 | reg = <0x01c81000 0x1000>, | |
| 167 | <0x01c82000 0x1000>, | |
| 168 | <0x01c84000 0x2000>, | |
| 169 | <0x01c86000 0x2000>; | |
| 170 | interrupt-controller; | |
| 171 | #interrupt-cells = <3>; | |
| 172 | interrupts = <1 9 0xf04>; | |
| 173 | }; | |
| 174 | }; | |
| 175 | }; |