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8aed3b31 MR |
1 | /* |
2 | * Copyright 2013 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | * http://www.opensource.org/licenses/gpl-license.html | |
11 | * http://www.gnu.org/copyleft/gpl.html | |
12 | */ | |
13 | ||
14 | /include/ "skeleton.dtsi" | |
15 | ||
16 | / { | |
17 | interrupt-parent = <&gic>; | |
18 | ||
54428d40 MR |
19 | aliases { |
20 | serial0 = &uart0; | |
21 | serial1 = &uart1; | |
22 | serial2 = &uart2; | |
23 | serial3 = &uart3; | |
24 | serial4 = &uart4; | |
25 | serial5 = &uart5; | |
26 | }; | |
27 | ||
28 | ||
8aed3b31 MR |
29 | cpus { |
30 | #address-cells = <1>; | |
31 | #size-cells = <0>; | |
32 | ||
33 | cpu@0 { | |
34 | compatible = "arm,cortex-a7"; | |
35 | device_type = "cpu"; | |
36 | reg = <0>; | |
37 | }; | |
38 | ||
39 | cpu@1 { | |
40 | compatible = "arm,cortex-a7"; | |
41 | device_type = "cpu"; | |
42 | reg = <1>; | |
43 | }; | |
44 | ||
45 | cpu@2 { | |
46 | compatible = "arm,cortex-a7"; | |
47 | device_type = "cpu"; | |
48 | reg = <2>; | |
49 | }; | |
50 | ||
51 | cpu@3 { | |
52 | compatible = "arm,cortex-a7"; | |
53 | device_type = "cpu"; | |
54 | reg = <3>; | |
55 | }; | |
56 | }; | |
57 | ||
58 | memory { | |
59 | reg = <0x40000000 0x80000000>; | |
60 | }; | |
61 | ||
b5a10b76 MR |
62 | pmu { |
63 | compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; | |
64 | interrupts = <0 120 4>, | |
65 | <0 121 4>, | |
66 | <0 122 4>, | |
67 | <0 123 4>; | |
68 | }; | |
69 | ||
8aed3b31 MR |
70 | clocks { |
71 | #address-cells = <1>; | |
98096560 MR |
72 | #size-cells = <1>; |
73 | ranges; | |
8aed3b31 | 74 | |
98096560 | 75 | osc24M: osc24M { |
8aed3b31 MR |
76 | #clock-cells = <0>; |
77 | compatible = "fixed-clock"; | |
78 | clock-frequency = <24000000>; | |
79 | }; | |
98096560 | 80 | |
7b5b2909 | 81 | osc32k: clk@0 { |
98096560 MR |
82 | #clock-cells = <0>; |
83 | compatible = "fixed-clock"; | |
84 | clock-frequency = <32768>; | |
7b5b2909 | 85 | clock-output-names = "osc32k"; |
98096560 MR |
86 | }; |
87 | ||
7b5b2909 | 88 | pll1: clk@01c20000 { |
98096560 MR |
89 | #clock-cells = <0>; |
90 | compatible = "allwinner,sun6i-a31-pll1-clk"; | |
91 | reg = <0x01c20000 0x4>; | |
92 | clocks = <&osc24M>; | |
7b5b2909 | 93 | clock-output-names = "pll1"; |
98096560 MR |
94 | }; |
95 | ||
b0a09c75 | 96 | pll6: clk@01c20028 { |
98096560 | 97 | #clock-cells = <0>; |
b0a09c75 MR |
98 | compatible = "allwinner,sun6i-a31-pll6-clk"; |
99 | reg = <0x01c20028 0x4>; | |
100 | clocks = <&osc24M>; | |
101 | clock-output-names = "pll6"; | |
98096560 MR |
102 | }; |
103 | ||
104 | cpu: cpu@01c20050 { | |
105 | #clock-cells = <0>; | |
bf6534a1 | 106 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
98096560 MR |
107 | reg = <0x01c20050 0x4>; |
108 | ||
109 | /* | |
110 | * PLL1 is listed twice here. | |
111 | * While it looks suspicious, it's actually documented | |
112 | * that way both in the datasheet and in the code from | |
113 | * Allwinner. | |
114 | */ | |
115 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; | |
7b5b2909 | 116 | clock-output-names = "cpu"; |
98096560 MR |
117 | }; |
118 | ||
119 | axi: axi@01c20050 { | |
120 | #clock-cells = <0>; | |
bf6534a1 | 121 | compatible = "allwinner,sun4i-a10-axi-clk"; |
98096560 MR |
122 | reg = <0x01c20050 0x4>; |
123 | clocks = <&cpu>; | |
7b5b2909 | 124 | clock-output-names = "axi"; |
98096560 MR |
125 | }; |
126 | ||
127 | ahb1_mux: ahb1_mux@01c20054 { | |
128 | #clock-cells = <0>; | |
129 | compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; | |
130 | reg = <0x01c20054 0x4>; | |
131 | clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; | |
7b5b2909 | 132 | clock-output-names = "ahb1_mux"; |
98096560 MR |
133 | }; |
134 | ||
135 | ahb1: ahb1@01c20054 { | |
136 | #clock-cells = <0>; | |
bf6534a1 | 137 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
98096560 MR |
138 | reg = <0x01c20054 0x4>; |
139 | clocks = <&ahb1_mux>; | |
7b5b2909 | 140 | clock-output-names = "ahb1"; |
98096560 MR |
141 | }; |
142 | ||
7b5b2909 | 143 | ahb1_gates: clk@01c20060 { |
98096560 MR |
144 | #clock-cells = <1>; |
145 | compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; | |
146 | reg = <0x01c20060 0x8>; | |
147 | clocks = <&ahb1>; | |
148 | clock-output-names = "ahb1_mipidsi", "ahb1_ss", | |
149 | "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1", | |
150 | "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1", | |
151 | "ahb1_nand0", "ahb1_sdram", | |
152 | "ahb1_gmac", "ahb1_ts", "ahb1_hstimer", | |
153 | "ahb1_spi0", "ahb1_spi1", "ahb1_spi2", | |
154 | "ahb1_spi3", "ahb1_otg", "ahb1_ehci0", | |
155 | "ahb1_ehci1", "ahb1_ohci0", | |
156 | "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve", | |
157 | "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi", | |
158 | "ahb1_hdmi", "ahb1_de0", "ahb1_de1", | |
159 | "ahb1_fe0", "ahb1_fe1", "ahb1_mp", | |
160 | "ahb1_gpu", "ahb1_deu0", "ahb1_deu1", | |
161 | "ahb1_drc0", "ahb1_drc1"; | |
162 | }; | |
163 | ||
164 | apb1: apb1@01c20054 { | |
165 | #clock-cells = <0>; | |
bf6534a1 | 166 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
98096560 MR |
167 | reg = <0x01c20054 0x4>; |
168 | clocks = <&ahb1>; | |
7b5b2909 | 169 | clock-output-names = "apb1"; |
98096560 MR |
170 | }; |
171 | ||
7b5b2909 | 172 | apb1_gates: clk@01c20068 { |
98096560 MR |
173 | #clock-cells = <1>; |
174 | compatible = "allwinner,sun6i-a31-apb1-gates-clk"; | |
175 | reg = <0x01c20068 0x4>; | |
176 | clocks = <&apb1>; | |
177 | clock-output-names = "apb1_codec", "apb1_digital_mic", | |
178 | "apb1_pio", "apb1_daudio0", | |
179 | "apb1_daudio1"; | |
180 | }; | |
181 | ||
182 | apb2_mux: apb2_mux@01c20058 { | |
183 | #clock-cells = <0>; | |
bf6534a1 | 184 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
98096560 MR |
185 | reg = <0x01c20058 0x4>; |
186 | clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; | |
7b5b2909 | 187 | clock-output-names = "apb2_mux"; |
98096560 MR |
188 | }; |
189 | ||
190 | apb2: apb2@01c20058 { | |
191 | #clock-cells = <0>; | |
192 | compatible = "allwinner,sun6i-a31-apb2-div-clk"; | |
193 | reg = <0x01c20058 0x4>; | |
194 | clocks = <&apb2_mux>; | |
7b5b2909 | 195 | clock-output-names = "apb2"; |
98096560 MR |
196 | }; |
197 | ||
7b5b2909 | 198 | apb2_gates: clk@01c2006c { |
98096560 MR |
199 | #clock-cells = <1>; |
200 | compatible = "allwinner,sun6i-a31-apb2-gates-clk"; | |
439d9f58 | 201 | reg = <0x01c2006c 0x4>; |
98096560 MR |
202 | clocks = <&apb2>; |
203 | clock-output-names = "apb2_i2c0", "apb2_i2c1", | |
204 | "apb2_i2c2", "apb2_i2c3", "apb2_uart0", | |
205 | "apb2_uart1", "apb2_uart2", "apb2_uart3", | |
206 | "apb2_uart4", "apb2_uart5"; | |
207 | }; | |
b0a09c75 | 208 | |
adc54c85 HG |
209 | mmc0_clk: clk@01c20088 { |
210 | #clock-cells = <0>; | |
211 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
212 | reg = <0x01c20088 0x4>; | |
213 | clocks = <&osc24M>, <&pll6>; | |
214 | clock-output-names = "mmc0"; | |
215 | }; | |
216 | ||
217 | mmc1_clk: clk@01c2008c { | |
218 | #clock-cells = <0>; | |
219 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
220 | reg = <0x01c2008c 0x4>; | |
221 | clocks = <&osc24M>, <&pll6>; | |
222 | clock-output-names = "mmc1"; | |
223 | }; | |
224 | ||
225 | mmc2_clk: clk@01c20090 { | |
226 | #clock-cells = <0>; | |
227 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
228 | reg = <0x01c20090 0x4>; | |
229 | clocks = <&osc24M>, <&pll6>; | |
230 | clock-output-names = "mmc2"; | |
231 | }; | |
232 | ||
233 | mmc3_clk: clk@01c20094 { | |
234 | #clock-cells = <0>; | |
235 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
236 | reg = <0x01c20094 0x4>; | |
237 | clocks = <&osc24M>, <&pll6>; | |
238 | clock-output-names = "mmc3"; | |
239 | }; | |
240 | ||
b0a09c75 MR |
241 | spi0_clk: clk@01c200a0 { |
242 | #clock-cells = <0>; | |
225b0216 | 243 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
b0a09c75 MR |
244 | reg = <0x01c200a0 0x4>; |
245 | clocks = <&osc24M>, <&pll6>; | |
246 | clock-output-names = "spi0"; | |
247 | }; | |
248 | ||
249 | spi1_clk: clk@01c200a4 { | |
250 | #clock-cells = <0>; | |
225b0216 | 251 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
b0a09c75 MR |
252 | reg = <0x01c200a4 0x4>; |
253 | clocks = <&osc24M>, <&pll6>; | |
254 | clock-output-names = "spi1"; | |
255 | }; | |
256 | ||
257 | spi2_clk: clk@01c200a8 { | |
258 | #clock-cells = <0>; | |
225b0216 | 259 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
b0a09c75 MR |
260 | reg = <0x01c200a8 0x4>; |
261 | clocks = <&osc24M>, <&pll6>; | |
262 | clock-output-names = "spi2"; | |
263 | }; | |
264 | ||
265 | spi3_clk: clk@01c200ac { | |
266 | #clock-cells = <0>; | |
225b0216 | 267 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
b0a09c75 MR |
268 | reg = <0x01c200ac 0x4>; |
269 | clocks = <&osc24M>, <&pll6>; | |
270 | clock-output-names = "spi3"; | |
271 | }; | |
94a1cd14 MR |
272 | |
273 | usb_clk: clk@01c200cc { | |
274 | #clock-cells = <1>; | |
275 | #reset-cells = <1>; | |
276 | compatible = "allwinner,sun6i-a31-usb-clk"; | |
277 | reg = <0x01c200cc 0x4>; | |
278 | clocks = <&osc24M>; | |
279 | clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2", | |
280 | "usb_ohci0", "usb_ohci1", | |
281 | "usb_ohci2"; | |
282 | }; | |
8aed3b31 MR |
283 | }; |
284 | ||
285 | soc@01c00000 { | |
286 | compatible = "simple-bus"; | |
287 | #address-cells = <1>; | |
288 | #size-cells = <1>; | |
289 | ranges; | |
290 | ||
d2d878c4 MR |
291 | dma: dma-controller@01c02000 { |
292 | compatible = "allwinner,sun6i-a31-dma"; | |
293 | reg = <0x01c02000 0x1000>; | |
294 | interrupts = <0 50 4>; | |
295 | clocks = <&ahb1_gates 6>; | |
296 | resets = <&ahb1_rst 6>; | |
297 | #dma-cells = <1>; | |
298 | }; | |
299 | ||
5b753f0e HG |
300 | mmc0: mmc@01c0f000 { |
301 | compatible = "allwinner,sun5i-a13-mmc"; | |
302 | reg = <0x01c0f000 0x1000>; | |
303 | clocks = <&ahb1_gates 8>, <&mmc0_clk>; | |
304 | clock-names = "ahb", "mmc"; | |
305 | resets = <&ahb1_rst 8>; | |
306 | reset-names = "ahb"; | |
307 | interrupts = <0 60 4>; | |
308 | status = "disabled"; | |
309 | }; | |
310 | ||
311 | mmc1: mmc@01c10000 { | |
312 | compatible = "allwinner,sun5i-a13-mmc"; | |
313 | reg = <0x01c10000 0x1000>; | |
314 | clocks = <&ahb1_gates 9>, <&mmc1_clk>; | |
315 | clock-names = "ahb", "mmc"; | |
316 | resets = <&ahb1_rst 9>; | |
317 | reset-names = "ahb"; | |
318 | interrupts = <0 61 4>; | |
319 | status = "disabled"; | |
320 | }; | |
321 | ||
322 | mmc2: mmc@01c11000 { | |
323 | compatible = "allwinner,sun5i-a13-mmc"; | |
324 | reg = <0x01c11000 0x1000>; | |
325 | clocks = <&ahb1_gates 10>, <&mmc2_clk>; | |
326 | clock-names = "ahb", "mmc"; | |
327 | resets = <&ahb1_rst 10>; | |
328 | reset-names = "ahb"; | |
329 | interrupts = <0 62 4>; | |
330 | status = "disabled"; | |
331 | }; | |
332 | ||
333 | mmc3: mmc@01c12000 { | |
334 | compatible = "allwinner,sun5i-a13-mmc"; | |
335 | reg = <0x01c12000 0x1000>; | |
336 | clocks = <&ahb1_gates 11>, <&mmc3_clk>; | |
337 | clock-names = "ahb", "mmc"; | |
338 | resets = <&ahb1_rst 11>; | |
339 | reset-names = "ahb"; | |
340 | interrupts = <0 63 4>; | |
341 | status = "disabled"; | |
342 | }; | |
343 | ||
ef964085 MR |
344 | usbphy: phy@01c19400 { |
345 | compatible = "allwinner,sun6i-a31-usb-phy"; | |
346 | reg = <0x01c19400 0x10>, | |
347 | <0x01c1a800 0x4>, | |
348 | <0x01c1b800 0x4>; | |
349 | reg-names = "phy_ctrl", | |
350 | "pmu1", | |
351 | "pmu2"; | |
352 | clocks = <&usb_clk 8>, | |
353 | <&usb_clk 9>, | |
354 | <&usb_clk 10>; | |
355 | clock-names = "usb0_phy", | |
356 | "usb1_phy", | |
357 | "usb2_phy"; | |
358 | resets = <&usb_clk 0>, | |
359 | <&usb_clk 1>, | |
360 | <&usb_clk 2>; | |
361 | reset-names = "usb0_reset", | |
362 | "usb1_reset", | |
363 | "usb2_reset"; | |
364 | status = "disabled"; | |
365 | #phy-cells = <1>; | |
366 | }; | |
367 | ||
368 | ehci0: usb@01c1a000 { | |
369 | compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; | |
370 | reg = <0x01c1a000 0x100>; | |
371 | interrupts = <0 72 4>; | |
372 | clocks = <&ahb1_gates 26>; | |
373 | resets = <&ahb1_rst 26>; | |
374 | phys = <&usbphy 1>; | |
375 | phy-names = "usb"; | |
376 | status = "disabled"; | |
377 | }; | |
378 | ||
379 | ohci0: usb@01c1a400 { | |
380 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; | |
381 | reg = <0x01c1a400 0x100>; | |
382 | interrupts = <0 73 4>; | |
383 | clocks = <&ahb1_gates 29>, <&usb_clk 16>; | |
384 | resets = <&ahb1_rst 29>; | |
385 | phys = <&usbphy 1>; | |
386 | phy-names = "usb"; | |
387 | status = "disabled"; | |
388 | }; | |
389 | ||
390 | ehci1: usb@01c1b000 { | |
391 | compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; | |
392 | reg = <0x01c1b000 0x100>; | |
393 | interrupts = <0 74 4>; | |
394 | clocks = <&ahb1_gates 27>; | |
395 | resets = <&ahb1_rst 27>; | |
396 | phys = <&usbphy 2>; | |
397 | phy-names = "usb"; | |
398 | status = "disabled"; | |
399 | }; | |
400 | ||
401 | ohci1: usb@01c1b400 { | |
402 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; | |
403 | reg = <0x01c1b400 0x100>; | |
404 | interrupts = <0 75 4>; | |
405 | clocks = <&ahb1_gates 30>, <&usb_clk 17>; | |
406 | resets = <&ahb1_rst 30>; | |
407 | phys = <&usbphy 2>; | |
408 | phy-names = "usb"; | |
409 | status = "disabled"; | |
410 | }; | |
411 | ||
412 | ohci2: usb@01c1c000 { | |
413 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; | |
414 | reg = <0x01c1c400 0x100>; | |
415 | interrupts = <0 77 4>; | |
416 | clocks = <&ahb1_gates 31>, <&usb_clk 18>; | |
417 | resets = <&ahb1_rst 31>; | |
418 | status = "disabled"; | |
419 | }; | |
420 | ||
140e1721 MR |
421 | pio: pinctrl@01c20800 { |
422 | compatible = "allwinner,sun6i-a31-pinctrl"; | |
423 | reg = <0x01c20800 0x400>; | |
6f97dc8d MR |
424 | interrupts = <0 11 4>, |
425 | <0 15 4>, | |
426 | <0 16 4>, | |
427 | <0 17 4>; | |
98096560 | 428 | clocks = <&apb1_gates 5>; |
140e1721 MR |
429 | gpio-controller; |
430 | interrupt-controller; | |
431 | #address-cells = <1>; | |
432 | #size-cells = <0>; | |
433 | #gpio-cells = <3>; | |
ab4238cd MR |
434 | |
435 | uart0_pins_a: uart0@0 { | |
436 | allwinner,pins = "PH20", "PH21"; | |
437 | allwinner,function = "uart0"; | |
438 | allwinner,drive = <0>; | |
439 | allwinner,pull = <0>; | |
440 | }; | |
8be188b8 MR |
441 | |
442 | i2c0_pins_a: i2c0@0 { | |
443 | allwinner,pins = "PH14", "PH15"; | |
444 | allwinner,function = "i2c0"; | |
445 | allwinner,drive = <0>; | |
446 | allwinner,pull = <0>; | |
447 | }; | |
448 | ||
449 | i2c1_pins_a: i2c1@0 { | |
450 | allwinner,pins = "PH16", "PH17"; | |
451 | allwinner,function = "i2c1"; | |
452 | allwinner,drive = <0>; | |
453 | allwinner,pull = <0>; | |
454 | }; | |
455 | ||
456 | i2c2_pins_a: i2c2@0 { | |
457 | allwinner,pins = "PH18", "PH19"; | |
458 | allwinner,function = "i2c2"; | |
459 | allwinner,drive = <0>; | |
460 | allwinner,pull = <0>; | |
461 | }; | |
9797eb83 HG |
462 | |
463 | mmc0_pins_a: mmc0@0 { | |
464 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | |
465 | allwinner,function = "mmc0"; | |
466 | allwinner,drive = <2>; | |
467 | allwinner,pull = <0>; | |
468 | }; | |
140e1721 MR |
469 | }; |
470 | ||
24a661e9 MR |
471 | ahb1_rst: reset@01c202c0 { |
472 | #reset-cells = <1>; | |
473 | compatible = "allwinner,sun6i-a31-ahb1-reset"; | |
474 | reg = <0x01c202c0 0xc>; | |
475 | }; | |
476 | ||
477 | apb1_rst: reset@01c202d0 { | |
478 | #reset-cells = <1>; | |
479 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
480 | reg = <0x01c202d0 0x4>; | |
481 | }; | |
482 | ||
483 | apb2_rst: reset@01c202d8 { | |
484 | #reset-cells = <1>; | |
485 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
486 | reg = <0x01c202d8 0x4>; | |
487 | }; | |
488 | ||
8aed3b31 | 489 | timer@01c20c00 { |
b4f26440 | 490 | compatible = "allwinner,sun4i-a10-timer"; |
8aed3b31 | 491 | reg = <0x01c20c00 0xa0>; |
6f97dc8d MR |
492 | interrupts = <0 18 4>, |
493 | <0 19 4>, | |
494 | <0 20 4>, | |
495 | <0 21 4>, | |
496 | <0 22 4>; | |
98096560 | 497 | clocks = <&osc24M>; |
8aed3b31 MR |
498 | }; |
499 | ||
500 | wdt1: watchdog@01c20ca0 { | |
ca5d04d9 | 501 | compatible = "allwinner,sun6i-a31-wdt"; |
8aed3b31 MR |
502 | reg = <0x01c20ca0 0x20>; |
503 | }; | |
504 | ||
505 | uart0: serial@01c28000 { | |
506 | compatible = "snps,dw-apb-uart"; | |
507 | reg = <0x01c28000 0x400>; | |
6f97dc8d | 508 | interrupts = <0 0 4>; |
8aed3b31 MR |
509 | reg-shift = <2>; |
510 | reg-io-width = <4>; | |
98096560 | 511 | clocks = <&apb2_gates 16>; |
24a661e9 | 512 | resets = <&apb2_rst 16>; |
d2d878c4 MR |
513 | dmas = <&dma 6>, <&dma 6>; |
514 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
515 | status = "disabled"; |
516 | }; | |
517 | ||
518 | uart1: serial@01c28400 { | |
519 | compatible = "snps,dw-apb-uart"; | |
520 | reg = <0x01c28400 0x400>; | |
6f97dc8d | 521 | interrupts = <0 1 4>; |
8aed3b31 MR |
522 | reg-shift = <2>; |
523 | reg-io-width = <4>; | |
98096560 | 524 | clocks = <&apb2_gates 17>; |
24a661e9 | 525 | resets = <&apb2_rst 17>; |
d2d878c4 MR |
526 | dmas = <&dma 7>, <&dma 7>; |
527 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
528 | status = "disabled"; |
529 | }; | |
530 | ||
531 | uart2: serial@01c28800 { | |
532 | compatible = "snps,dw-apb-uart"; | |
533 | reg = <0x01c28800 0x400>; | |
6f97dc8d | 534 | interrupts = <0 2 4>; |
8aed3b31 MR |
535 | reg-shift = <2>; |
536 | reg-io-width = <4>; | |
98096560 | 537 | clocks = <&apb2_gates 18>; |
24a661e9 | 538 | resets = <&apb2_rst 18>; |
d2d878c4 MR |
539 | dmas = <&dma 8>, <&dma 8>; |
540 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
541 | status = "disabled"; |
542 | }; | |
543 | ||
544 | uart3: serial@01c28c00 { | |
545 | compatible = "snps,dw-apb-uart"; | |
546 | reg = <0x01c28c00 0x400>; | |
6f97dc8d | 547 | interrupts = <0 3 4>; |
8aed3b31 MR |
548 | reg-shift = <2>; |
549 | reg-io-width = <4>; | |
98096560 | 550 | clocks = <&apb2_gates 19>; |
24a661e9 | 551 | resets = <&apb2_rst 19>; |
d2d878c4 MR |
552 | dmas = <&dma 9>, <&dma 9>; |
553 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
554 | status = "disabled"; |
555 | }; | |
556 | ||
557 | uart4: serial@01c29000 { | |
558 | compatible = "snps,dw-apb-uart"; | |
559 | reg = <0x01c29000 0x400>; | |
6f97dc8d | 560 | interrupts = <0 4 4>; |
8aed3b31 MR |
561 | reg-shift = <2>; |
562 | reg-io-width = <4>; | |
98096560 | 563 | clocks = <&apb2_gates 20>; |
24a661e9 | 564 | resets = <&apb2_rst 20>; |
d2d878c4 MR |
565 | dmas = <&dma 10>, <&dma 10>; |
566 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
567 | status = "disabled"; |
568 | }; | |
569 | ||
570 | uart5: serial@01c29400 { | |
571 | compatible = "snps,dw-apb-uart"; | |
572 | reg = <0x01c29400 0x400>; | |
6f97dc8d | 573 | interrupts = <0 5 4>; |
8aed3b31 MR |
574 | reg-shift = <2>; |
575 | reg-io-width = <4>; | |
98096560 | 576 | clocks = <&apb2_gates 21>; |
24a661e9 | 577 | resets = <&apb2_rst 21>; |
d2d878c4 MR |
578 | dmas = <&dma 22>, <&dma 22>; |
579 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
580 | status = "disabled"; |
581 | }; | |
582 | ||
96c7cc9b MR |
583 | i2c0: i2c@01c2ac00 { |
584 | compatible = "allwinner,sun6i-a31-i2c"; | |
585 | reg = <0x01c2ac00 0x400>; | |
586 | interrupts = <0 6 4>; | |
587 | clocks = <&apb2_gates 0>; | |
588 | clock-frequency = <100000>; | |
589 | resets = <&apb2_rst 0>; | |
590 | status = "disabled"; | |
591 | }; | |
592 | ||
593 | i2c1: i2c@01c2b000 { | |
594 | compatible = "allwinner,sun6i-a31-i2c"; | |
595 | reg = <0x01c2b000 0x400>; | |
596 | interrupts = <0 7 4>; | |
597 | clocks = <&apb2_gates 1>; | |
598 | clock-frequency = <100000>; | |
599 | resets = <&apb2_rst 1>; | |
600 | status = "disabled"; | |
601 | }; | |
602 | ||
603 | i2c2: i2c@01c2b400 { | |
604 | compatible = "allwinner,sun6i-a31-i2c"; | |
605 | reg = <0x01c2b400 0x400>; | |
606 | interrupts = <0 8 4>; | |
607 | clocks = <&apb2_gates 2>; | |
608 | clock-frequency = <100000>; | |
609 | resets = <&apb2_rst 2>; | |
610 | status = "disabled"; | |
611 | }; | |
612 | ||
613 | i2c3: i2c@01c2b800 { | |
614 | compatible = "allwinner,sun6i-a31-i2c"; | |
615 | reg = <0x01c2b800 0x400>; | |
616 | interrupts = <0 9 4>; | |
617 | clocks = <&apb2_gates 3>; | |
618 | clock-frequency = <100000>; | |
619 | resets = <&apb2_rst 3>; | |
620 | status = "disabled"; | |
621 | }; | |
622 | ||
0d6efe33 MR |
623 | spi0: spi@01c68000 { |
624 | compatible = "allwinner,sun6i-a31-spi"; | |
625 | reg = <0x01c68000 0x1000>; | |
626 | interrupts = <0 65 4>; | |
627 | clocks = <&ahb1_gates 20>, <&spi0_clk>; | |
628 | clock-names = "ahb", "mod"; | |
d2d878c4 MR |
629 | dmas = <&dma 23>, <&dma 23>; |
630 | dma-names = "rx", "tx"; | |
0d6efe33 MR |
631 | resets = <&ahb1_rst 20>; |
632 | status = "disabled"; | |
633 | }; | |
634 | ||
635 | spi1: spi@01c69000 { | |
636 | compatible = "allwinner,sun6i-a31-spi"; | |
637 | reg = <0x01c69000 0x1000>; | |
638 | interrupts = <0 66 4>; | |
639 | clocks = <&ahb1_gates 21>, <&spi1_clk>; | |
640 | clock-names = "ahb", "mod"; | |
d2d878c4 MR |
641 | dmas = <&dma 24>, <&dma 24>; |
642 | dma-names = "rx", "tx"; | |
0d6efe33 MR |
643 | resets = <&ahb1_rst 21>; |
644 | status = "disabled"; | |
645 | }; | |
646 | ||
647 | spi2: spi@01c6a000 { | |
648 | compatible = "allwinner,sun6i-a31-spi"; | |
649 | reg = <0x01c6a000 0x1000>; | |
650 | interrupts = <0 67 4>; | |
651 | clocks = <&ahb1_gates 22>, <&spi2_clk>; | |
652 | clock-names = "ahb", "mod"; | |
d2d878c4 MR |
653 | dmas = <&dma 25>, <&dma 25>; |
654 | dma-names = "rx", "tx"; | |
0d6efe33 MR |
655 | resets = <&ahb1_rst 22>; |
656 | status = "disabled"; | |
657 | }; | |
658 | ||
659 | spi3: spi@01c6b000 { | |
660 | compatible = "allwinner,sun6i-a31-spi"; | |
661 | reg = <0x01c6b000 0x1000>; | |
662 | interrupts = <0 68 4>; | |
663 | clocks = <&ahb1_gates 23>, <&spi3_clk>; | |
664 | clock-names = "ahb", "mod"; | |
d2d878c4 MR |
665 | dmas = <&dma 26>, <&dma 26>; |
666 | dma-names = "rx", "tx"; | |
0d6efe33 MR |
667 | resets = <&ahb1_rst 23>; |
668 | status = "disabled"; | |
669 | }; | |
670 | ||
8aed3b31 MR |
671 | gic: interrupt-controller@01c81000 { |
672 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
673 | reg = <0x01c81000 0x1000>, | |
674 | <0x01c82000 0x1000>, | |
675 | <0x01c84000 0x2000>, | |
676 | <0x01c86000 0x2000>; | |
677 | interrupt-controller; | |
678 | #interrupt-cells = <3>; | |
679 | interrupts = <1 9 0xf04>; | |
680 | }; | |
81ee429f | 681 | |
28240d27 MR |
682 | nmi_intc: interrupt-controller@01f00c0c { |
683 | compatible = "allwinner,sun6i-a31-sc-nmi"; | |
684 | interrupt-controller; | |
685 | #interrupt-cells = <2>; | |
686 | reg = <0x01f00c0c 0x38>; | |
687 | interrupts = <0 32 4>; | |
688 | }; | |
689 | ||
a42ea603 HG |
690 | prcm@01f01400 { |
691 | compatible = "allwinner,sun6i-a31-prcm"; | |
692 | reg = <0x01f01400 0x200>; | |
cc08f5e9 BB |
693 | |
694 | ar100: ar100_clk { | |
695 | compatible = "allwinner,sun6i-a31-ar100-clk"; | |
696 | #clock-cells = <0>; | |
697 | clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; | |
698 | clock-output-names = "ar100"; | |
699 | }; | |
700 | ||
701 | ahb0: ahb0_clk { | |
702 | compatible = "fixed-factor-clock"; | |
703 | #clock-cells = <0>; | |
704 | clock-div = <1>; | |
705 | clock-mult = <1>; | |
706 | clocks = <&ar100>; | |
707 | clock-output-names = "ahb0"; | |
708 | }; | |
709 | ||
710 | apb0: apb0_clk { | |
711 | compatible = "allwinner,sun6i-a31-apb0-clk"; | |
712 | #clock-cells = <0>; | |
713 | clocks = <&ahb0>; | |
714 | clock-output-names = "apb0"; | |
715 | }; | |
716 | ||
717 | apb0_gates: apb0_gates_clk { | |
718 | compatible = "allwinner,sun6i-a31-apb0-gates-clk"; | |
719 | #clock-cells = <1>; | |
720 | clocks = <&apb0>; | |
721 | clock-output-names = "apb0_pio", "apb0_ir", | |
722 | "apb0_timer", "apb0_p2wi", | |
723 | "apb0_uart", "apb0_1wire", | |
724 | "apb0_i2c"; | |
725 | }; | |
726 | ||
727 | apb0_rst: apb0_rst { | |
728 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
729 | #reset-cells = <1>; | |
730 | }; | |
a42ea603 HG |
731 | }; |
732 | ||
81ee429f MR |
733 | cpucfg@01f01c00 { |
734 | compatible = "allwinner,sun6i-a31-cpuconfig"; | |
735 | reg = <0x01f01c00 0x300>; | |
736 | }; | |
209394ae BB |
737 | |
738 | r_pio: pinctrl@01f02c00 { | |
739 | compatible = "allwinner,sun6i-a31-r-pinctrl"; | |
740 | reg = <0x01f02c00 0x400>; | |
741 | interrupts = <0 45 4>, | |
742 | <0 46 4>; | |
743 | clocks = <&apb0_gates 0>; | |
744 | resets = <&apb0_rst 0>; | |
745 | gpio-controller; | |
746 | interrupt-controller; | |
747 | #address-cells = <1>; | |
748 | #size-cells = <0>; | |
749 | #gpio-cells = <3>; | |
750 | }; | |
8aed3b31 MR |
751 | }; |
752 | }; |