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8aed3b31 MR |
1 | /* |
2 | * Copyright 2013 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
6c3ba724 MR |
6 | * This file is dual-licensed: you can use it either under the terms |
7 | * of the GPL or the X11 license, at your option. Note that this dual | |
8 | * licensing only applies to this file, and not this project as a | |
9 | * whole. | |
8aed3b31 | 10 | * |
6c3ba724 MR |
11 | * a) This library is free software; you can redistribute it and/or |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of the | |
14 | * License, or (at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public | |
22 | * License along with this library; if not, write to the Free | |
23 | * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, | |
24 | * MA 02110-1301 USA | |
25 | * | |
26 | * Or, alternatively, | |
27 | * | |
28 | * b) Permission is hereby granted, free of charge, to any person | |
29 | * obtaining a copy of this software and associated documentation | |
30 | * files (the "Software"), to deal in the Software without | |
31 | * restriction, including without limitation the rights to use, | |
32 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
33 | * sell copies of the Software, and to permit persons to whom the | |
34 | * Software is furnished to do so, subject to the following | |
35 | * conditions: | |
36 | * | |
37 | * The above copyright notice and this permission notice shall be | |
38 | * included in all copies or substantial portions of the Software. | |
39 | * | |
40 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
41 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
42 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
43 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
44 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
45 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
46 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
47 | * OTHER DEALINGS IN THE SOFTWARE. | |
8aed3b31 MR |
48 | */ |
49 | ||
50 | /include/ "skeleton.dtsi" | |
51 | ||
52 | / { | |
53 | interrupt-parent = <&gic>; | |
54 | ||
54428d40 MR |
55 | aliases { |
56 | serial0 = &uart0; | |
57 | serial1 = &uart1; | |
58 | serial2 = &uart2; | |
59 | serial3 = &uart3; | |
60 | serial4 = &uart4; | |
61 | serial5 = &uart5; | |
e5073fde | 62 | ethernet0 = &gmac; |
54428d40 MR |
63 | }; |
64 | ||
65 | ||
8aed3b31 | 66 | cpus { |
ce78e353 | 67 | enable-method = "allwinner,sun6i-a31"; |
8aed3b31 MR |
68 | #address-cells = <1>; |
69 | #size-cells = <0>; | |
70 | ||
71 | cpu@0 { | |
72 | compatible = "arm,cortex-a7"; | |
73 | device_type = "cpu"; | |
74 | reg = <0>; | |
75 | }; | |
76 | ||
77 | cpu@1 { | |
78 | compatible = "arm,cortex-a7"; | |
79 | device_type = "cpu"; | |
80 | reg = <1>; | |
81 | }; | |
82 | ||
83 | cpu@2 { | |
84 | compatible = "arm,cortex-a7"; | |
85 | device_type = "cpu"; | |
86 | reg = <2>; | |
87 | }; | |
88 | ||
89 | cpu@3 { | |
90 | compatible = "arm,cortex-a7"; | |
91 | device_type = "cpu"; | |
92 | reg = <3>; | |
93 | }; | |
94 | }; | |
95 | ||
96 | memory { | |
97 | reg = <0x40000000 0x80000000>; | |
98 | }; | |
99 | ||
b5a10b76 MR |
100 | pmu { |
101 | compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; | |
102 | interrupts = <0 120 4>, | |
103 | <0 121 4>, | |
104 | <0 122 4>, | |
105 | <0 123 4>; | |
106 | }; | |
107 | ||
8aed3b31 MR |
108 | clocks { |
109 | #address-cells = <1>; | |
98096560 MR |
110 | #size-cells = <1>; |
111 | ranges; | |
8aed3b31 | 112 | |
98096560 | 113 | osc24M: osc24M { |
8aed3b31 MR |
114 | #clock-cells = <0>; |
115 | compatible = "fixed-clock"; | |
116 | clock-frequency = <24000000>; | |
117 | }; | |
98096560 | 118 | |
7b5b2909 | 119 | osc32k: clk@0 { |
98096560 MR |
120 | #clock-cells = <0>; |
121 | compatible = "fixed-clock"; | |
122 | clock-frequency = <32768>; | |
7b5b2909 | 123 | clock-output-names = "osc32k"; |
98096560 MR |
124 | }; |
125 | ||
7b5b2909 | 126 | pll1: clk@01c20000 { |
98096560 MR |
127 | #clock-cells = <0>; |
128 | compatible = "allwinner,sun6i-a31-pll1-clk"; | |
129 | reg = <0x01c20000 0x4>; | |
130 | clocks = <&osc24M>; | |
7b5b2909 | 131 | clock-output-names = "pll1"; |
98096560 MR |
132 | }; |
133 | ||
b0a09c75 | 134 | pll6: clk@01c20028 { |
98096560 | 135 | #clock-cells = <0>; |
b0a09c75 MR |
136 | compatible = "allwinner,sun6i-a31-pll6-clk"; |
137 | reg = <0x01c20028 0x4>; | |
138 | clocks = <&osc24M>; | |
139 | clock-output-names = "pll6"; | |
98096560 MR |
140 | }; |
141 | ||
142 | cpu: cpu@01c20050 { | |
143 | #clock-cells = <0>; | |
bf6534a1 | 144 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
98096560 MR |
145 | reg = <0x01c20050 0x4>; |
146 | ||
147 | /* | |
148 | * PLL1 is listed twice here. | |
149 | * While it looks suspicious, it's actually documented | |
150 | * that way both in the datasheet and in the code from | |
151 | * Allwinner. | |
152 | */ | |
153 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; | |
7b5b2909 | 154 | clock-output-names = "cpu"; |
98096560 MR |
155 | }; |
156 | ||
157 | axi: axi@01c20050 { | |
158 | #clock-cells = <0>; | |
bf6534a1 | 159 | compatible = "allwinner,sun4i-a10-axi-clk"; |
98096560 MR |
160 | reg = <0x01c20050 0x4>; |
161 | clocks = <&cpu>; | |
7b5b2909 | 162 | clock-output-names = "axi"; |
98096560 MR |
163 | }; |
164 | ||
165 | ahb1_mux: ahb1_mux@01c20054 { | |
166 | #clock-cells = <0>; | |
167 | compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; | |
168 | reg = <0x01c20054 0x4>; | |
169 | clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; | |
7b5b2909 | 170 | clock-output-names = "ahb1_mux"; |
98096560 MR |
171 | }; |
172 | ||
173 | ahb1: ahb1@01c20054 { | |
174 | #clock-cells = <0>; | |
bf6534a1 | 175 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
98096560 MR |
176 | reg = <0x01c20054 0x4>; |
177 | clocks = <&ahb1_mux>; | |
7b5b2909 | 178 | clock-output-names = "ahb1"; |
98096560 MR |
179 | }; |
180 | ||
7b5b2909 | 181 | ahb1_gates: clk@01c20060 { |
98096560 MR |
182 | #clock-cells = <1>; |
183 | compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; | |
184 | reg = <0x01c20060 0x8>; | |
185 | clocks = <&ahb1>; | |
186 | clock-output-names = "ahb1_mipidsi", "ahb1_ss", | |
187 | "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1", | |
188 | "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1", | |
189 | "ahb1_nand0", "ahb1_sdram", | |
190 | "ahb1_gmac", "ahb1_ts", "ahb1_hstimer", | |
191 | "ahb1_spi0", "ahb1_spi1", "ahb1_spi2", | |
192 | "ahb1_spi3", "ahb1_otg", "ahb1_ehci0", | |
193 | "ahb1_ehci1", "ahb1_ohci0", | |
194 | "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve", | |
195 | "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi", | |
196 | "ahb1_hdmi", "ahb1_de0", "ahb1_de1", | |
197 | "ahb1_fe0", "ahb1_fe1", "ahb1_mp", | |
198 | "ahb1_gpu", "ahb1_deu0", "ahb1_deu1", | |
199 | "ahb1_drc0", "ahb1_drc1"; | |
200 | }; | |
201 | ||
202 | apb1: apb1@01c20054 { | |
203 | #clock-cells = <0>; | |
bf6534a1 | 204 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
98096560 MR |
205 | reg = <0x01c20054 0x4>; |
206 | clocks = <&ahb1>; | |
7b5b2909 | 207 | clock-output-names = "apb1"; |
98096560 MR |
208 | }; |
209 | ||
7b5b2909 | 210 | apb1_gates: clk@01c20068 { |
98096560 MR |
211 | #clock-cells = <1>; |
212 | compatible = "allwinner,sun6i-a31-apb1-gates-clk"; | |
213 | reg = <0x01c20068 0x4>; | |
214 | clocks = <&apb1>; | |
215 | clock-output-names = "apb1_codec", "apb1_digital_mic", | |
216 | "apb1_pio", "apb1_daudio0", | |
217 | "apb1_daudio1"; | |
218 | }; | |
219 | ||
220 | apb2_mux: apb2_mux@01c20058 { | |
221 | #clock-cells = <0>; | |
bf6534a1 | 222 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
98096560 MR |
223 | reg = <0x01c20058 0x4>; |
224 | clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; | |
7b5b2909 | 225 | clock-output-names = "apb2_mux"; |
98096560 MR |
226 | }; |
227 | ||
228 | apb2: apb2@01c20058 { | |
229 | #clock-cells = <0>; | |
230 | compatible = "allwinner,sun6i-a31-apb2-div-clk"; | |
231 | reg = <0x01c20058 0x4>; | |
232 | clocks = <&apb2_mux>; | |
7b5b2909 | 233 | clock-output-names = "apb2"; |
98096560 MR |
234 | }; |
235 | ||
7b5b2909 | 236 | apb2_gates: clk@01c2006c { |
98096560 MR |
237 | #clock-cells = <1>; |
238 | compatible = "allwinner,sun6i-a31-apb2-gates-clk"; | |
439d9f58 | 239 | reg = <0x01c2006c 0x4>; |
98096560 MR |
240 | clocks = <&apb2>; |
241 | clock-output-names = "apb2_i2c0", "apb2_i2c1", | |
242 | "apb2_i2c2", "apb2_i2c3", "apb2_uart0", | |
243 | "apb2_uart1", "apb2_uart2", "apb2_uart3", | |
244 | "apb2_uart4", "apb2_uart5"; | |
245 | }; | |
b0a09c75 | 246 | |
adc54c85 HG |
247 | mmc0_clk: clk@01c20088 { |
248 | #clock-cells = <0>; | |
249 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
250 | reg = <0x01c20088 0x4>; | |
251 | clocks = <&osc24M>, <&pll6>; | |
252 | clock-output-names = "mmc0"; | |
253 | }; | |
254 | ||
255 | mmc1_clk: clk@01c2008c { | |
256 | #clock-cells = <0>; | |
257 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
258 | reg = <0x01c2008c 0x4>; | |
259 | clocks = <&osc24M>, <&pll6>; | |
260 | clock-output-names = "mmc1"; | |
261 | }; | |
262 | ||
263 | mmc2_clk: clk@01c20090 { | |
264 | #clock-cells = <0>; | |
265 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
266 | reg = <0x01c20090 0x4>; | |
267 | clocks = <&osc24M>, <&pll6>; | |
268 | clock-output-names = "mmc2"; | |
269 | }; | |
270 | ||
271 | mmc3_clk: clk@01c20094 { | |
272 | #clock-cells = <0>; | |
273 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
274 | reg = <0x01c20094 0x4>; | |
275 | clocks = <&osc24M>, <&pll6>; | |
276 | clock-output-names = "mmc3"; | |
277 | }; | |
278 | ||
b0a09c75 MR |
279 | spi0_clk: clk@01c200a0 { |
280 | #clock-cells = <0>; | |
225b0216 | 281 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
b0a09c75 MR |
282 | reg = <0x01c200a0 0x4>; |
283 | clocks = <&osc24M>, <&pll6>; | |
284 | clock-output-names = "spi0"; | |
285 | }; | |
286 | ||
287 | spi1_clk: clk@01c200a4 { | |
288 | #clock-cells = <0>; | |
225b0216 | 289 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
b0a09c75 MR |
290 | reg = <0x01c200a4 0x4>; |
291 | clocks = <&osc24M>, <&pll6>; | |
292 | clock-output-names = "spi1"; | |
293 | }; | |
294 | ||
295 | spi2_clk: clk@01c200a8 { | |
296 | #clock-cells = <0>; | |
225b0216 | 297 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
b0a09c75 MR |
298 | reg = <0x01c200a8 0x4>; |
299 | clocks = <&osc24M>, <&pll6>; | |
300 | clock-output-names = "spi2"; | |
301 | }; | |
302 | ||
303 | spi3_clk: clk@01c200ac { | |
304 | #clock-cells = <0>; | |
225b0216 | 305 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
b0a09c75 MR |
306 | reg = <0x01c200ac 0x4>; |
307 | clocks = <&osc24M>, <&pll6>; | |
308 | clock-output-names = "spi3"; | |
309 | }; | |
94a1cd14 MR |
310 | |
311 | usb_clk: clk@01c200cc { | |
312 | #clock-cells = <1>; | |
313 | #reset-cells = <1>; | |
314 | compatible = "allwinner,sun6i-a31-usb-clk"; | |
315 | reg = <0x01c200cc 0x4>; | |
316 | clocks = <&osc24M>; | |
317 | clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2", | |
318 | "usb_ohci0", "usb_ohci1", | |
319 | "usb_ohci2"; | |
320 | }; | |
ed29861a CYT |
321 | |
322 | /* | |
323 | * The following two are dummy clocks, placeholders used in the gmac_tx | |
324 | * clock. The gmac driver will choose one parent depending on the PHY | |
325 | * interface mode, using clk_set_rate auto-reparenting. | |
326 | * The actual TX clock rate is not controlled by the gmac_tx clock. | |
327 | */ | |
328 | mii_phy_tx_clk: clk@1 { | |
329 | #clock-cells = <0>; | |
330 | compatible = "fixed-clock"; | |
331 | clock-frequency = <25000000>; | |
332 | clock-output-names = "mii_phy_tx"; | |
333 | }; | |
334 | ||
335 | gmac_int_tx_clk: clk@2 { | |
336 | #clock-cells = <0>; | |
337 | compatible = "fixed-clock"; | |
338 | clock-frequency = <125000000>; | |
339 | clock-output-names = "gmac_int_tx"; | |
340 | }; | |
341 | ||
342 | gmac_tx_clk: clk@01c200d0 { | |
343 | #clock-cells = <0>; | |
344 | compatible = "allwinner,sun7i-a20-gmac-clk"; | |
345 | reg = <0x01c200d0 0x4>; | |
346 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; | |
347 | clock-output-names = "gmac_tx"; | |
348 | }; | |
8aed3b31 MR |
349 | }; |
350 | ||
351 | soc@01c00000 { | |
352 | compatible = "simple-bus"; | |
353 | #address-cells = <1>; | |
354 | #size-cells = <1>; | |
355 | ranges; | |
356 | ||
d2d878c4 MR |
357 | dma: dma-controller@01c02000 { |
358 | compatible = "allwinner,sun6i-a31-dma"; | |
359 | reg = <0x01c02000 0x1000>; | |
360 | interrupts = <0 50 4>; | |
361 | clocks = <&ahb1_gates 6>; | |
362 | resets = <&ahb1_rst 6>; | |
363 | #dma-cells = <1>; | |
364 | }; | |
365 | ||
5b753f0e HG |
366 | mmc0: mmc@01c0f000 { |
367 | compatible = "allwinner,sun5i-a13-mmc"; | |
368 | reg = <0x01c0f000 0x1000>; | |
369 | clocks = <&ahb1_gates 8>, <&mmc0_clk>; | |
370 | clock-names = "ahb", "mmc"; | |
371 | resets = <&ahb1_rst 8>; | |
372 | reset-names = "ahb"; | |
373 | interrupts = <0 60 4>; | |
374 | status = "disabled"; | |
375 | }; | |
376 | ||
377 | mmc1: mmc@01c10000 { | |
378 | compatible = "allwinner,sun5i-a13-mmc"; | |
379 | reg = <0x01c10000 0x1000>; | |
380 | clocks = <&ahb1_gates 9>, <&mmc1_clk>; | |
381 | clock-names = "ahb", "mmc"; | |
382 | resets = <&ahb1_rst 9>; | |
383 | reset-names = "ahb"; | |
384 | interrupts = <0 61 4>; | |
385 | status = "disabled"; | |
386 | }; | |
387 | ||
388 | mmc2: mmc@01c11000 { | |
389 | compatible = "allwinner,sun5i-a13-mmc"; | |
390 | reg = <0x01c11000 0x1000>; | |
391 | clocks = <&ahb1_gates 10>, <&mmc2_clk>; | |
392 | clock-names = "ahb", "mmc"; | |
393 | resets = <&ahb1_rst 10>; | |
394 | reset-names = "ahb"; | |
395 | interrupts = <0 62 4>; | |
396 | status = "disabled"; | |
397 | }; | |
398 | ||
399 | mmc3: mmc@01c12000 { | |
400 | compatible = "allwinner,sun5i-a13-mmc"; | |
401 | reg = <0x01c12000 0x1000>; | |
402 | clocks = <&ahb1_gates 11>, <&mmc3_clk>; | |
403 | clock-names = "ahb", "mmc"; | |
404 | resets = <&ahb1_rst 11>; | |
405 | reset-names = "ahb"; | |
406 | interrupts = <0 63 4>; | |
407 | status = "disabled"; | |
408 | }; | |
409 | ||
ef964085 MR |
410 | usbphy: phy@01c19400 { |
411 | compatible = "allwinner,sun6i-a31-usb-phy"; | |
412 | reg = <0x01c19400 0x10>, | |
413 | <0x01c1a800 0x4>, | |
414 | <0x01c1b800 0x4>; | |
415 | reg-names = "phy_ctrl", | |
416 | "pmu1", | |
417 | "pmu2"; | |
418 | clocks = <&usb_clk 8>, | |
419 | <&usb_clk 9>, | |
420 | <&usb_clk 10>; | |
421 | clock-names = "usb0_phy", | |
422 | "usb1_phy", | |
423 | "usb2_phy"; | |
424 | resets = <&usb_clk 0>, | |
425 | <&usb_clk 1>, | |
426 | <&usb_clk 2>; | |
427 | reset-names = "usb0_reset", | |
428 | "usb1_reset", | |
429 | "usb2_reset"; | |
430 | status = "disabled"; | |
431 | #phy-cells = <1>; | |
432 | }; | |
433 | ||
434 | ehci0: usb@01c1a000 { | |
435 | compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; | |
436 | reg = <0x01c1a000 0x100>; | |
437 | interrupts = <0 72 4>; | |
438 | clocks = <&ahb1_gates 26>; | |
439 | resets = <&ahb1_rst 26>; | |
440 | phys = <&usbphy 1>; | |
441 | phy-names = "usb"; | |
442 | status = "disabled"; | |
443 | }; | |
444 | ||
445 | ohci0: usb@01c1a400 { | |
446 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; | |
447 | reg = <0x01c1a400 0x100>; | |
448 | interrupts = <0 73 4>; | |
449 | clocks = <&ahb1_gates 29>, <&usb_clk 16>; | |
450 | resets = <&ahb1_rst 29>; | |
451 | phys = <&usbphy 1>; | |
452 | phy-names = "usb"; | |
453 | status = "disabled"; | |
454 | }; | |
455 | ||
456 | ehci1: usb@01c1b000 { | |
457 | compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; | |
458 | reg = <0x01c1b000 0x100>; | |
459 | interrupts = <0 74 4>; | |
460 | clocks = <&ahb1_gates 27>; | |
461 | resets = <&ahb1_rst 27>; | |
462 | phys = <&usbphy 2>; | |
463 | phy-names = "usb"; | |
464 | status = "disabled"; | |
465 | }; | |
466 | ||
467 | ohci1: usb@01c1b400 { | |
468 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; | |
469 | reg = <0x01c1b400 0x100>; | |
470 | interrupts = <0 75 4>; | |
471 | clocks = <&ahb1_gates 30>, <&usb_clk 17>; | |
472 | resets = <&ahb1_rst 30>; | |
473 | phys = <&usbphy 2>; | |
474 | phy-names = "usb"; | |
475 | status = "disabled"; | |
476 | }; | |
477 | ||
b294ebbc | 478 | ohci2: usb@01c1c400 { |
ef964085 MR |
479 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; |
480 | reg = <0x01c1c400 0x100>; | |
481 | interrupts = <0 77 4>; | |
482 | clocks = <&ahb1_gates 31>, <&usb_clk 18>; | |
483 | resets = <&ahb1_rst 31>; | |
484 | status = "disabled"; | |
485 | }; | |
486 | ||
140e1721 MR |
487 | pio: pinctrl@01c20800 { |
488 | compatible = "allwinner,sun6i-a31-pinctrl"; | |
489 | reg = <0x01c20800 0x400>; | |
6f97dc8d MR |
490 | interrupts = <0 11 4>, |
491 | <0 15 4>, | |
492 | <0 16 4>, | |
493 | <0 17 4>; | |
98096560 | 494 | clocks = <&apb1_gates 5>; |
140e1721 MR |
495 | gpio-controller; |
496 | interrupt-controller; | |
7d4ff96d | 497 | #interrupt-cells = <2>; |
140e1721 MR |
498 | #size-cells = <0>; |
499 | #gpio-cells = <3>; | |
ab4238cd MR |
500 | |
501 | uart0_pins_a: uart0@0 { | |
502 | allwinner,pins = "PH20", "PH21"; | |
503 | allwinner,function = "uart0"; | |
504 | allwinner,drive = <0>; | |
505 | allwinner,pull = <0>; | |
506 | }; | |
8be188b8 MR |
507 | |
508 | i2c0_pins_a: i2c0@0 { | |
509 | allwinner,pins = "PH14", "PH15"; | |
510 | allwinner,function = "i2c0"; | |
511 | allwinner,drive = <0>; | |
512 | allwinner,pull = <0>; | |
513 | }; | |
514 | ||
515 | i2c1_pins_a: i2c1@0 { | |
516 | allwinner,pins = "PH16", "PH17"; | |
517 | allwinner,function = "i2c1"; | |
518 | allwinner,drive = <0>; | |
519 | allwinner,pull = <0>; | |
520 | }; | |
521 | ||
522 | i2c2_pins_a: i2c2@0 { | |
523 | allwinner,pins = "PH18", "PH19"; | |
524 | allwinner,function = "i2c2"; | |
525 | allwinner,drive = <0>; | |
526 | allwinner,pull = <0>; | |
527 | }; | |
9797eb83 HG |
528 | |
529 | mmc0_pins_a: mmc0@0 { | |
530 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | |
531 | allwinner,function = "mmc0"; | |
532 | allwinner,drive = <2>; | |
533 | allwinner,pull = <0>; | |
534 | }; | |
ee39a3e3 CYT |
535 | |
536 | gmac_pins_mii_a: gmac_mii@0 { | |
537 | allwinner,pins = "PA0", "PA1", "PA2", "PA3", | |
538 | "PA8", "PA9", "PA11", | |
539 | "PA12", "PA13", "PA14", "PA19", | |
540 | "PA20", "PA21", "PA22", "PA23", | |
541 | "PA24", "PA26", "PA27"; | |
542 | allwinner,function = "gmac"; | |
543 | allwinner,drive = <0>; | |
544 | allwinner,pull = <0>; | |
545 | }; | |
546 | ||
547 | gmac_pins_gmii_a: gmac_gmii@0 { | |
548 | allwinner,pins = "PA0", "PA1", "PA2", "PA3", | |
549 | "PA4", "PA5", "PA6", "PA7", | |
550 | "PA8", "PA9", "PA10", "PA11", | |
551 | "PA12", "PA13", "PA14", "PA15", | |
552 | "PA16", "PA17", "PA18", "PA19", | |
553 | "PA20", "PA21", "PA22", "PA23", | |
554 | "PA24", "PA25", "PA26", "PA27"; | |
555 | allwinner,function = "gmac"; | |
556 | /* | |
557 | * data lines in GMII mode run at 125MHz and | |
558 | * might need a higher signal drive strength | |
559 | */ | |
560 | allwinner,drive = <2>; | |
561 | allwinner,pull = <0>; | |
562 | }; | |
563 | ||
564 | gmac_pins_rgmii_a: gmac_rgmii@0 { | |
565 | allwinner,pins = "PA0", "PA1", "PA2", "PA3", | |
566 | "PA9", "PA10", "PA11", | |
567 | "PA12", "PA13", "PA14", "PA19", | |
568 | "PA20", "PA25", "PA26", "PA27"; | |
569 | allwinner,function = "gmac"; | |
570 | /* | |
571 | * data lines in RGMII mode use DDR mode | |
572 | * and need a higher signal drive strength | |
573 | */ | |
574 | allwinner,drive = <3>; | |
575 | allwinner,pull = <0>; | |
576 | }; | |
140e1721 MR |
577 | }; |
578 | ||
24a661e9 MR |
579 | ahb1_rst: reset@01c202c0 { |
580 | #reset-cells = <1>; | |
581 | compatible = "allwinner,sun6i-a31-ahb1-reset"; | |
582 | reg = <0x01c202c0 0xc>; | |
583 | }; | |
584 | ||
585 | apb1_rst: reset@01c202d0 { | |
586 | #reset-cells = <1>; | |
587 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
588 | reg = <0x01c202d0 0x4>; | |
589 | }; | |
590 | ||
591 | apb2_rst: reset@01c202d8 { | |
592 | #reset-cells = <1>; | |
593 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
594 | reg = <0x01c202d8 0x4>; | |
595 | }; | |
596 | ||
8aed3b31 | 597 | timer@01c20c00 { |
b4f26440 | 598 | compatible = "allwinner,sun4i-a10-timer"; |
8aed3b31 | 599 | reg = <0x01c20c00 0xa0>; |
6f97dc8d MR |
600 | interrupts = <0 18 4>, |
601 | <0 19 4>, | |
602 | <0 20 4>, | |
603 | <0 21 4>, | |
604 | <0 22 4>; | |
98096560 | 605 | clocks = <&osc24M>; |
8aed3b31 MR |
606 | }; |
607 | ||
608 | wdt1: watchdog@01c20ca0 { | |
ca5d04d9 | 609 | compatible = "allwinner,sun6i-a31-wdt"; |
8aed3b31 MR |
610 | reg = <0x01c20ca0 0x20>; |
611 | }; | |
612 | ||
613 | uart0: serial@01c28000 { | |
614 | compatible = "snps,dw-apb-uart"; | |
615 | reg = <0x01c28000 0x400>; | |
6f97dc8d | 616 | interrupts = <0 0 4>; |
8aed3b31 MR |
617 | reg-shift = <2>; |
618 | reg-io-width = <4>; | |
98096560 | 619 | clocks = <&apb2_gates 16>; |
24a661e9 | 620 | resets = <&apb2_rst 16>; |
d2d878c4 MR |
621 | dmas = <&dma 6>, <&dma 6>; |
622 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
623 | status = "disabled"; |
624 | }; | |
625 | ||
626 | uart1: serial@01c28400 { | |
627 | compatible = "snps,dw-apb-uart"; | |
628 | reg = <0x01c28400 0x400>; | |
6f97dc8d | 629 | interrupts = <0 1 4>; |
8aed3b31 MR |
630 | reg-shift = <2>; |
631 | reg-io-width = <4>; | |
98096560 | 632 | clocks = <&apb2_gates 17>; |
24a661e9 | 633 | resets = <&apb2_rst 17>; |
d2d878c4 MR |
634 | dmas = <&dma 7>, <&dma 7>; |
635 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
636 | status = "disabled"; |
637 | }; | |
638 | ||
639 | uart2: serial@01c28800 { | |
640 | compatible = "snps,dw-apb-uart"; | |
641 | reg = <0x01c28800 0x400>; | |
6f97dc8d | 642 | interrupts = <0 2 4>; |
8aed3b31 MR |
643 | reg-shift = <2>; |
644 | reg-io-width = <4>; | |
98096560 | 645 | clocks = <&apb2_gates 18>; |
24a661e9 | 646 | resets = <&apb2_rst 18>; |
d2d878c4 MR |
647 | dmas = <&dma 8>, <&dma 8>; |
648 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
649 | status = "disabled"; |
650 | }; | |
651 | ||
652 | uart3: serial@01c28c00 { | |
653 | compatible = "snps,dw-apb-uart"; | |
654 | reg = <0x01c28c00 0x400>; | |
6f97dc8d | 655 | interrupts = <0 3 4>; |
8aed3b31 MR |
656 | reg-shift = <2>; |
657 | reg-io-width = <4>; | |
98096560 | 658 | clocks = <&apb2_gates 19>; |
24a661e9 | 659 | resets = <&apb2_rst 19>; |
d2d878c4 MR |
660 | dmas = <&dma 9>, <&dma 9>; |
661 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
662 | status = "disabled"; |
663 | }; | |
664 | ||
665 | uart4: serial@01c29000 { | |
666 | compatible = "snps,dw-apb-uart"; | |
667 | reg = <0x01c29000 0x400>; | |
6f97dc8d | 668 | interrupts = <0 4 4>; |
8aed3b31 MR |
669 | reg-shift = <2>; |
670 | reg-io-width = <4>; | |
98096560 | 671 | clocks = <&apb2_gates 20>; |
24a661e9 | 672 | resets = <&apb2_rst 20>; |
d2d878c4 MR |
673 | dmas = <&dma 10>, <&dma 10>; |
674 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
675 | status = "disabled"; |
676 | }; | |
677 | ||
678 | uart5: serial@01c29400 { | |
679 | compatible = "snps,dw-apb-uart"; | |
680 | reg = <0x01c29400 0x400>; | |
6f97dc8d | 681 | interrupts = <0 5 4>; |
8aed3b31 MR |
682 | reg-shift = <2>; |
683 | reg-io-width = <4>; | |
98096560 | 684 | clocks = <&apb2_gates 21>; |
24a661e9 | 685 | resets = <&apb2_rst 21>; |
d2d878c4 MR |
686 | dmas = <&dma 22>, <&dma 22>; |
687 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
688 | status = "disabled"; |
689 | }; | |
690 | ||
96c7cc9b MR |
691 | i2c0: i2c@01c2ac00 { |
692 | compatible = "allwinner,sun6i-a31-i2c"; | |
693 | reg = <0x01c2ac00 0x400>; | |
694 | interrupts = <0 6 4>; | |
695 | clocks = <&apb2_gates 0>; | |
96c7cc9b MR |
696 | resets = <&apb2_rst 0>; |
697 | status = "disabled"; | |
495bccf3 CYT |
698 | #address-cells = <1>; |
699 | #size-cells = <0>; | |
96c7cc9b MR |
700 | }; |
701 | ||
702 | i2c1: i2c@01c2b000 { | |
703 | compatible = "allwinner,sun6i-a31-i2c"; | |
704 | reg = <0x01c2b000 0x400>; | |
705 | interrupts = <0 7 4>; | |
706 | clocks = <&apb2_gates 1>; | |
96c7cc9b MR |
707 | resets = <&apb2_rst 1>; |
708 | status = "disabled"; | |
495bccf3 CYT |
709 | #address-cells = <1>; |
710 | #size-cells = <0>; | |
96c7cc9b MR |
711 | }; |
712 | ||
713 | i2c2: i2c@01c2b400 { | |
714 | compatible = "allwinner,sun6i-a31-i2c"; | |
715 | reg = <0x01c2b400 0x400>; | |
716 | interrupts = <0 8 4>; | |
717 | clocks = <&apb2_gates 2>; | |
96c7cc9b MR |
718 | resets = <&apb2_rst 2>; |
719 | status = "disabled"; | |
495bccf3 CYT |
720 | #address-cells = <1>; |
721 | #size-cells = <0>; | |
96c7cc9b MR |
722 | }; |
723 | ||
724 | i2c3: i2c@01c2b800 { | |
725 | compatible = "allwinner,sun6i-a31-i2c"; | |
726 | reg = <0x01c2b800 0x400>; | |
727 | interrupts = <0 9 4>; | |
728 | clocks = <&apb2_gates 3>; | |
96c7cc9b MR |
729 | resets = <&apb2_rst 3>; |
730 | status = "disabled"; | |
495bccf3 CYT |
731 | #address-cells = <1>; |
732 | #size-cells = <0>; | |
96c7cc9b MR |
733 | }; |
734 | ||
3dca65f8 CYT |
735 | gmac: ethernet@01c30000 { |
736 | compatible = "allwinner,sun7i-a20-gmac"; | |
737 | reg = <0x01c30000 0x1054>; | |
738 | interrupts = <0 82 4>; | |
739 | interrupt-names = "macirq"; | |
740 | clocks = <&ahb1_gates 17>, <&gmac_tx_clk>; | |
741 | clock-names = "stmmaceth", "allwinner_gmac_tx"; | |
742 | resets = <&ahb1_rst 17>; | |
743 | reset-names = "stmmaceth"; | |
744 | snps,pbl = <2>; | |
745 | snps,fixed-burst; | |
746 | snps,force_sf_dma_mode; | |
747 | status = "disabled"; | |
748 | #address-cells = <1>; | |
749 | #size-cells = <0>; | |
750 | }; | |
751 | ||
8cffcb0c MR |
752 | timer@01c60000 { |
753 | compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; | |
754 | reg = <0x01c60000 0x1000>; | |
755 | interrupts = <0 51 4>, | |
756 | <0 52 4>, | |
757 | <0 53 4>, | |
758 | <0 54 4>; | |
759 | clocks = <&ahb1_gates 19>; | |
760 | resets = <&ahb1_rst 19>; | |
761 | }; | |
762 | ||
0d6efe33 MR |
763 | spi0: spi@01c68000 { |
764 | compatible = "allwinner,sun6i-a31-spi"; | |
765 | reg = <0x01c68000 0x1000>; | |
766 | interrupts = <0 65 4>; | |
767 | clocks = <&ahb1_gates 20>, <&spi0_clk>; | |
768 | clock-names = "ahb", "mod"; | |
d2d878c4 MR |
769 | dmas = <&dma 23>, <&dma 23>; |
770 | dma-names = "rx", "tx"; | |
0d6efe33 MR |
771 | resets = <&ahb1_rst 20>; |
772 | status = "disabled"; | |
773 | }; | |
774 | ||
775 | spi1: spi@01c69000 { | |
776 | compatible = "allwinner,sun6i-a31-spi"; | |
777 | reg = <0x01c69000 0x1000>; | |
778 | interrupts = <0 66 4>; | |
779 | clocks = <&ahb1_gates 21>, <&spi1_clk>; | |
780 | clock-names = "ahb", "mod"; | |
d2d878c4 MR |
781 | dmas = <&dma 24>, <&dma 24>; |
782 | dma-names = "rx", "tx"; | |
0d6efe33 MR |
783 | resets = <&ahb1_rst 21>; |
784 | status = "disabled"; | |
785 | }; | |
786 | ||
787 | spi2: spi@01c6a000 { | |
788 | compatible = "allwinner,sun6i-a31-spi"; | |
789 | reg = <0x01c6a000 0x1000>; | |
790 | interrupts = <0 67 4>; | |
791 | clocks = <&ahb1_gates 22>, <&spi2_clk>; | |
792 | clock-names = "ahb", "mod"; | |
d2d878c4 MR |
793 | dmas = <&dma 25>, <&dma 25>; |
794 | dma-names = "rx", "tx"; | |
0d6efe33 MR |
795 | resets = <&ahb1_rst 22>; |
796 | status = "disabled"; | |
797 | }; | |
798 | ||
799 | spi3: spi@01c6b000 { | |
800 | compatible = "allwinner,sun6i-a31-spi"; | |
801 | reg = <0x01c6b000 0x1000>; | |
802 | interrupts = <0 68 4>; | |
803 | clocks = <&ahb1_gates 23>, <&spi3_clk>; | |
804 | clock-names = "ahb", "mod"; | |
d2d878c4 MR |
805 | dmas = <&dma 26>, <&dma 26>; |
806 | dma-names = "rx", "tx"; | |
0d6efe33 MR |
807 | resets = <&ahb1_rst 23>; |
808 | status = "disabled"; | |
809 | }; | |
810 | ||
8aed3b31 MR |
811 | gic: interrupt-controller@01c81000 { |
812 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
813 | reg = <0x01c81000 0x1000>, | |
814 | <0x01c82000 0x1000>, | |
815 | <0x01c84000 0x2000>, | |
816 | <0x01c86000 0x2000>; | |
817 | interrupt-controller; | |
818 | #interrupt-cells = <3>; | |
819 | interrupts = <1 9 0xf04>; | |
820 | }; | |
81ee429f | 821 | |
5e700435 CYT |
822 | rtc: rtc@01f00000 { |
823 | compatible = "allwinner,sun6i-a31-rtc"; | |
824 | reg = <0x01f00000 0x54>; | |
825 | interrupts = <0 40 4>, <0 41 4>; | |
826 | }; | |
827 | ||
28240d27 MR |
828 | nmi_intc: interrupt-controller@01f00c0c { |
829 | compatible = "allwinner,sun6i-a31-sc-nmi"; | |
830 | interrupt-controller; | |
831 | #interrupt-cells = <2>; | |
832 | reg = <0x01f00c0c 0x38>; | |
833 | interrupts = <0 32 4>; | |
834 | }; | |
835 | ||
a42ea603 HG |
836 | prcm@01f01400 { |
837 | compatible = "allwinner,sun6i-a31-prcm"; | |
838 | reg = <0x01f01400 0x200>; | |
cc08f5e9 BB |
839 | |
840 | ar100: ar100_clk { | |
841 | compatible = "allwinner,sun6i-a31-ar100-clk"; | |
842 | #clock-cells = <0>; | |
843 | clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; | |
844 | clock-output-names = "ar100"; | |
845 | }; | |
846 | ||
847 | ahb0: ahb0_clk { | |
848 | compatible = "fixed-factor-clock"; | |
849 | #clock-cells = <0>; | |
850 | clock-div = <1>; | |
851 | clock-mult = <1>; | |
852 | clocks = <&ar100>; | |
853 | clock-output-names = "ahb0"; | |
854 | }; | |
855 | ||
856 | apb0: apb0_clk { | |
857 | compatible = "allwinner,sun6i-a31-apb0-clk"; | |
858 | #clock-cells = <0>; | |
859 | clocks = <&ahb0>; | |
860 | clock-output-names = "apb0"; | |
861 | }; | |
862 | ||
863 | apb0_gates: apb0_gates_clk { | |
864 | compatible = "allwinner,sun6i-a31-apb0-gates-clk"; | |
865 | #clock-cells = <1>; | |
866 | clocks = <&apb0>; | |
867 | clock-output-names = "apb0_pio", "apb0_ir", | |
868 | "apb0_timer", "apb0_p2wi", | |
869 | "apb0_uart", "apb0_1wire", | |
870 | "apb0_i2c"; | |
871 | }; | |
872 | ||
873 | apb0_rst: apb0_rst { | |
874 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
875 | #reset-cells = <1>; | |
876 | }; | |
a42ea603 HG |
877 | }; |
878 | ||
81ee429f MR |
879 | cpucfg@01f01c00 { |
880 | compatible = "allwinner,sun6i-a31-cpuconfig"; | |
881 | reg = <0x01f01c00 0x300>; | |
882 | }; | |
209394ae BB |
883 | |
884 | r_pio: pinctrl@01f02c00 { | |
885 | compatible = "allwinner,sun6i-a31-r-pinctrl"; | |
886 | reg = <0x01f02c00 0x400>; | |
887 | interrupts = <0 45 4>, | |
888 | <0 46 4>; | |
889 | clocks = <&apb0_gates 0>; | |
890 | resets = <&apb0_rst 0>; | |
891 | gpio-controller; | |
892 | interrupt-controller; | |
7d4ff96d | 893 | #interrupt-cells = <2>; |
209394ae BB |
894 | #size-cells = <0>; |
895 | #gpio-cells = <3>; | |
896 | }; | |
8aed3b31 MR |
897 | }; |
898 | }; |