[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / sun6i-a31.dtsi

/*
 * Copyright 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "skeleton.dtsi"

/ {
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
	};


	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};

		cpu@2 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <3>;
		};
	};

	memory {
		reg = <0x40000000 0x80000000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc24M: osc24M {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};

		osc32k: osc32k {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		pll1: pll1@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
		};

		pll6: clk@01c20028 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-pll6-clk";
			reg = <0x01c20028 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll6";
		};

		cpu: cpu@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-cpu-clk";
			reg = <0x01c20050 0x4>;

			/*
			 * PLL1 is listed twice here.
			 * While it looks suspicious, it's actually documented
			 * that way both in the datasheet and in the code from
			 * Allwinner.
			 */
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
		};

		axi: axi@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-axi-clk";
			reg = <0x01c20050 0x4>;
			clocks = <&cpu>;
		};

		ahb1_mux: ahb1_mux@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
		};

		ahb1: ahb1@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-ahb-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb1_mux>;
		};

		ahb1_gates: ahb1_gates@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb1>;
			clock-output-names = "ahb1_mipidsi", "ahb1_ss",
					"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
					"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
					"ahb1_nand0", "ahb1_sdram",
					"ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
					"ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
					"ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
					"ahb1_ehci1", "ahb1_ohci0",
					"ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
					"ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
					"ahb1_hdmi", "ahb1_de0", "ahb1_de1",
					"ahb1_fe0", "ahb1_fe1", "ahb1_mp",
					"ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
					"ahb1_drc0", "ahb1_drc1";
		};

		apb1: apb1@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb1>;
		};

		apb1_gates: apb1_gates@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun6i-a31-apb1-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb1>;
			clock-output-names = "apb1_codec", "apb1_digital_mic",
					"apb1_pio", "apb1_daudio0",
					"apb1_daudio1";
		};

		apb2_mux: apb2_mux@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb1-mux-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
		};

		apb2: apb2@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-apb2-div-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&apb2_mux>;
		};

		apb2_gates: apb2_gates@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun6i-a31-apb2-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb2>;
			clock-output-names = "apb2_i2c0", "apb2_i2c1",
					"apb2_i2c2", "apb2_i2c3", "apb2_uart0",
					"apb2_uart1", "apb2_uart2", "apb2_uart3",
					"apb2_uart4", "apb2_uart5";
		};

		spi0_clk: clk@01c200a0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200a0 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi0";
		};

		spi1_clk: clk@01c200a4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200a4 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi1";
		};

		spi2_clk: clk@01c200a8 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200a8 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi2";
		};

		spi3_clk: clk@01c200ac {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200ac 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi3";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun6i-a31-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <0 11 4>,
				     <0 15 4>,
				     <0 16 4>,
				     <0 17 4>;
			clocks = <&apb1_gates 5>;
			gpio-controller;
			interrupt-controller;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PH20", "PH21";
				allwinner,function = "uart0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};
		};

		ahb1_rst: reset@01c202c0 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-ahb1-reset";
			reg = <0x01c202c0 0xc>;
		};

		apb1_rst: reset@01c202d0 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x01c202d0 0x4>;
		};

		apb2_rst: reset@01c202d8 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x01c202d8 0x4>;
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-timer";
			reg = <0x01c20c00 0xa0>;
			interrupts = <0 18 4>,
				     <0 19 4>,
				     <0 20 4>,
				     <0 21 4>,
				     <0 22 4>;
			clocks = <&osc24M>;
		};

		wdt1: watchdog@01c20ca0 {
			compatible = "allwinner,sun6i-wdt";
			reg = <0x01c20ca0 0x20>;
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <0 0 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 16>;
			resets = <&apb2_rst 16>;
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <0 1 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 17>;
			resets = <&apb2_rst 17>;
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <0 2 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 18>;
			resets = <&apb2_rst 18>;
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <0 3 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 19>;
			resets = <&apb2_rst 19>;
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <0 4 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 20>;
			resets = <&apb2_rst 20>;
			status = "disabled";
		};

		uart5: serial@01c29400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29400 0x400>;
			interrupts = <0 5 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 21>;
			resets = <&apb2_rst 21>;
			status = "disabled";
		};

		gic: interrupt-controller@01c81000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x1000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <1 9 0xf04>;
		};

		cpucfg@01f01c00 {
			compatible = "allwinner,sun6i-a31-cpuconfig";
			reg = <0x01f01c00 0x300>;
		};

		prcm@01f01c00 {
			compatible = "allwinner,sun6i-a31-prcm";
			reg = <0x01f01400 0x200>;
		};
	};
};
Commit	Line	Data
8aed3b31 MR	1	/*
	2	* Copyright 2013 Maxime Ripard
	3	*
	4	* Maxime Ripard <maxime.ripard@free-electrons.com>
	5	*
	6	* The code contained herein is licensed under the GNU General Public
	7	* License. You may obtain a copy of the GNU General Public License
	8	* Version 2 or later at the following locations:
	9	*
	10	* http://www.opensource.org/licenses/gpl-license.html
	11	* http://www.gnu.org/copyleft/gpl.html
	12	*/
	13
	14	/include/ "skeleton.dtsi"
	15
	16	/ {
	17	interrupt-parent = <&gic>;
	18
54428d40 MR	19	aliases {
	20	serial0 = &uart0;
	21	serial1 = &uart1;
	22	serial2 = &uart2;
	23	serial3 = &uart3;
	24	serial4 = &uart4;
	25	serial5 = &uart5;
	26	};
	27
	28
8aed3b31 MR	29	cpus {
	30	#address-cells = <1>;
	31	#size-cells = <0>;
	32
	33	cpu@0 {
	34	compatible = "arm,cortex-a7";
	35	device_type = "cpu";
	36	reg = <0>;
	37	};
	38
	39	cpu@1 {
	40	compatible = "arm,cortex-a7";
	41	device_type = "cpu";
	42	reg = <1>;
	43	};
	44
	45	cpu@2 {
	46	compatible = "arm,cortex-a7";
	47	device_type = "cpu";
	48	reg = <2>;
	49	};
	50
	51	cpu@3 {
	52	compatible = "arm,cortex-a7";
	53	device_type = "cpu";
	54	reg = <3>;
	55	};
	56	};
	57
	58	memory {
	59	reg = <0x40000000 0x80000000>;
	60	};
	61
	62	clocks {
	63	#address-cells = <1>;
98096560 MR	64	#size-cells = <1>;
98096560 MR	65	ranges;
8aed3b31	66
98096560	67	osc24M: osc24M {
8aed3b31 MR	68	#clock-cells = <0>;
	69	compatible = "fixed-clock";
	70	clock-frequency = <24000000>;
	71	};
98096560 MR	72
	73	osc32k: osc32k {
	74	#clock-cells = <0>;
	75	compatible = "fixed-clock";
	76	clock-frequency = <32768>;
	77	};
	78
	79	pll1: pll1@01c20000 {
	80	#clock-cells = <0>;
	81	compatible = "allwinner,sun6i-a31-pll1-clk";
	82	reg = <0x01c20000 0x4>;
	83	clocks = <&osc24M>;
	84	};
	85
b0a09c75	86	pll6: clk@01c20028 {
98096560	87	#clock-cells = <0>;
b0a09c75 MR	88	compatible = "allwinner,sun6i-a31-pll6-clk";
	89	reg = <0x01c20028 0x4>;
	90	clocks = <&osc24M>;
	91	clock-output-names = "pll6";
98096560 MR	92	};
	93
	94	cpu: cpu@01c20050 {
	95	#clock-cells = <0>;
	96	compatible = "allwinner,sun4i-cpu-clk";
	97	reg = <0x01c20050 0x4>;
	98
	99	/*
	100	* PLL1 is listed twice here.
	101	* While it looks suspicious, it's actually documented
	102	* that way both in the datasheet and in the code from
	103	* Allwinner.
	104	*/
	105	clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
	106	};
	107
	108	axi: axi@01c20050 {
	109	#clock-cells = <0>;
	110	compatible = "allwinner,sun4i-axi-clk";
	111	reg = <0x01c20050 0x4>;
	112	clocks = <&cpu>;
	113	};
	114
	115	ahb1_mux: ahb1_mux@01c20054 {
	116	#clock-cells = <0>;
	117	compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
	118	reg = <0x01c20054 0x4>;
	119	clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
	120	};
	121
	122	ahb1: ahb1@01c20054 {
	123	#clock-cells = <0>;
	124	compatible = "allwinner,sun4i-ahb-clk";
	125	reg = <0x01c20054 0x4>;
	126	clocks = <&ahb1_mux>;
	127	};
	128
	129	ahb1_gates: ahb1_gates@01c20060 {
	130	#clock-cells = <1>;
	131	compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
	132	reg = <0x01c20060 0x8>;
	133	clocks = <&ahb1>;
	134	clock-output-names = "ahb1_mipidsi", "ahb1_ss",
	135	"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
	136	"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
	137	"ahb1_nand0", "ahb1_sdram",
	138	"ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
	139	"ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
	140	"ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
	141	"ahb1_ehci1", "ahb1_ohci0",
	142	"ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
	143	"ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
	144	"ahb1_hdmi", "ahb1_de0", "ahb1_de1",
	145	"ahb1_fe0", "ahb1_fe1", "ahb1_mp",
	146	"ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
	147	"ahb1_drc0", "ahb1_drc1";
	148	};
	149
	150	apb1: apb1@01c20054 {
	151	#clock-cells = <0>;
	152	compatible = "allwinner,sun4i-apb0-clk";
	153	reg = <0x01c20054 0x4>;
	154	clocks = <&ahb1>;
	155	};
156
157	apb1_gates: apb1_gates@01c20060 {
158	#clock-cells = <1>;
159	compatible = "allwinner,sun6i-a31-apb1-gates-clk";
160	reg = <0x01c20068 0x4>;
161	clocks = <&apb1>;
162	clock-output-names = "apb1_codec", "apb1_digital_mic",
163	"apb1_pio", "apb1_daudio0",
164	"apb1_daudio1";
165	};
166
167	apb2_mux: apb2_mux@01c20058 {
168	#clock-cells = <0>;
169	compatible = "allwinner,sun4i-apb1-mux-clk";
170	reg = <0x01c20058 0x4>;
171	clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
172	};
173
174	apb2: apb2@01c20058 {
175	#clock-cells = <0>;
176	compatible = "allwinner,sun6i-a31-apb2-div-clk";
177	reg = <0x01c20058 0x4>;
178	clocks = <&apb2_mux>;
179	};
180
181	apb2_gates: apb2_gates@01c2006c {
182	#clock-cells = <1>;
183	compatible = "allwinner,sun6i-a31-apb2-gates-clk";
439d9f58	184	reg = <0x01c2006c 0x4>;
98096560 MR	185	clocks = <&apb2>;
	186	clock-output-names = "apb2_i2c0", "apb2_i2c1",
	187	"apb2_i2c2", "apb2_i2c3", "apb2_uart0",
	188	"apb2_uart1", "apb2_uart2", "apb2_uart3",
	189	"apb2_uart4", "apb2_uart5";
	190	};
b0a09c75 MR	191
	192	spi0_clk: clk@01c200a0 {
	193	#clock-cells = <0>;
	194	compatible = "allwinner,sun4i-mod0-clk";
	195	reg = <0x01c200a0 0x4>;
	196	clocks = <&osc24M>, <&pll6>;
	197	clock-output-names = "spi0";
	198	};
	199
	200	spi1_clk: clk@01c200a4 {
	201	#clock-cells = <0>;
	202	compatible = "allwinner,sun4i-mod0-clk";
	203	reg = <0x01c200a4 0x4>;
	204	clocks = <&osc24M>, <&pll6>;
	205	clock-output-names = "spi1";
	206	};
	207
	208	spi2_clk: clk@01c200a8 {
	209	#clock-cells = <0>;
	210	compatible = "allwinner,sun4i-mod0-clk";
	211	reg = <0x01c200a8 0x4>;
	212	clocks = <&osc24M>, <&pll6>;
	213	clock-output-names = "spi2";
	214	};
	215
	216	spi3_clk: clk@01c200ac {
	217	#clock-cells = <0>;
	218	compatible = "allwinner,sun4i-mod0-clk";
	219	reg = <0x01c200ac 0x4>;
	220	clocks = <&osc24M>, <&pll6>;
	221	clock-output-names = "spi3";
	222	};
8aed3b31 MR	223	};
	224
	225	soc@01c00000 {
	226	compatible = "simple-bus";
	227	#address-cells = <1>;
	228	#size-cells = <1>;
	229	ranges;
	230
140e1721 MR	231	pio: pinctrl@01c20800 {
	232	compatible = "allwinner,sun6i-a31-pinctrl";
	233	reg = <0x01c20800 0x400>;
6f97dc8d MR	234	interrupts = <0 11 4>,
	235	<0 15 4>,
	236	<0 16 4>,
	237	<0 17 4>;
98096560	238	clocks = <&apb1_gates 5>;
140e1721 MR	239	gpio-controller;
	240	interrupt-controller;
	241	#address-cells = <1>;
	242	#size-cells = <0>;
	243	#gpio-cells = <3>;
ab4238cd MR	244
	245	uart0_pins_a: uart0@0 {
	246	allwinner,pins = "PH20", "PH21";
	247	allwinner,function = "uart0";
	248	allwinner,drive = <0>;
	249	allwinner,pull = <0>;
	250	};
140e1721 MR	251	};
140e1721 MR	252
24a661e9 MR	253	ahb1_rst: reset@01c202c0 {
	254	#reset-cells = <1>;
	255	compatible = "allwinner,sun6i-a31-ahb1-reset";
	256	reg = <0x01c202c0 0xc>;
	257	};
	258
	259	apb1_rst: reset@01c202d0 {
	260	#reset-cells = <1>;
	261	compatible = "allwinner,sun6i-a31-clock-reset";
	262	reg = <0x01c202d0 0x4>;
	263	};
	264
	265	apb2_rst: reset@01c202d8 {
	266	#reset-cells = <1>;
	267	compatible = "allwinner,sun6i-a31-clock-reset";
	268	reg = <0x01c202d8 0x4>;
	269	};
	270
8aed3b31 MR	271	timer@01c20c00 {
	272	compatible = "allwinner,sun4i-timer";
	273	reg = <0x01c20c00 0xa0>;
6f97dc8d MR	274	interrupts = <0 18 4>,
	275	<0 19 4>,
	276	<0 20 4>,
	277	<0 21 4>,
	278	<0 22 4>;
98096560	279	clocks = <&osc24M>;
8aed3b31 MR	280	};
	281
	282	wdt1: watchdog@01c20ca0 {
	283	compatible = "allwinner,sun6i-wdt";
	284	reg = <0x01c20ca0 0x20>;
	285	};
	286
	287	uart0: serial@01c28000 {
	288	compatible = "snps,dw-apb-uart";
	289	reg = <0x01c28000 0x400>;
6f97dc8d	290	interrupts = <0 0 4>;
8aed3b31 MR	291	reg-shift = <2>;
8aed3b31 MR	292	reg-io-width = <4>;
98096560	293	clocks = <&apb2_gates 16>;
24a661e9	294	resets = <&apb2_rst 16>;
8aed3b31 MR	295	status = "disabled";
	296	};
	297
	298	uart1: serial@01c28400 {
	299	compatible = "snps,dw-apb-uart";
	300	reg = <0x01c28400 0x400>;
6f97dc8d	301	interrupts = <0 1 4>;
8aed3b31 MR	302	reg-shift = <2>;
8aed3b31 MR	303	reg-io-width = <4>;
98096560	304	clocks = <&apb2_gates 17>;
24a661e9	305	resets = <&apb2_rst 17>;
8aed3b31 MR	306	status = "disabled";
	307	};
	308
	309	uart2: serial@01c28800 {
	310	compatible = "snps,dw-apb-uart";
	311	reg = <0x01c28800 0x400>;
6f97dc8d	312	interrupts = <0 2 4>;
8aed3b31 MR	313	reg-shift = <2>;
8aed3b31 MR	314	reg-io-width = <4>;
98096560	315	clocks = <&apb2_gates 18>;
24a661e9	316	resets = <&apb2_rst 18>;
8aed3b31 MR	317	status = "disabled";
	318	};
	319
	320	uart3: serial@01c28c00 {
	321	compatible = "snps,dw-apb-uart";
	322	reg = <0x01c28c00 0x400>;
6f97dc8d	323	interrupts = <0 3 4>;
8aed3b31 MR	324	reg-shift = <2>;
8aed3b31 MR	325	reg-io-width = <4>;
98096560	326	clocks = <&apb2_gates 19>;
24a661e9	327	resets = <&apb2_rst 19>;
8aed3b31 MR	328	status = "disabled";
	329	};
	330
	331	uart4: serial@01c29000 {
	332	compatible = "snps,dw-apb-uart";
	333	reg = <0x01c29000 0x400>;
6f97dc8d	334	interrupts = <0 4 4>;
8aed3b31 MR	335	reg-shift = <2>;
8aed3b31 MR	336	reg-io-width = <4>;
98096560	337	clocks = <&apb2_gates 20>;
24a661e9	338	resets = <&apb2_rst 20>;
8aed3b31 MR	339	status = "disabled";
	340	};
	341
	342	uart5: serial@01c29400 {
	343	compatible = "snps,dw-apb-uart";
	344	reg = <0x01c29400 0x400>;
6f97dc8d	345	interrupts = <0 5 4>;
8aed3b31 MR	346	reg-shift = <2>;
8aed3b31 MR	347	reg-io-width = <4>;
98096560	348	clocks = <&apb2_gates 21>;
24a661e9	349	resets = <&apb2_rst 21>;
8aed3b31 MR	350	status = "disabled";
	351	};
	352
	353	gic: interrupt-controller@01c81000 {
	354	compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
	355	reg = <0x01c81000 0x1000>,
	356	<0x01c82000 0x1000>,
	357	<0x01c84000 0x2000>,
	358	<0x01c86000 0x2000>;
	359	interrupt-controller;
	360	#interrupt-cells = <3>;
	361	interrupts = <1 9 0xf04>;
	362	};
81ee429f MR	363
	364	cpucfg@01f01c00 {
	365	compatible = "allwinner,sun6i-a31-cpuconfig";
	366	reg = <0x01f01c00 0x300>;
	367	};
	368
	369	prcm@01f01c00 {
	370	compatible = "allwinner,sun6i-a31-prcm";
	371	reg = <0x01f01400 0x200>;
	372	};
8aed3b31 MR	373	};
8aed3b31 MR	374	};