[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / sun6i-a31.dtsi

/*
 * Copyright 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "skeleton.dtsi"

/ {
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
	};


	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};

		cpu@2 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <3>;
		};
	};

	memory {
		reg = <0x40000000 0x80000000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc24M: osc24M {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};

		osc32k: clk@0 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};

		pll1: clk@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll1";
		};

		pll6: clk@01c20028 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-pll6-clk";
			reg = <0x01c20028 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll6";
		};

		cpu: cpu@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-cpu-clk";
			reg = <0x01c20050 0x4>;

			/*
			 * PLL1 is listed twice here.
			 * While it looks suspicious, it's actually documented
			 * that way both in the datasheet and in the code from
			 * Allwinner.
			 */
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
			clock-output-names = "cpu";
		};

		axi: axi@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-axi-clk";
			reg = <0x01c20050 0x4>;
			clocks = <&cpu>;
			clock-output-names = "axi";
		};

		ahb1_mux: ahb1_mux@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
			clock-output-names = "ahb1_mux";
		};

		ahb1: ahb1@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-ahb-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb1_mux>;
			clock-output-names = "ahb1";
		};

		ahb1_gates: clk@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb1>;
			clock-output-names = "ahb1_mipidsi", "ahb1_ss",
					"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
					"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
					"ahb1_nand0", "ahb1_sdram",
					"ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
					"ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
					"ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
					"ahb1_ehci1", "ahb1_ohci0",
					"ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
					"ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
					"ahb1_hdmi", "ahb1_de0", "ahb1_de1",
					"ahb1_fe0", "ahb1_fe1", "ahb1_mp",
					"ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
					"ahb1_drc0", "ahb1_drc1";
		};

		apb1: apb1@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb1>;
			clock-output-names = "apb1";
		};

		apb1_gates: clk@01c20068 {
			#clock-cells = <1>;
			compatible = "allwinner,sun6i-a31-apb1-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb1>;
			clock-output-names = "apb1_codec", "apb1_digital_mic",
					"apb1_pio", "apb1_daudio0",
					"apb1_daudio1";
		};

		apb2_mux: apb2_mux@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb1-mux-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
			clock-output-names = "apb2_mux";
		};

		apb2: apb2@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-apb2-div-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&apb2_mux>;
			clock-output-names = "apb2";
		};

		apb2_gates: clk@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun6i-a31-apb2-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb2>;
			clock-output-names = "apb2_i2c0", "apb2_i2c1",
					"apb2_i2c2", "apb2_i2c3", "apb2_uart0",
					"apb2_uart1", "apb2_uart2", "apb2_uart3",
					"apb2_uart4", "apb2_uart5";
		};

		spi0_clk: clk@01c200a0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a0 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi0";
		};

		spi1_clk: clk@01c200a4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a4 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi1";
		};

		spi2_clk: clk@01c200a8 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a8 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi2";
		};

		spi3_clk: clk@01c200ac {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200ac 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi3";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		nmi_intc: interrupt-controller@01f00c0c {
			compatible = "allwinner,sun6i-a31-sc-nmi";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x01f00c0c 0x38>;
			interrupts = <0 32 4>;
		};

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun6i-a31-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <0 11 4>,
				     <0 15 4>,
				     <0 16 4>,
				     <0 17 4>;
			clocks = <&apb1_gates 5>;
			gpio-controller;
			interrupt-controller;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PH20", "PH21";
				allwinner,function = "uart0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c0_pins_a: i2c0@0 {
				allwinner,pins = "PH14", "PH15";
				allwinner,function = "i2c0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c1_pins_a: i2c1@0 {
				allwinner,pins = "PH16", "PH17";
				allwinner,function = "i2c1";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c2_pins_a: i2c2@0 {
				allwinner,pins = "PH18", "PH19";
				allwinner,function = "i2c2";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};
		};

		ahb1_rst: reset@01c202c0 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-ahb1-reset";
			reg = <0x01c202c0 0xc>;
		};

		apb1_rst: reset@01c202d0 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x01c202d0 0x4>;
		};

		apb2_rst: reset@01c202d8 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x01c202d8 0x4>;
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x01c20c00 0xa0>;
			interrupts = <0 18 4>,
				     <0 19 4>,
				     <0 20 4>,
				     <0 21 4>,
				     <0 22 4>;
			clocks = <&osc24M>;
		};

		wdt1: watchdog@01c20ca0 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x01c20ca0 0x20>;
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <0 0 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 16>;
			resets = <&apb2_rst 16>;
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <0 1 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 17>;
			resets = <&apb2_rst 17>;
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <0 2 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 18>;
			resets = <&apb2_rst 18>;
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <0 3 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 19>;
			resets = <&apb2_rst 19>;
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <0 4 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 20>;
			resets = <&apb2_rst 20>;
			status = "disabled";
		};

		uart5: serial@01c29400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29400 0x400>;
			interrupts = <0 5 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 21>;
			resets = <&apb2_rst 21>;
			status = "disabled";
		};

		i2c0: i2c@01c2ac00 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <0 6 4>;
			clocks = <&apb2_gates 0>;
			clock-frequency = <100000>;
			resets = <&apb2_rst 0>;
			status = "disabled";
		};

		i2c1: i2c@01c2b000 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <0 7 4>;
			clocks = <&apb2_gates 1>;
			clock-frequency = <100000>;
			resets = <&apb2_rst 1>;
			status = "disabled";
		};

		i2c2: i2c@01c2b400 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <0 8 4>;
			clocks = <&apb2_gates 2>;
			clock-frequency = <100000>;
			resets = <&apb2_rst 2>;
			status = "disabled";
		};

		i2c3: i2c@01c2b800 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b800 0x400>;
			interrupts = <0 9 4>;
			clocks = <&apb2_gates 3>;
			clock-frequency = <100000>;
			resets = <&apb2_rst 3>;
			status = "disabled";
		};

		spi0: spi@01c68000 {
			compatible = "allwinner,sun6i-a31-spi";
			reg = <0x01c68000 0x1000>;
			interrupts = <0 65 4>;
			clocks = <&ahb1_gates 20>, <&spi0_clk>;
			clock-names = "ahb", "mod";
			resets = <&ahb1_rst 20>;
			status = "disabled";
		};

		spi1: spi@01c69000 {
			compatible = "allwinner,sun6i-a31-spi";
			reg = <0x01c69000 0x1000>;
			interrupts = <0 66 4>;
			clocks = <&ahb1_gates 21>, <&spi1_clk>;
			clock-names = "ahb", "mod";
			resets = <&ahb1_rst 21>;
			status = "disabled";
		};

		spi2: spi@01c6a000 {
			compatible = "allwinner,sun6i-a31-spi";
			reg = <0x01c6a000 0x1000>;
			interrupts = <0 67 4>;
			clocks = <&ahb1_gates 22>, <&spi2_clk>;
			clock-names = "ahb", "mod";
			resets = <&ahb1_rst 22>;
			status = "disabled";
		};

		spi3: spi@01c6b000 {
			compatible = "allwinner,sun6i-a31-spi";
			reg = <0x01c6b000 0x1000>;
			interrupts = <0 68 4>;
			clocks = <&ahb1_gates 23>, <&spi3_clk>;
			clock-names = "ahb", "mod";
			resets = <&ahb1_rst 23>;
			status = "disabled";
		};

		gic: interrupt-controller@01c81000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x1000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <1 9 0xf04>;
		};

		cpucfg@01f01c00 {
			compatible = "allwinner,sun6i-a31-cpuconfig";
			reg = <0x01f01c00 0x300>;
		};

		prcm@01f01c00 {
			compatible = "allwinner,sun6i-a31-prcm";
			reg = <0x01f01400 0x200>;
		};
	};
};
Commit	Line	Data
8aed3b31 MR	1	/*
	2	* Copyright 2013 Maxime Ripard
	3	*
	4	* Maxime Ripard <maxime.ripard@free-electrons.com>
	5	*
	6	* The code contained herein is licensed under the GNU General Public
	7	* License. You may obtain a copy of the GNU General Public License
	8	* Version 2 or later at the following locations:
	9	*
	10	* http://www.opensource.org/licenses/gpl-license.html
	11	* http://www.gnu.org/copyleft/gpl.html
	12	*/
	13
	14	/include/ "skeleton.dtsi"
	15
	16	/ {
	17	interrupt-parent = <&gic>;
	18
54428d40 MR	19	aliases {
	20	serial0 = &uart0;
	21	serial1 = &uart1;
	22	serial2 = &uart2;
	23	serial3 = &uart3;
	24	serial4 = &uart4;
	25	serial5 = &uart5;
	26	};
	27
	28
8aed3b31 MR	29	cpus {
	30	#address-cells = <1>;
	31	#size-cells = <0>;
	32
	33	cpu@0 {
	34	compatible = "arm,cortex-a7";
	35	device_type = "cpu";
	36	reg = <0>;
	37	};
	38
	39	cpu@1 {
	40	compatible = "arm,cortex-a7";
	41	device_type = "cpu";
	42	reg = <1>;
	43	};
	44
	45	cpu@2 {
	46	compatible = "arm,cortex-a7";
	47	device_type = "cpu";
	48	reg = <2>;
	49	};
	50
	51	cpu@3 {
	52	compatible = "arm,cortex-a7";
	53	device_type = "cpu";
	54	reg = <3>;
	55	};
	56	};
	57
	58	memory {
	59	reg = <0x40000000 0x80000000>;
	60	};
	61
	62	clocks {
	63	#address-cells = <1>;
98096560 MR	64	#size-cells = <1>;
98096560 MR	65	ranges;
8aed3b31	66
98096560	67	osc24M: osc24M {
8aed3b31 MR	68	#clock-cells = <0>;
	69	compatible = "fixed-clock";
	70	clock-frequency = <24000000>;
	71	};
98096560	72
7b5b2909	73	osc32k: clk@0 {
98096560 MR	74	#clock-cells = <0>;
	75	compatible = "fixed-clock";
	76	clock-frequency = <32768>;
7b5b2909	77	clock-output-names = "osc32k";
98096560 MR	78	};
98096560 MR	79
7b5b2909	80	pll1: clk@01c20000 {
98096560 MR	81	#clock-cells = <0>;
	82	compatible = "allwinner,sun6i-a31-pll1-clk";
	83	reg = <0x01c20000 0x4>;
	84	clocks = <&osc24M>;
7b5b2909	85	clock-output-names = "pll1";
98096560 MR	86	};
98096560 MR	87
b0a09c75	88	pll6: clk@01c20028 {
98096560	89	#clock-cells = <0>;
b0a09c75 MR	90	compatible = "allwinner,sun6i-a31-pll6-clk";
	91	reg = <0x01c20028 0x4>;
	92	clocks = <&osc24M>;
	93	clock-output-names = "pll6";
98096560 MR	94	};
	95
	96	cpu: cpu@01c20050 {
	97	#clock-cells = <0>;
bf6534a1	98	compatible = "allwinner,sun4i-a10-cpu-clk";
98096560 MR	99	reg = <0x01c20050 0x4>;
	100
	101	/*
	102	* PLL1 is listed twice here.
	103	* While it looks suspicious, it's actually documented
	104	* that way both in the datasheet and in the code from
	105	* Allwinner.
	106	*/
	107	clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
7b5b2909	108	clock-output-names = "cpu";
98096560 MR	109	};
	110
	111	axi: axi@01c20050 {
	112	#clock-cells = <0>;
bf6534a1	113	compatible = "allwinner,sun4i-a10-axi-clk";
98096560 MR	114	reg = <0x01c20050 0x4>;
98096560 MR	115	clocks = <&cpu>;
7b5b2909	116	clock-output-names = "axi";
98096560 MR	117	};
	118
	119	ahb1_mux: ahb1_mux@01c20054 {
	120	#clock-cells = <0>;
	121	compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
	122	reg = <0x01c20054 0x4>;
	123	clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
7b5b2909	124	clock-output-names = "ahb1_mux";
98096560 MR	125	};
	126
	127	ahb1: ahb1@01c20054 {
	128	#clock-cells = <0>;
bf6534a1	129	compatible = "allwinner,sun4i-a10-ahb-clk";
98096560 MR	130	reg = <0x01c20054 0x4>;
98096560 MR	131	clocks = <&ahb1_mux>;
7b5b2909	132	clock-output-names = "ahb1";
98096560 MR	133	};
98096560 MR	134
7b5b2909	135	ahb1_gates: clk@01c20060 {
98096560 MR	136	#clock-cells = <1>;
	137	compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
	138	reg = <0x01c20060 0x8>;
	139	clocks = <&ahb1>;
	140	clock-output-names = "ahb1_mipidsi", "ahb1_ss",
	141	"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
	142	"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
	143	"ahb1_nand0", "ahb1_sdram",
	144	"ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
	145	"ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
	146	"ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
	147	"ahb1_ehci1", "ahb1_ohci0",
	148	"ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
	149	"ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
	150	"ahb1_hdmi", "ahb1_de0", "ahb1_de1",
	151	"ahb1_fe0", "ahb1_fe1", "ahb1_mp",
	152	"ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
	153	"ahb1_drc0", "ahb1_drc1";
	154	};
	155
	156	apb1: apb1@01c20054 {
	157	#clock-cells = <0>;
bf6534a1	158	compatible = "allwinner,sun4i-a10-apb0-clk";
98096560 MR	159	reg = <0x01c20054 0x4>;
98096560 MR	160	clocks = <&ahb1>;
7b5b2909	161	clock-output-names = "apb1";
98096560 MR	162	};
98096560 MR	163
7b5b2909	164	apb1_gates: clk@01c20068 {
98096560 MR	165	#clock-cells = <1>;
	166	compatible = "allwinner,sun6i-a31-apb1-gates-clk";
	167	reg = <0x01c20068 0x4>;
	168	clocks = <&apb1>;
	169	clock-output-names = "apb1_codec", "apb1_digital_mic",
	170	"apb1_pio", "apb1_daudio0",
	171	"apb1_daudio1";
	172	};
	173
	174	apb2_mux: apb2_mux@01c20058 {
	175	#clock-cells = <0>;
bf6534a1	176	compatible = "allwinner,sun4i-a10-apb1-mux-clk";
98096560 MR	177	reg = <0x01c20058 0x4>;
98096560 MR	178	clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
7b5b2909	179	clock-output-names = "apb2_mux";
98096560 MR	180	};
	181
	182	apb2: apb2@01c20058 {
	183	#clock-cells = <0>;
	184	compatible = "allwinner,sun6i-a31-apb2-div-clk";
	185	reg = <0x01c20058 0x4>;
	186	clocks = <&apb2_mux>;
7b5b2909	187	clock-output-names = "apb2";
98096560 MR	188	};
98096560 MR	189
7b5b2909	190	apb2_gates: clk@01c2006c {
98096560 MR	191	#clock-cells = <1>;
98096560 MR	192	compatible = "allwinner,sun6i-a31-apb2-gates-clk";
439d9f58	193	reg = <0x01c2006c 0x4>;
98096560 MR	194	clocks = <&apb2>;
	195	clock-output-names = "apb2_i2c0", "apb2_i2c1",
	196	"apb2_i2c2", "apb2_i2c3", "apb2_uart0",
	197	"apb2_uart1", "apb2_uart2", "apb2_uart3",
	198	"apb2_uart4", "apb2_uart5";
	199	};
b0a09c75 MR	200
	201	spi0_clk: clk@01c200a0 {
	202	#clock-cells = <0>;
225b0216	203	compatible = "allwinner,sun4i-a10-mod0-clk";
b0a09c75 MR	204	reg = <0x01c200a0 0x4>;
	205	clocks = <&osc24M>, <&pll6>;
	206	clock-output-names = "spi0";
	207	};
	208
	209	spi1_clk: clk@01c200a4 {
	210	#clock-cells = <0>;
225b0216	211	compatible = "allwinner,sun4i-a10-mod0-clk";
b0a09c75 MR	212	reg = <0x01c200a4 0x4>;
	213	clocks = <&osc24M>, <&pll6>;
	214	clock-output-names = "spi1";
	215	};
	216
	217	spi2_clk: clk@01c200a8 {
	218	#clock-cells = <0>;
225b0216	219	compatible = "allwinner,sun4i-a10-mod0-clk";
b0a09c75 MR	220	reg = <0x01c200a8 0x4>;
	221	clocks = <&osc24M>, <&pll6>;
	222	clock-output-names = "spi2";
	223	};
	224
	225	spi3_clk: clk@01c200ac {
	226	#clock-cells = <0>;
225b0216	227	compatible = "allwinner,sun4i-a10-mod0-clk";
b0a09c75 MR	228	reg = <0x01c200ac 0x4>;
	229	clocks = <&osc24M>, <&pll6>;
	230	clock-output-names = "spi3";
	231	};
8aed3b31 MR	232	};
	233
	234	soc@01c00000 {
	235	compatible = "simple-bus";
	236	#address-cells = <1>;
	237	#size-cells = <1>;
	238	ranges;
	239
8ff973a2 CC	240	nmi_intc: interrupt-controller@01f00c0c {
	241	compatible = "allwinner,sun6i-a31-sc-nmi";
	242	interrupt-controller;
	243	#interrupt-cells = <2>;
	244	reg = <0x01f00c0c 0x38>;
536a44d4	245	interrupts = <0 32 4>;
8ff973a2 CC	246	};
8ff973a2 CC	247
140e1721 MR	248	pio: pinctrl@01c20800 {
	249	compatible = "allwinner,sun6i-a31-pinctrl";
	250	reg = <0x01c20800 0x400>;
6f97dc8d MR	251	interrupts = <0 11 4>,
	252	<0 15 4>,
	253	<0 16 4>,
	254	<0 17 4>;
98096560	255	clocks = <&apb1_gates 5>;
140e1721 MR	256	gpio-controller;
	257	interrupt-controller;
	258	#address-cells = <1>;
	259	#size-cells = <0>;
	260	#gpio-cells = <3>;
ab4238cd MR	261
	262	uart0_pins_a: uart0@0 {
	263	allwinner,pins = "PH20", "PH21";
	264	allwinner,function = "uart0";
	265	allwinner,drive = <0>;
	266	allwinner,pull = <0>;
	267	};
8be188b8 MR	268
	269	i2c0_pins_a: i2c0@0 {
	270	allwinner,pins = "PH14", "PH15";
	271	allwinner,function = "i2c0";
	272	allwinner,drive = <0>;
	273	allwinner,pull = <0>;
	274	};
	275
	276	i2c1_pins_a: i2c1@0 {
	277	allwinner,pins = "PH16", "PH17";
	278	allwinner,function = "i2c1";
	279	allwinner,drive = <0>;
	280	allwinner,pull = <0>;
	281	};
	282
	283	i2c2_pins_a: i2c2@0 {
	284	allwinner,pins = "PH18", "PH19";
	285	allwinner,function = "i2c2";
	286	allwinner,drive = <0>;
	287	allwinner,pull = <0>;
	288	};
140e1721 MR	289	};
140e1721 MR	290
24a661e9 MR	291	ahb1_rst: reset@01c202c0 {
	292	#reset-cells = <1>;
	293	compatible = "allwinner,sun6i-a31-ahb1-reset";
	294	reg = <0x01c202c0 0xc>;
	295	};
	296
	297	apb1_rst: reset@01c202d0 {
	298	#reset-cells = <1>;
	299	compatible = "allwinner,sun6i-a31-clock-reset";
	300	reg = <0x01c202d0 0x4>;
	301	};
	302
	303	apb2_rst: reset@01c202d8 {
	304	#reset-cells = <1>;
	305	compatible = "allwinner,sun6i-a31-clock-reset";
	306	reg = <0x01c202d8 0x4>;
	307	};
	308
8aed3b31	309	timer@01c20c00 {
b4f26440	310	compatible = "allwinner,sun4i-a10-timer";
8aed3b31	311	reg = <0x01c20c00 0xa0>;
6f97dc8d MR	312	interrupts = <0 18 4>,
	313	<0 19 4>,
	314	<0 20 4>,
	315	<0 21 4>,
	316	<0 22 4>;
98096560	317	clocks = <&osc24M>;
8aed3b31 MR	318	};
	319
	320	wdt1: watchdog@01c20ca0 {
ca5d04d9	321	compatible = "allwinner,sun6i-a31-wdt";
8aed3b31 MR	322	reg = <0x01c20ca0 0x20>;
	323	};
	324
	325	uart0: serial@01c28000 {
	326	compatible = "snps,dw-apb-uart";
	327	reg = <0x01c28000 0x400>;
6f97dc8d	328	interrupts = <0 0 4>;
8aed3b31 MR	329	reg-shift = <2>;
8aed3b31 MR	330	reg-io-width = <4>;
98096560	331	clocks = <&apb2_gates 16>;
24a661e9	332	resets = <&apb2_rst 16>;
8aed3b31 MR	333	status = "disabled";
	334	};
	335
	336	uart1: serial@01c28400 {
	337	compatible = "snps,dw-apb-uart";
	338	reg = <0x01c28400 0x400>;
6f97dc8d	339	interrupts = <0 1 4>;
8aed3b31 MR	340	reg-shift = <2>;
8aed3b31 MR	341	reg-io-width = <4>;
98096560	342	clocks = <&apb2_gates 17>;
24a661e9	343	resets = <&apb2_rst 17>;
8aed3b31 MR	344	status = "disabled";
	345	};
	346
	347	uart2: serial@01c28800 {
	348	compatible = "snps,dw-apb-uart";
	349	reg = <0x01c28800 0x400>;
6f97dc8d	350	interrupts = <0 2 4>;
8aed3b31 MR	351	reg-shift = <2>;
8aed3b31 MR	352	reg-io-width = <4>;
98096560	353	clocks = <&apb2_gates 18>;
24a661e9	354	resets = <&apb2_rst 18>;
8aed3b31 MR	355	status = "disabled";
	356	};
	357
	358	uart3: serial@01c28c00 {
	359	compatible = "snps,dw-apb-uart";
	360	reg = <0x01c28c00 0x400>;
6f97dc8d	361	interrupts = <0 3 4>;
8aed3b31 MR	362	reg-shift = <2>;
8aed3b31 MR	363	reg-io-width = <4>;
98096560	364	clocks = <&apb2_gates 19>;
24a661e9	365	resets = <&apb2_rst 19>;
8aed3b31 MR	366	status = "disabled";
	367	};
	368
	369	uart4: serial@01c29000 {
	370	compatible = "snps,dw-apb-uart";
	371	reg = <0x01c29000 0x400>;
6f97dc8d	372	interrupts = <0 4 4>;
8aed3b31 MR	373	reg-shift = <2>;
8aed3b31 MR	374	reg-io-width = <4>;
98096560	375	clocks = <&apb2_gates 20>;
24a661e9	376	resets = <&apb2_rst 20>;
8aed3b31 MR	377	status = "disabled";
	378	};
	379
	380	uart5: serial@01c29400 {
	381	compatible = "snps,dw-apb-uart";
	382	reg = <0x01c29400 0x400>;
6f97dc8d	383	interrupts = <0 5 4>;
8aed3b31 MR	384	reg-shift = <2>;
8aed3b31 MR	385	reg-io-width = <4>;
98096560	386	clocks = <&apb2_gates 21>;
24a661e9	387	resets = <&apb2_rst 21>;
8aed3b31 MR	388	status = "disabled";
	389	};
	390
96c7cc9b MR	391	i2c0: i2c@01c2ac00 {
	392	compatible = "allwinner,sun6i-a31-i2c";
	393	reg = <0x01c2ac00 0x400>;
	394	interrupts = <0 6 4>;
	395	clocks = <&apb2_gates 0>;
	396	clock-frequency = <100000>;
	397	resets = <&apb2_rst 0>;
	398	status = "disabled";
	399	};
	400
	401	i2c1: i2c@01c2b000 {
	402	compatible = "allwinner,sun6i-a31-i2c";
	403	reg = <0x01c2b000 0x400>;
	404	interrupts = <0 7 4>;
	405	clocks = <&apb2_gates 1>;
	406	clock-frequency = <100000>;
	407	resets = <&apb2_rst 1>;
	408	status = "disabled";
	409	};
	410
	411	i2c2: i2c@01c2b400 {
	412	compatible = "allwinner,sun6i-a31-i2c";
	413	reg = <0x01c2b400 0x400>;
	414	interrupts = <0 8 4>;
	415	clocks = <&apb2_gates 2>;
	416	clock-frequency = <100000>;
	417	resets = <&apb2_rst 2>;
	418	status = "disabled";
	419	};
	420
	421	i2c3: i2c@01c2b800 {
	422	compatible = "allwinner,sun6i-a31-i2c";
	423	reg = <0x01c2b800 0x400>;
	424	interrupts = <0 9 4>;
	425	clocks = <&apb2_gates 3>;
	426	clock-frequency = <100000>;
	427	resets = <&apb2_rst 3>;
	428	status = "disabled";
	429	};
	430
0d6efe33 MR	431	spi0: spi@01c68000 {
	432	compatible = "allwinner,sun6i-a31-spi";
	433	reg = <0x01c68000 0x1000>;
	434	interrupts = <0 65 4>;
	435	clocks = <&ahb1_gates 20>, <&spi0_clk>;
	436	clock-names = "ahb", "mod";
	437	resets = <&ahb1_rst 20>;
	438	status = "disabled";
	439	};
	440
	441	spi1: spi@01c69000 {
	442	compatible = "allwinner,sun6i-a31-spi";
	443	reg = <0x01c69000 0x1000>;
	444	interrupts = <0 66 4>;
	445	clocks = <&ahb1_gates 21>, <&spi1_clk>;
	446	clock-names = "ahb", "mod";
	447	resets = <&ahb1_rst 21>;
	448	status = "disabled";
	449	};
	450
	451	spi2: spi@01c6a000 {
	452	compatible = "allwinner,sun6i-a31-spi";
	453	reg = <0x01c6a000 0x1000>;
	454	interrupts = <0 67 4>;
	455	clocks = <&ahb1_gates 22>, <&spi2_clk>;
	456	clock-names = "ahb", "mod";
	457	resets = <&ahb1_rst 22>;
	458	status = "disabled";
	459	};
	460
	461	spi3: spi@01c6b000 {
	462	compatible = "allwinner,sun6i-a31-spi";
	463	reg = <0x01c6b000 0x1000>;
	464	interrupts = <0 68 4>;
	465	clocks = <&ahb1_gates 23>, <&spi3_clk>;
	466	clock-names = "ahb", "mod";
	467	resets = <&ahb1_rst 23>;
	468	status = "disabled";
	469	};
	470
8aed3b31 MR	471	gic: interrupt-controller@01c81000 {
	472	compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
	473	reg = <0x01c81000 0x1000>,
	474	<0x01c82000 0x1000>,
	475	<0x01c84000 0x2000>,
	476	<0x01c86000 0x2000>;
	477	interrupt-controller;
	478	#interrupt-cells = <3>;
	479	interrupts = <1 9 0xf04>;
	480	};
81ee429f MR	481
	482	cpucfg@01f01c00 {
	483	compatible = "allwinner,sun6i-a31-cpuconfig";
	484	reg = <0x01f01c00 0x300>;
	485	};
	486
	487	prcm@01f01c00 {
	488	compatible = "allwinner,sun6i-a31-prcm";
	489	reg = <0x01f01400 0x200>;
	490	};
8aed3b31 MR	491	};
8aed3b31 MR	492	};