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8aed3b31 MR |
1 | /* |
2 | * Copyright 2013 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
6c3ba724 MR |
6 | * This file is dual-licensed: you can use it either under the terms |
7 | * of the GPL or the X11 license, at your option. Note that this dual | |
8 | * licensing only applies to this file, and not this project as a | |
9 | * whole. | |
8aed3b31 | 10 | * |
5186d83a | 11 | * a) This file is free software; you can redistribute it and/or |
6c3ba724 MR |
12 | * modify it under the terms of the GNU General Public License as |
13 | * published by the Free Software Foundation; either version 2 of the | |
14 | * License, or (at your option) any later version. | |
15 | * | |
5186d83a | 16 | * This file is distributed in the hope that it will be useful, |
6c3ba724 MR |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public | |
5186d83a | 22 | * License along with this file; if not, write to the Free |
6c3ba724 MR |
23 | * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
24 | * MA 02110-1301 USA | |
25 | * | |
26 | * Or, alternatively, | |
27 | * | |
28 | * b) Permission is hereby granted, free of charge, to any person | |
29 | * obtaining a copy of this software and associated documentation | |
30 | * files (the "Software"), to deal in the Software without | |
31 | * restriction, including without limitation the rights to use, | |
32 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
33 | * sell copies of the Software, and to permit persons to whom the | |
34 | * Software is furnished to do so, subject to the following | |
35 | * conditions: | |
36 | * | |
37 | * The above copyright notice and this permission notice shall be | |
38 | * included in all copies or substantial portions of the Software. | |
39 | * | |
40 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
41 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
42 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
43 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
44 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
45 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
46 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
47 | * OTHER DEALINGS IN THE SOFTWARE. | |
8aed3b31 MR |
48 | */ |
49 | ||
50 | /include/ "skeleton.dtsi" | |
51 | ||
52 | / { | |
53 | interrupt-parent = <&gic>; | |
54 | ||
54428d40 MR |
55 | aliases { |
56 | serial0 = &uart0; | |
57 | serial1 = &uart1; | |
58 | serial2 = &uart2; | |
59 | serial3 = &uart3; | |
60 | serial4 = &uart4; | |
61 | serial5 = &uart5; | |
e5073fde | 62 | ethernet0 = &gmac; |
54428d40 MR |
63 | }; |
64 | ||
e53a8b22 HG |
65 | chosen { |
66 | #address-cells = <1>; | |
67 | #size-cells = <1>; | |
68 | ranges; | |
69 | ||
a9f8cda3 HG |
70 | framebuffer@0 { |
71 | compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; | |
72 | allwinner,pipeline = "de_be0-lcd0-hdmi"; | |
678e75d3 | 73 | clocks = <&pll6 0>; |
e53a8b22 HG |
74 | status = "disabled"; |
75 | }; | |
76 | }; | |
54428d40 | 77 | |
8aed3b31 | 78 | cpus { |
ce78e353 | 79 | enable-method = "allwinner,sun6i-a31"; |
8aed3b31 MR |
80 | #address-cells = <1>; |
81 | #size-cells = <0>; | |
82 | ||
83 | cpu@0 { | |
84 | compatible = "arm,cortex-a7"; | |
85 | device_type = "cpu"; | |
86 | reg = <0>; | |
87 | }; | |
88 | ||
89 | cpu@1 { | |
90 | compatible = "arm,cortex-a7"; | |
91 | device_type = "cpu"; | |
92 | reg = <1>; | |
93 | }; | |
94 | ||
95 | cpu@2 { | |
96 | compatible = "arm,cortex-a7"; | |
97 | device_type = "cpu"; | |
98 | reg = <2>; | |
99 | }; | |
100 | ||
101 | cpu@3 { | |
102 | compatible = "arm,cortex-a7"; | |
103 | device_type = "cpu"; | |
104 | reg = <3>; | |
105 | }; | |
106 | }; | |
107 | ||
108 | memory { | |
109 | reg = <0x40000000 0x80000000>; | |
110 | }; | |
111 | ||
b5a10b76 MR |
112 | pmu { |
113 | compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; | |
114 | interrupts = <0 120 4>, | |
115 | <0 121 4>, | |
116 | <0 122 4>, | |
117 | <0 123 4>; | |
118 | }; | |
119 | ||
8aed3b31 MR |
120 | clocks { |
121 | #address-cells = <1>; | |
98096560 MR |
122 | #size-cells = <1>; |
123 | ranges; | |
8aed3b31 | 124 | |
98096560 | 125 | osc24M: osc24M { |
8aed3b31 MR |
126 | #clock-cells = <0>; |
127 | compatible = "fixed-clock"; | |
128 | clock-frequency = <24000000>; | |
129 | }; | |
98096560 | 130 | |
7b5b2909 | 131 | osc32k: clk@0 { |
98096560 MR |
132 | #clock-cells = <0>; |
133 | compatible = "fixed-clock"; | |
134 | clock-frequency = <32768>; | |
7b5b2909 | 135 | clock-output-names = "osc32k"; |
98096560 MR |
136 | }; |
137 | ||
7b5b2909 | 138 | pll1: clk@01c20000 { |
98096560 MR |
139 | #clock-cells = <0>; |
140 | compatible = "allwinner,sun6i-a31-pll1-clk"; | |
141 | reg = <0x01c20000 0x4>; | |
142 | clocks = <&osc24M>; | |
7b5b2909 | 143 | clock-output-names = "pll1"; |
98096560 MR |
144 | }; |
145 | ||
b0a09c75 | 146 | pll6: clk@01c20028 { |
f6c3b046 | 147 | #clock-cells = <1>; |
b0a09c75 MR |
148 | compatible = "allwinner,sun6i-a31-pll6-clk"; |
149 | reg = <0x01c20028 0x4>; | |
150 | clocks = <&osc24M>; | |
f6c3b046 | 151 | clock-output-names = "pll6", "pll6x2"; |
98096560 MR |
152 | }; |
153 | ||
154 | cpu: cpu@01c20050 { | |
155 | #clock-cells = <0>; | |
bf6534a1 | 156 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
98096560 MR |
157 | reg = <0x01c20050 0x4>; |
158 | ||
159 | /* | |
160 | * PLL1 is listed twice here. | |
161 | * While it looks suspicious, it's actually documented | |
162 | * that way both in the datasheet and in the code from | |
163 | * Allwinner. | |
164 | */ | |
165 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; | |
7b5b2909 | 166 | clock-output-names = "cpu"; |
98096560 MR |
167 | }; |
168 | ||
169 | axi: axi@01c20050 { | |
170 | #clock-cells = <0>; | |
bf6534a1 | 171 | compatible = "allwinner,sun4i-a10-axi-clk"; |
98096560 MR |
172 | reg = <0x01c20050 0x4>; |
173 | clocks = <&cpu>; | |
7b5b2909 | 174 | clock-output-names = "axi"; |
98096560 MR |
175 | }; |
176 | ||
177 | ahb1_mux: ahb1_mux@01c20054 { | |
178 | #clock-cells = <0>; | |
179 | compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; | |
180 | reg = <0x01c20054 0x4>; | |
f6c3b046 | 181 | clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; |
7b5b2909 | 182 | clock-output-names = "ahb1_mux"; |
98096560 MR |
183 | }; |
184 | ||
185 | ahb1: ahb1@01c20054 { | |
186 | #clock-cells = <0>; | |
bf6534a1 | 187 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
98096560 MR |
188 | reg = <0x01c20054 0x4>; |
189 | clocks = <&ahb1_mux>; | |
7b5b2909 | 190 | clock-output-names = "ahb1"; |
98096560 MR |
191 | }; |
192 | ||
7b5b2909 | 193 | ahb1_gates: clk@01c20060 { |
98096560 MR |
194 | #clock-cells = <1>; |
195 | compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; | |
196 | reg = <0x01c20060 0x8>; | |
197 | clocks = <&ahb1>; | |
198 | clock-output-names = "ahb1_mipidsi", "ahb1_ss", | |
199 | "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1", | |
200 | "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1", | |
201 | "ahb1_nand0", "ahb1_sdram", | |
202 | "ahb1_gmac", "ahb1_ts", "ahb1_hstimer", | |
203 | "ahb1_spi0", "ahb1_spi1", "ahb1_spi2", | |
204 | "ahb1_spi3", "ahb1_otg", "ahb1_ehci0", | |
205 | "ahb1_ehci1", "ahb1_ohci0", | |
206 | "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve", | |
207 | "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi", | |
208 | "ahb1_hdmi", "ahb1_de0", "ahb1_de1", | |
209 | "ahb1_fe0", "ahb1_fe1", "ahb1_mp", | |
210 | "ahb1_gpu", "ahb1_deu0", "ahb1_deu1", | |
211 | "ahb1_drc0", "ahb1_drc1"; | |
212 | }; | |
213 | ||
214 | apb1: apb1@01c20054 { | |
215 | #clock-cells = <0>; | |
bf6534a1 | 216 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
98096560 MR |
217 | reg = <0x01c20054 0x4>; |
218 | clocks = <&ahb1>; | |
7b5b2909 | 219 | clock-output-names = "apb1"; |
98096560 MR |
220 | }; |
221 | ||
7b5b2909 | 222 | apb1_gates: clk@01c20068 { |
98096560 MR |
223 | #clock-cells = <1>; |
224 | compatible = "allwinner,sun6i-a31-apb1-gates-clk"; | |
225 | reg = <0x01c20068 0x4>; | |
226 | clocks = <&apb1>; | |
227 | clock-output-names = "apb1_codec", "apb1_digital_mic", | |
228 | "apb1_pio", "apb1_daudio0", | |
229 | "apb1_daudio1"; | |
230 | }; | |
231 | ||
74c947ab | 232 | apb2: clk@01c20058 { |
98096560 | 233 | #clock-cells = <0>; |
74c947ab | 234 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
98096560 | 235 | reg = <0x01c20058 0x4>; |
f6c3b046 | 236 | clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; |
7b5b2909 | 237 | clock-output-names = "apb2"; |
98096560 MR |
238 | }; |
239 | ||
7b5b2909 | 240 | apb2_gates: clk@01c2006c { |
98096560 MR |
241 | #clock-cells = <1>; |
242 | compatible = "allwinner,sun6i-a31-apb2-gates-clk"; | |
439d9f58 | 243 | reg = <0x01c2006c 0x4>; |
98096560 MR |
244 | clocks = <&apb2>; |
245 | clock-output-names = "apb2_i2c0", "apb2_i2c1", | |
246 | "apb2_i2c2", "apb2_i2c3", "apb2_uart0", | |
247 | "apb2_uart1", "apb2_uart2", "apb2_uart3", | |
248 | "apb2_uart4", "apb2_uart5"; | |
249 | }; | |
b0a09c75 | 250 | |
adc54c85 HG |
251 | mmc0_clk: clk@01c20088 { |
252 | #clock-cells = <0>; | |
253 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
254 | reg = <0x01c20088 0x4>; | |
f6c3b046 | 255 | clocks = <&osc24M>, <&pll6 0>; |
adc54c85 HG |
256 | clock-output-names = "mmc0"; |
257 | }; | |
258 | ||
259 | mmc1_clk: clk@01c2008c { | |
260 | #clock-cells = <0>; | |
261 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
262 | reg = <0x01c2008c 0x4>; | |
f6c3b046 | 263 | clocks = <&osc24M>, <&pll6 0>; |
adc54c85 HG |
264 | clock-output-names = "mmc1"; |
265 | }; | |
266 | ||
267 | mmc2_clk: clk@01c20090 { | |
268 | #clock-cells = <0>; | |
269 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
270 | reg = <0x01c20090 0x4>; | |
f6c3b046 | 271 | clocks = <&osc24M>, <&pll6 0>; |
adc54c85 HG |
272 | clock-output-names = "mmc2"; |
273 | }; | |
274 | ||
275 | mmc3_clk: clk@01c20094 { | |
276 | #clock-cells = <0>; | |
277 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
278 | reg = <0x01c20094 0x4>; | |
f6c3b046 | 279 | clocks = <&osc24M>, <&pll6 0>; |
adc54c85 HG |
280 | clock-output-names = "mmc3"; |
281 | }; | |
282 | ||
b0a09c75 MR |
283 | spi0_clk: clk@01c200a0 { |
284 | #clock-cells = <0>; | |
225b0216 | 285 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
b0a09c75 | 286 | reg = <0x01c200a0 0x4>; |
f6c3b046 | 287 | clocks = <&osc24M>, <&pll6 0>; |
b0a09c75 MR |
288 | clock-output-names = "spi0"; |
289 | }; | |
290 | ||
291 | spi1_clk: clk@01c200a4 { | |
292 | #clock-cells = <0>; | |
225b0216 | 293 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
b0a09c75 | 294 | reg = <0x01c200a4 0x4>; |
f6c3b046 | 295 | clocks = <&osc24M>, <&pll6 0>; |
b0a09c75 MR |
296 | clock-output-names = "spi1"; |
297 | }; | |
298 | ||
299 | spi2_clk: clk@01c200a8 { | |
300 | #clock-cells = <0>; | |
225b0216 | 301 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
b0a09c75 | 302 | reg = <0x01c200a8 0x4>; |
f6c3b046 | 303 | clocks = <&osc24M>, <&pll6 0>; |
b0a09c75 MR |
304 | clock-output-names = "spi2"; |
305 | }; | |
306 | ||
307 | spi3_clk: clk@01c200ac { | |
308 | #clock-cells = <0>; | |
225b0216 | 309 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
b0a09c75 | 310 | reg = <0x01c200ac 0x4>; |
f6c3b046 | 311 | clocks = <&osc24M>, <&pll6 0>; |
b0a09c75 MR |
312 | clock-output-names = "spi3"; |
313 | }; | |
94a1cd14 MR |
314 | |
315 | usb_clk: clk@01c200cc { | |
316 | #clock-cells = <1>; | |
317 | #reset-cells = <1>; | |
318 | compatible = "allwinner,sun6i-a31-usb-clk"; | |
319 | reg = <0x01c200cc 0x4>; | |
320 | clocks = <&osc24M>; | |
321 | clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2", | |
322 | "usb_ohci0", "usb_ohci1", | |
323 | "usb_ohci2"; | |
324 | }; | |
ed29861a CYT |
325 | |
326 | /* | |
327 | * The following two are dummy clocks, placeholders used in the gmac_tx | |
328 | * clock. The gmac driver will choose one parent depending on the PHY | |
329 | * interface mode, using clk_set_rate auto-reparenting. | |
330 | * The actual TX clock rate is not controlled by the gmac_tx clock. | |
331 | */ | |
332 | mii_phy_tx_clk: clk@1 { | |
333 | #clock-cells = <0>; | |
334 | compatible = "fixed-clock"; | |
335 | clock-frequency = <25000000>; | |
336 | clock-output-names = "mii_phy_tx"; | |
337 | }; | |
338 | ||
339 | gmac_int_tx_clk: clk@2 { | |
340 | #clock-cells = <0>; | |
341 | compatible = "fixed-clock"; | |
342 | clock-frequency = <125000000>; | |
343 | clock-output-names = "gmac_int_tx"; | |
344 | }; | |
345 | ||
346 | gmac_tx_clk: clk@01c200d0 { | |
347 | #clock-cells = <0>; | |
348 | compatible = "allwinner,sun7i-a20-gmac-clk"; | |
349 | reg = <0x01c200d0 0x4>; | |
350 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; | |
351 | clock-output-names = "gmac_tx"; | |
352 | }; | |
8aed3b31 MR |
353 | }; |
354 | ||
355 | soc@01c00000 { | |
356 | compatible = "simple-bus"; | |
357 | #address-cells = <1>; | |
358 | #size-cells = <1>; | |
359 | ranges; | |
360 | ||
d2d878c4 MR |
361 | dma: dma-controller@01c02000 { |
362 | compatible = "allwinner,sun6i-a31-dma"; | |
363 | reg = <0x01c02000 0x1000>; | |
364 | interrupts = <0 50 4>; | |
365 | clocks = <&ahb1_gates 6>; | |
366 | resets = <&ahb1_rst 6>; | |
367 | #dma-cells = <1>; | |
532425a7 CYT |
368 | |
369 | /* DMA controller requires AHB1 clocked from PLL6 */ | |
370 | assigned-clocks = <&ahb1_mux>; | |
f6c3b046 | 371 | assigned-clock-parents = <&pll6 0>; |
d2d878c4 MR |
372 | }; |
373 | ||
5b753f0e HG |
374 | mmc0: mmc@01c0f000 { |
375 | compatible = "allwinner,sun5i-a13-mmc"; | |
376 | reg = <0x01c0f000 0x1000>; | |
377 | clocks = <&ahb1_gates 8>, <&mmc0_clk>; | |
378 | clock-names = "ahb", "mmc"; | |
379 | resets = <&ahb1_rst 8>; | |
380 | reset-names = "ahb"; | |
381 | interrupts = <0 60 4>; | |
382 | status = "disabled"; | |
383 | }; | |
384 | ||
385 | mmc1: mmc@01c10000 { | |
386 | compatible = "allwinner,sun5i-a13-mmc"; | |
387 | reg = <0x01c10000 0x1000>; | |
388 | clocks = <&ahb1_gates 9>, <&mmc1_clk>; | |
389 | clock-names = "ahb", "mmc"; | |
390 | resets = <&ahb1_rst 9>; | |
391 | reset-names = "ahb"; | |
392 | interrupts = <0 61 4>; | |
393 | status = "disabled"; | |
394 | }; | |
395 | ||
396 | mmc2: mmc@01c11000 { | |
397 | compatible = "allwinner,sun5i-a13-mmc"; | |
398 | reg = <0x01c11000 0x1000>; | |
399 | clocks = <&ahb1_gates 10>, <&mmc2_clk>; | |
400 | clock-names = "ahb", "mmc"; | |
401 | resets = <&ahb1_rst 10>; | |
402 | reset-names = "ahb"; | |
403 | interrupts = <0 62 4>; | |
404 | status = "disabled"; | |
405 | }; | |
406 | ||
407 | mmc3: mmc@01c12000 { | |
408 | compatible = "allwinner,sun5i-a13-mmc"; | |
409 | reg = <0x01c12000 0x1000>; | |
410 | clocks = <&ahb1_gates 11>, <&mmc3_clk>; | |
411 | clock-names = "ahb", "mmc"; | |
412 | resets = <&ahb1_rst 11>; | |
413 | reset-names = "ahb"; | |
414 | interrupts = <0 63 4>; | |
415 | status = "disabled"; | |
416 | }; | |
417 | ||
ef964085 MR |
418 | usbphy: phy@01c19400 { |
419 | compatible = "allwinner,sun6i-a31-usb-phy"; | |
420 | reg = <0x01c19400 0x10>, | |
421 | <0x01c1a800 0x4>, | |
422 | <0x01c1b800 0x4>; | |
423 | reg-names = "phy_ctrl", | |
424 | "pmu1", | |
425 | "pmu2"; | |
426 | clocks = <&usb_clk 8>, | |
427 | <&usb_clk 9>, | |
428 | <&usb_clk 10>; | |
429 | clock-names = "usb0_phy", | |
430 | "usb1_phy", | |
431 | "usb2_phy"; | |
432 | resets = <&usb_clk 0>, | |
433 | <&usb_clk 1>, | |
434 | <&usb_clk 2>; | |
435 | reset-names = "usb0_reset", | |
436 | "usb1_reset", | |
437 | "usb2_reset"; | |
438 | status = "disabled"; | |
439 | #phy-cells = <1>; | |
440 | }; | |
441 | ||
442 | ehci0: usb@01c1a000 { | |
443 | compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; | |
444 | reg = <0x01c1a000 0x100>; | |
445 | interrupts = <0 72 4>; | |
446 | clocks = <&ahb1_gates 26>; | |
447 | resets = <&ahb1_rst 26>; | |
448 | phys = <&usbphy 1>; | |
449 | phy-names = "usb"; | |
450 | status = "disabled"; | |
451 | }; | |
452 | ||
453 | ohci0: usb@01c1a400 { | |
454 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; | |
455 | reg = <0x01c1a400 0x100>; | |
456 | interrupts = <0 73 4>; | |
457 | clocks = <&ahb1_gates 29>, <&usb_clk 16>; | |
458 | resets = <&ahb1_rst 29>; | |
459 | phys = <&usbphy 1>; | |
460 | phy-names = "usb"; | |
461 | status = "disabled"; | |
462 | }; | |
463 | ||
464 | ehci1: usb@01c1b000 { | |
465 | compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; | |
466 | reg = <0x01c1b000 0x100>; | |
467 | interrupts = <0 74 4>; | |
468 | clocks = <&ahb1_gates 27>; | |
469 | resets = <&ahb1_rst 27>; | |
470 | phys = <&usbphy 2>; | |
471 | phy-names = "usb"; | |
472 | status = "disabled"; | |
473 | }; | |
474 | ||
475 | ohci1: usb@01c1b400 { | |
476 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; | |
477 | reg = <0x01c1b400 0x100>; | |
478 | interrupts = <0 75 4>; | |
479 | clocks = <&ahb1_gates 30>, <&usb_clk 17>; | |
480 | resets = <&ahb1_rst 30>; | |
481 | phys = <&usbphy 2>; | |
482 | phy-names = "usb"; | |
483 | status = "disabled"; | |
484 | }; | |
485 | ||
b294ebbc | 486 | ohci2: usb@01c1c400 { |
ef964085 MR |
487 | compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; |
488 | reg = <0x01c1c400 0x100>; | |
489 | interrupts = <0 77 4>; | |
490 | clocks = <&ahb1_gates 31>, <&usb_clk 18>; | |
491 | resets = <&ahb1_rst 31>; | |
492 | status = "disabled"; | |
493 | }; | |
494 | ||
140e1721 MR |
495 | pio: pinctrl@01c20800 { |
496 | compatible = "allwinner,sun6i-a31-pinctrl"; | |
497 | reg = <0x01c20800 0x400>; | |
6f97dc8d MR |
498 | interrupts = <0 11 4>, |
499 | <0 15 4>, | |
500 | <0 16 4>, | |
501 | <0 17 4>; | |
98096560 | 502 | clocks = <&apb1_gates 5>; |
140e1721 MR |
503 | gpio-controller; |
504 | interrupt-controller; | |
7d4ff96d | 505 | #interrupt-cells = <2>; |
140e1721 MR |
506 | #size-cells = <0>; |
507 | #gpio-cells = <3>; | |
ab4238cd MR |
508 | |
509 | uart0_pins_a: uart0@0 { | |
510 | allwinner,pins = "PH20", "PH21"; | |
511 | allwinner,function = "uart0"; | |
512 | allwinner,drive = <0>; | |
513 | allwinner,pull = <0>; | |
514 | }; | |
8be188b8 MR |
515 | |
516 | i2c0_pins_a: i2c0@0 { | |
517 | allwinner,pins = "PH14", "PH15"; | |
518 | allwinner,function = "i2c0"; | |
519 | allwinner,drive = <0>; | |
520 | allwinner,pull = <0>; | |
521 | }; | |
522 | ||
523 | i2c1_pins_a: i2c1@0 { | |
524 | allwinner,pins = "PH16", "PH17"; | |
525 | allwinner,function = "i2c1"; | |
526 | allwinner,drive = <0>; | |
527 | allwinner,pull = <0>; | |
528 | }; | |
529 | ||
530 | i2c2_pins_a: i2c2@0 { | |
531 | allwinner,pins = "PH18", "PH19"; | |
532 | allwinner,function = "i2c2"; | |
533 | allwinner,drive = <0>; | |
534 | allwinner,pull = <0>; | |
535 | }; | |
9797eb83 HG |
536 | |
537 | mmc0_pins_a: mmc0@0 { | |
538 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | |
539 | allwinner,function = "mmc0"; | |
540 | allwinner,drive = <2>; | |
541 | allwinner,pull = <0>; | |
542 | }; | |
ee39a3e3 CYT |
543 | |
544 | gmac_pins_mii_a: gmac_mii@0 { | |
545 | allwinner,pins = "PA0", "PA1", "PA2", "PA3", | |
546 | "PA8", "PA9", "PA11", | |
547 | "PA12", "PA13", "PA14", "PA19", | |
548 | "PA20", "PA21", "PA22", "PA23", | |
549 | "PA24", "PA26", "PA27"; | |
550 | allwinner,function = "gmac"; | |
551 | allwinner,drive = <0>; | |
552 | allwinner,pull = <0>; | |
553 | }; | |
554 | ||
555 | gmac_pins_gmii_a: gmac_gmii@0 { | |
556 | allwinner,pins = "PA0", "PA1", "PA2", "PA3", | |
557 | "PA4", "PA5", "PA6", "PA7", | |
558 | "PA8", "PA9", "PA10", "PA11", | |
559 | "PA12", "PA13", "PA14", "PA15", | |
560 | "PA16", "PA17", "PA18", "PA19", | |
561 | "PA20", "PA21", "PA22", "PA23", | |
562 | "PA24", "PA25", "PA26", "PA27"; | |
563 | allwinner,function = "gmac"; | |
564 | /* | |
565 | * data lines in GMII mode run at 125MHz and | |
566 | * might need a higher signal drive strength | |
567 | */ | |
568 | allwinner,drive = <2>; | |
569 | allwinner,pull = <0>; | |
570 | }; | |
571 | ||
572 | gmac_pins_rgmii_a: gmac_rgmii@0 { | |
573 | allwinner,pins = "PA0", "PA1", "PA2", "PA3", | |
574 | "PA9", "PA10", "PA11", | |
575 | "PA12", "PA13", "PA14", "PA19", | |
576 | "PA20", "PA25", "PA26", "PA27"; | |
577 | allwinner,function = "gmac"; | |
578 | /* | |
579 | * data lines in RGMII mode use DDR mode | |
580 | * and need a higher signal drive strength | |
581 | */ | |
582 | allwinner,drive = <3>; | |
583 | allwinner,pull = <0>; | |
584 | }; | |
140e1721 MR |
585 | }; |
586 | ||
24a661e9 MR |
587 | ahb1_rst: reset@01c202c0 { |
588 | #reset-cells = <1>; | |
589 | compatible = "allwinner,sun6i-a31-ahb1-reset"; | |
590 | reg = <0x01c202c0 0xc>; | |
591 | }; | |
592 | ||
593 | apb1_rst: reset@01c202d0 { | |
594 | #reset-cells = <1>; | |
595 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
596 | reg = <0x01c202d0 0x4>; | |
597 | }; | |
598 | ||
599 | apb2_rst: reset@01c202d8 { | |
600 | #reset-cells = <1>; | |
601 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
602 | reg = <0x01c202d8 0x4>; | |
603 | }; | |
604 | ||
8aed3b31 | 605 | timer@01c20c00 { |
b4f26440 | 606 | compatible = "allwinner,sun4i-a10-timer"; |
8aed3b31 | 607 | reg = <0x01c20c00 0xa0>; |
6f97dc8d MR |
608 | interrupts = <0 18 4>, |
609 | <0 19 4>, | |
610 | <0 20 4>, | |
611 | <0 21 4>, | |
612 | <0 22 4>; | |
98096560 | 613 | clocks = <&osc24M>; |
8aed3b31 MR |
614 | }; |
615 | ||
616 | wdt1: watchdog@01c20ca0 { | |
ca5d04d9 | 617 | compatible = "allwinner,sun6i-a31-wdt"; |
8aed3b31 MR |
618 | reg = <0x01c20ca0 0x20>; |
619 | }; | |
620 | ||
621 | uart0: serial@01c28000 { | |
622 | compatible = "snps,dw-apb-uart"; | |
623 | reg = <0x01c28000 0x400>; | |
6f97dc8d | 624 | interrupts = <0 0 4>; |
8aed3b31 MR |
625 | reg-shift = <2>; |
626 | reg-io-width = <4>; | |
98096560 | 627 | clocks = <&apb2_gates 16>; |
24a661e9 | 628 | resets = <&apb2_rst 16>; |
d2d878c4 MR |
629 | dmas = <&dma 6>, <&dma 6>; |
630 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
631 | status = "disabled"; |
632 | }; | |
633 | ||
634 | uart1: serial@01c28400 { | |
635 | compatible = "snps,dw-apb-uart"; | |
636 | reg = <0x01c28400 0x400>; | |
6f97dc8d | 637 | interrupts = <0 1 4>; |
8aed3b31 MR |
638 | reg-shift = <2>; |
639 | reg-io-width = <4>; | |
98096560 | 640 | clocks = <&apb2_gates 17>; |
24a661e9 | 641 | resets = <&apb2_rst 17>; |
d2d878c4 MR |
642 | dmas = <&dma 7>, <&dma 7>; |
643 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
644 | status = "disabled"; |
645 | }; | |
646 | ||
647 | uart2: serial@01c28800 { | |
648 | compatible = "snps,dw-apb-uart"; | |
649 | reg = <0x01c28800 0x400>; | |
6f97dc8d | 650 | interrupts = <0 2 4>; |
8aed3b31 MR |
651 | reg-shift = <2>; |
652 | reg-io-width = <4>; | |
98096560 | 653 | clocks = <&apb2_gates 18>; |
24a661e9 | 654 | resets = <&apb2_rst 18>; |
d2d878c4 MR |
655 | dmas = <&dma 8>, <&dma 8>; |
656 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
657 | status = "disabled"; |
658 | }; | |
659 | ||
660 | uart3: serial@01c28c00 { | |
661 | compatible = "snps,dw-apb-uart"; | |
662 | reg = <0x01c28c00 0x400>; | |
6f97dc8d | 663 | interrupts = <0 3 4>; |
8aed3b31 MR |
664 | reg-shift = <2>; |
665 | reg-io-width = <4>; | |
98096560 | 666 | clocks = <&apb2_gates 19>; |
24a661e9 | 667 | resets = <&apb2_rst 19>; |
d2d878c4 MR |
668 | dmas = <&dma 9>, <&dma 9>; |
669 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
670 | status = "disabled"; |
671 | }; | |
672 | ||
673 | uart4: serial@01c29000 { | |
674 | compatible = "snps,dw-apb-uart"; | |
675 | reg = <0x01c29000 0x400>; | |
6f97dc8d | 676 | interrupts = <0 4 4>; |
8aed3b31 MR |
677 | reg-shift = <2>; |
678 | reg-io-width = <4>; | |
98096560 | 679 | clocks = <&apb2_gates 20>; |
24a661e9 | 680 | resets = <&apb2_rst 20>; |
d2d878c4 MR |
681 | dmas = <&dma 10>, <&dma 10>; |
682 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
683 | status = "disabled"; |
684 | }; | |
685 | ||
686 | uart5: serial@01c29400 { | |
687 | compatible = "snps,dw-apb-uart"; | |
688 | reg = <0x01c29400 0x400>; | |
6f97dc8d | 689 | interrupts = <0 5 4>; |
8aed3b31 MR |
690 | reg-shift = <2>; |
691 | reg-io-width = <4>; | |
98096560 | 692 | clocks = <&apb2_gates 21>; |
24a661e9 | 693 | resets = <&apb2_rst 21>; |
d2d878c4 MR |
694 | dmas = <&dma 22>, <&dma 22>; |
695 | dma-names = "rx", "tx"; | |
8aed3b31 MR |
696 | status = "disabled"; |
697 | }; | |
698 | ||
96c7cc9b MR |
699 | i2c0: i2c@01c2ac00 { |
700 | compatible = "allwinner,sun6i-a31-i2c"; | |
701 | reg = <0x01c2ac00 0x400>; | |
702 | interrupts = <0 6 4>; | |
703 | clocks = <&apb2_gates 0>; | |
96c7cc9b MR |
704 | resets = <&apb2_rst 0>; |
705 | status = "disabled"; | |
495bccf3 CYT |
706 | #address-cells = <1>; |
707 | #size-cells = <0>; | |
96c7cc9b MR |
708 | }; |
709 | ||
710 | i2c1: i2c@01c2b000 { | |
711 | compatible = "allwinner,sun6i-a31-i2c"; | |
712 | reg = <0x01c2b000 0x400>; | |
713 | interrupts = <0 7 4>; | |
714 | clocks = <&apb2_gates 1>; | |
96c7cc9b MR |
715 | resets = <&apb2_rst 1>; |
716 | status = "disabled"; | |
495bccf3 CYT |
717 | #address-cells = <1>; |
718 | #size-cells = <0>; | |
96c7cc9b MR |
719 | }; |
720 | ||
721 | i2c2: i2c@01c2b400 { | |
722 | compatible = "allwinner,sun6i-a31-i2c"; | |
723 | reg = <0x01c2b400 0x400>; | |
724 | interrupts = <0 8 4>; | |
725 | clocks = <&apb2_gates 2>; | |
96c7cc9b MR |
726 | resets = <&apb2_rst 2>; |
727 | status = "disabled"; | |
495bccf3 CYT |
728 | #address-cells = <1>; |
729 | #size-cells = <0>; | |
96c7cc9b MR |
730 | }; |
731 | ||
732 | i2c3: i2c@01c2b800 { | |
733 | compatible = "allwinner,sun6i-a31-i2c"; | |
734 | reg = <0x01c2b800 0x400>; | |
735 | interrupts = <0 9 4>; | |
736 | clocks = <&apb2_gates 3>; | |
96c7cc9b MR |
737 | resets = <&apb2_rst 3>; |
738 | status = "disabled"; | |
495bccf3 CYT |
739 | #address-cells = <1>; |
740 | #size-cells = <0>; | |
96c7cc9b MR |
741 | }; |
742 | ||
3dca65f8 CYT |
743 | gmac: ethernet@01c30000 { |
744 | compatible = "allwinner,sun7i-a20-gmac"; | |
745 | reg = <0x01c30000 0x1054>; | |
746 | interrupts = <0 82 4>; | |
747 | interrupt-names = "macirq"; | |
748 | clocks = <&ahb1_gates 17>, <&gmac_tx_clk>; | |
749 | clock-names = "stmmaceth", "allwinner_gmac_tx"; | |
750 | resets = <&ahb1_rst 17>; | |
751 | reset-names = "stmmaceth"; | |
752 | snps,pbl = <2>; | |
753 | snps,fixed-burst; | |
754 | snps,force_sf_dma_mode; | |
755 | status = "disabled"; | |
756 | #address-cells = <1>; | |
757 | #size-cells = <0>; | |
758 | }; | |
759 | ||
8cffcb0c MR |
760 | timer@01c60000 { |
761 | compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; | |
762 | reg = <0x01c60000 0x1000>; | |
763 | interrupts = <0 51 4>, | |
764 | <0 52 4>, | |
765 | <0 53 4>, | |
766 | <0 54 4>; | |
767 | clocks = <&ahb1_gates 19>; | |
768 | resets = <&ahb1_rst 19>; | |
769 | }; | |
770 | ||
0d6efe33 MR |
771 | spi0: spi@01c68000 { |
772 | compatible = "allwinner,sun6i-a31-spi"; | |
773 | reg = <0x01c68000 0x1000>; | |
774 | interrupts = <0 65 4>; | |
775 | clocks = <&ahb1_gates 20>, <&spi0_clk>; | |
776 | clock-names = "ahb", "mod"; | |
d2d878c4 MR |
777 | dmas = <&dma 23>, <&dma 23>; |
778 | dma-names = "rx", "tx"; | |
0d6efe33 MR |
779 | resets = <&ahb1_rst 20>; |
780 | status = "disabled"; | |
781 | }; | |
782 | ||
783 | spi1: spi@01c69000 { | |
784 | compatible = "allwinner,sun6i-a31-spi"; | |
785 | reg = <0x01c69000 0x1000>; | |
786 | interrupts = <0 66 4>; | |
787 | clocks = <&ahb1_gates 21>, <&spi1_clk>; | |
788 | clock-names = "ahb", "mod"; | |
d2d878c4 MR |
789 | dmas = <&dma 24>, <&dma 24>; |
790 | dma-names = "rx", "tx"; | |
0d6efe33 MR |
791 | resets = <&ahb1_rst 21>; |
792 | status = "disabled"; | |
793 | }; | |
794 | ||
795 | spi2: spi@01c6a000 { | |
796 | compatible = "allwinner,sun6i-a31-spi"; | |
797 | reg = <0x01c6a000 0x1000>; | |
798 | interrupts = <0 67 4>; | |
799 | clocks = <&ahb1_gates 22>, <&spi2_clk>; | |
800 | clock-names = "ahb", "mod"; | |
d2d878c4 MR |
801 | dmas = <&dma 25>, <&dma 25>; |
802 | dma-names = "rx", "tx"; | |
0d6efe33 MR |
803 | resets = <&ahb1_rst 22>; |
804 | status = "disabled"; | |
805 | }; | |
806 | ||
807 | spi3: spi@01c6b000 { | |
808 | compatible = "allwinner,sun6i-a31-spi"; | |
809 | reg = <0x01c6b000 0x1000>; | |
810 | interrupts = <0 68 4>; | |
811 | clocks = <&ahb1_gates 23>, <&spi3_clk>; | |
812 | clock-names = "ahb", "mod"; | |
d2d878c4 MR |
813 | dmas = <&dma 26>, <&dma 26>; |
814 | dma-names = "rx", "tx"; | |
0d6efe33 MR |
815 | resets = <&ahb1_rst 23>; |
816 | status = "disabled"; | |
817 | }; | |
818 | ||
8aed3b31 MR |
819 | gic: interrupt-controller@01c81000 { |
820 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
821 | reg = <0x01c81000 0x1000>, | |
822 | <0x01c82000 0x1000>, | |
823 | <0x01c84000 0x2000>, | |
824 | <0x01c86000 0x2000>; | |
825 | interrupt-controller; | |
826 | #interrupt-cells = <3>; | |
827 | interrupts = <1 9 0xf04>; | |
828 | }; | |
81ee429f | 829 | |
5e700435 CYT |
830 | rtc: rtc@01f00000 { |
831 | compatible = "allwinner,sun6i-a31-rtc"; | |
832 | reg = <0x01f00000 0x54>; | |
833 | interrupts = <0 40 4>, <0 41 4>; | |
834 | }; | |
835 | ||
28240d27 MR |
836 | nmi_intc: interrupt-controller@01f00c0c { |
837 | compatible = "allwinner,sun6i-a31-sc-nmi"; | |
838 | interrupt-controller; | |
839 | #interrupt-cells = <2>; | |
840 | reg = <0x01f00c0c 0x38>; | |
841 | interrupts = <0 32 4>; | |
842 | }; | |
843 | ||
a42ea603 HG |
844 | prcm@01f01400 { |
845 | compatible = "allwinner,sun6i-a31-prcm"; | |
846 | reg = <0x01f01400 0x200>; | |
cc08f5e9 BB |
847 | |
848 | ar100: ar100_clk { | |
849 | compatible = "allwinner,sun6i-a31-ar100-clk"; | |
850 | #clock-cells = <0>; | |
f6c3b046 | 851 | clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; |
cc08f5e9 BB |
852 | clock-output-names = "ar100"; |
853 | }; | |
854 | ||
855 | ahb0: ahb0_clk { | |
856 | compatible = "fixed-factor-clock"; | |
857 | #clock-cells = <0>; | |
858 | clock-div = <1>; | |
859 | clock-mult = <1>; | |
860 | clocks = <&ar100>; | |
861 | clock-output-names = "ahb0"; | |
862 | }; | |
863 | ||
864 | apb0: apb0_clk { | |
865 | compatible = "allwinner,sun6i-a31-apb0-clk"; | |
866 | #clock-cells = <0>; | |
867 | clocks = <&ahb0>; | |
868 | clock-output-names = "apb0"; | |
869 | }; | |
870 | ||
871 | apb0_gates: apb0_gates_clk { | |
872 | compatible = "allwinner,sun6i-a31-apb0-gates-clk"; | |
873 | #clock-cells = <1>; | |
874 | clocks = <&apb0>; | |
875 | clock-output-names = "apb0_pio", "apb0_ir", | |
876 | "apb0_timer", "apb0_p2wi", | |
877 | "apb0_uart", "apb0_1wire", | |
878 | "apb0_i2c"; | |
879 | }; | |
880 | ||
881 | apb0_rst: apb0_rst { | |
882 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
883 | #reset-cells = <1>; | |
884 | }; | |
a42ea603 HG |
885 | }; |
886 | ||
81ee429f MR |
887 | cpucfg@01f01c00 { |
888 | compatible = "allwinner,sun6i-a31-cpuconfig"; | |
889 | reg = <0x01f01c00 0x300>; | |
890 | }; | |
209394ae BB |
891 | |
892 | r_pio: pinctrl@01f02c00 { | |
893 | compatible = "allwinner,sun6i-a31-r-pinctrl"; | |
894 | reg = <0x01f02c00 0x400>; | |
895 | interrupts = <0 45 4>, | |
896 | <0 46 4>; | |
897 | clocks = <&apb0_gates 0>; | |
898 | resets = <&apb0_rst 0>; | |
899 | gpio-controller; | |
900 | interrupt-controller; | |
7d4ff96d | 901 | #interrupt-cells = <2>; |
209394ae BB |
902 | #size-cells = <0>; |
903 | #gpio-cells = <3>; | |
dbbcd881 HG |
904 | |
905 | ir_pins_a: ir@0 { | |
906 | allwinner,pins = "PL4"; | |
907 | allwinner,function = "s_ir"; | |
908 | allwinner,drive = <0>; | |
909 | allwinner,pull = <0>; | |
910 | }; | |
209394ae | 911 | }; |
8aed3b31 MR |
912 | }; |
913 | }; |