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4790ecfa MR |
1 | /* |
2 | * Copyright 2013 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
394c56ce MR |
6 | * This file is dual-licensed: you can use it either under the terms |
7 | * of the GPL or the X11 license, at your option. Note that this dual | |
8 | * licensing only applies to this file, and not this project as a | |
9 | * whole. | |
4790ecfa | 10 | * |
5186d83a | 11 | * a) This file is free software; you can redistribute it and/or |
394c56ce MR |
12 | * modify it under the terms of the GNU General Public License as |
13 | * published by the Free Software Foundation; either version 2 of the | |
14 | * License, or (at your option) any later version. | |
15 | * | |
5186d83a | 16 | * This file is distributed in the hope that it will be useful, |
394c56ce MR |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
394c56ce MR |
21 | * Or, alternatively, |
22 | * | |
23 | * b) Permission is hereby granted, free of charge, to any person | |
24 | * obtaining a copy of this software and associated documentation | |
25 | * files (the "Software"), to deal in the Software without | |
26 | * restriction, including without limitation the rights to use, | |
27 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
28 | * sell copies of the Software, and to permit persons to whom the | |
29 | * Software is furnished to do so, subject to the following | |
30 | * conditions: | |
31 | * | |
32 | * The above copyright notice and this permission notice shall be | |
33 | * included in all copies or substantial portions of the Software. | |
34 | * | |
35 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
36 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
37 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
38 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
39 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
40 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
41 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
42 | * OTHER DEALINGS IN THE SOFTWARE. | |
4790ecfa MR |
43 | */ |
44 | ||
71455701 | 45 | #include "skeleton.dtsi" |
4790ecfa | 46 | |
19882b84 | 47 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
b6d34248 | 48 | #include <dt-bindings/thermal/thermal.h> |
19882b84 | 49 | |
1f9f6a78 | 50 | #include <dt-bindings/dma/sun4i-a10.h> |
092a0c3b | 51 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
4790ecfa MR |
52 | |
53 | / { | |
54 | interrupt-parent = <&gic>; | |
55 | ||
e751cce9 | 56 | aliases { |
18428f77 | 57 | ethernet0 = &gmac; |
e751cce9 EL |
58 | }; |
59 | ||
8efc5c2b HG |
60 | chosen { |
61 | #address-cells = <1>; | |
62 | #size-cells = <1>; | |
63 | ranges; | |
64 | ||
a9f8cda3 | 65 | framebuffer@0 { |
d8cacaa3 MR |
66 | compatible = "allwinner,simple-framebuffer", |
67 | "simple-framebuffer"; | |
a9f8cda3 | 68 | allwinner,pipeline = "de_be0-lcd0-hdmi"; |
678e75d3 HG |
69 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, |
70 | <&ahb_gates 44>; | |
8efc5c2b HG |
71 | status = "disabled"; |
72 | }; | |
fd18c7ea HG |
73 | |
74 | framebuffer@1 { | |
75 | compatible = "allwinner,simple-framebuffer", | |
76 | "simple-framebuffer"; | |
77 | allwinner,pipeline = "de_be0-lcd0"; | |
78 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>; | |
79 | status = "disabled"; | |
80 | }; | |
81 | ||
82 | framebuffer@2 { | |
83 | compatible = "allwinner,simple-framebuffer", | |
84 | "simple-framebuffer"; | |
85 | allwinner,pipeline = "de_be0-lcd0-tve0"; | |
86 | clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, | |
87 | <&ahb_gates 44>; | |
88 | status = "disabled"; | |
89 | }; | |
8efc5c2b HG |
90 | }; |
91 | ||
4790ecfa MR |
92 | cpus { |
93 | #address-cells = <1>; | |
94 | #size-cells = <0>; | |
95 | ||
d96b7161 | 96 | cpu0: cpu@0 { |
4790ecfa MR |
97 | compatible = "arm,cortex-a7"; |
98 | device_type = "cpu"; | |
99 | reg = <0>; | |
d96b7161 CYT |
100 | clocks = <&cpu>; |
101 | clock-latency = <244144>; /* 8 32k periods */ | |
102 | operating-points = < | |
8358aada MR |
103 | /* kHz uV */ |
104 | 960000 1400000 | |
105 | 912000 1400000 | |
106 | 864000 1300000 | |
107 | 720000 1200000 | |
108 | 528000 1100000 | |
109 | 312000 1000000 | |
110 | 144000 900000 | |
d96b7161 CYT |
111 | >; |
112 | #cooling-cells = <2>; | |
113 | cooling-min-level = <0>; | |
370a9b5f | 114 | cooling-max-level = <6>; |
4790ecfa MR |
115 | }; |
116 | ||
117 | cpu@1 { | |
118 | compatible = "arm,cortex-a7"; | |
119 | device_type = "cpu"; | |
120 | reg = <1>; | |
121 | }; | |
122 | }; | |
123 | ||
b6d34248 CYT |
124 | thermal-zones { |
125 | cpu_thermal { | |
126 | /* milliseconds */ | |
127 | polling-delay-passive = <250>; | |
128 | polling-delay = <1000>; | |
129 | thermal-sensors = <&rtp>; | |
130 | ||
131 | cooling-maps { | |
132 | map0 { | |
133 | trip = <&cpu_alert0>; | |
134 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
135 | }; | |
136 | }; | |
137 | ||
138 | trips { | |
139 | cpu_alert0: cpu_alert0 { | |
140 | /* milliCelsius */ | |
141 | temperature = <75000>; | |
142 | hysteresis = <2000>; | |
143 | type = "passive"; | |
144 | }; | |
145 | ||
146 | cpu_crit: cpu_crit { | |
147 | /* milliCelsius */ | |
148 | temperature = <100000>; | |
149 | hysteresis = <2000>; | |
150 | type = "critical"; | |
151 | }; | |
152 | }; | |
153 | }; | |
154 | }; | |
155 | ||
4790ecfa MR |
156 | memory { |
157 | reg = <0x40000000 0x80000000>; | |
158 | }; | |
159 | ||
7902763e MZ |
160 | timer { |
161 | compatible = "arm,armv7-timer"; | |
19882b84 MR |
162 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
163 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
164 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
165 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
7902763e MZ |
166 | }; |
167 | ||
e29ea4d3 MR |
168 | pmu { |
169 | compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; | |
19882b84 MR |
170 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
171 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; | |
e29ea4d3 MR |
172 | }; |
173 | ||
4790ecfa MR |
174 | clocks { |
175 | #address-cells = <1>; | |
176 | #size-cells = <1>; | |
177 | ranges; | |
178 | ||
06067a2f | 179 | osc24M: clk@01c20050 { |
4790ecfa | 180 | #clock-cells = <0>; |
bf6534a1 | 181 | compatible = "allwinner,sun4i-a10-osc-clk"; |
de7dc935 | 182 | reg = <0x01c20050 0x4>; |
4790ecfa | 183 | clock-frequency = <24000000>; |
06067a2f | 184 | clock-output-names = "osc24M"; |
4790ecfa MR |
185 | }; |
186 | ||
673fac74 | 187 | osc32k: clk@0 { |
4790ecfa MR |
188 | #clock-cells = <0>; |
189 | compatible = "fixed-clock"; | |
190 | clock-frequency = <32768>; | |
673fac74 | 191 | clock-output-names = "osc32k"; |
4790ecfa | 192 | }; |
de7dc935 | 193 | |
06067a2f | 194 | pll1: clk@01c20000 { |
de7dc935 | 195 | #clock-cells = <0>; |
bf6534a1 | 196 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
de7dc935 MR |
197 | reg = <0x01c20000 0x4>; |
198 | clocks = <&osc24M>; | |
06067a2f | 199 | clock-output-names = "pll1"; |
de7dc935 MR |
200 | }; |
201 | ||
06067a2f | 202 | pll4: clk@01c20018 { |
de7dc935 | 203 | #clock-cells = <0>; |
04ebcb54 | 204 | compatible = "allwinner,sun7i-a20-pll4-clk"; |
ec5589f7 EL |
205 | reg = <0x01c20018 0x4>; |
206 | clocks = <&osc24M>; | |
06067a2f | 207 | clock-output-names = "pll4"; |
ec5589f7 EL |
208 | }; |
209 | ||
06067a2f | 210 | pll5: clk@01c20020 { |
c3e5e66b | 211 | #clock-cells = <1>; |
bf6534a1 | 212 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
c3e5e66b EL |
213 | reg = <0x01c20020 0x4>; |
214 | clocks = <&osc24M>; | |
215 | clock-output-names = "pll5_ddr", "pll5_other"; | |
216 | }; | |
217 | ||
06067a2f | 218 | pll6: clk@01c20028 { |
c3e5e66b | 219 | #clock-cells = <1>; |
bf6534a1 | 220 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
c3e5e66b EL |
221 | reg = <0x01c20028 0x4>; |
222 | clocks = <&osc24M>; | |
2186df37 CYT |
223 | clock-output-names = "pll6_sata", "pll6_other", "pll6", |
224 | "pll6_div_4"; | |
de7dc935 MR |
225 | }; |
226 | ||
04ebcb54 EL |
227 | pll8: clk@01c20040 { |
228 | #clock-cells = <0>; | |
229 | compatible = "allwinner,sun7i-a20-pll4-clk"; | |
230 | reg = <0x01c20040 0x4>; | |
231 | clocks = <&osc24M>; | |
232 | clock-output-names = "pll8"; | |
233 | }; | |
234 | ||
de7dc935 MR |
235 | cpu: cpu@01c20054 { |
236 | #clock-cells = <0>; | |
bf6534a1 | 237 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
de7dc935 | 238 | reg = <0x01c20054 0x4>; |
c3e5e66b | 239 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; |
06067a2f | 240 | clock-output-names = "cpu"; |
de7dc935 MR |
241 | }; |
242 | ||
243 | axi: axi@01c20054 { | |
244 | #clock-cells = <0>; | |
bf6534a1 | 245 | compatible = "allwinner,sun4i-a10-axi-clk"; |
de7dc935 MR |
246 | reg = <0x01c20054 0x4>; |
247 | clocks = <&cpu>; | |
06067a2f | 248 | clock-output-names = "axi"; |
de7dc935 MR |
249 | }; |
250 | ||
251 | ahb: ahb@01c20054 { | |
252 | #clock-cells = <0>; | |
2186df37 | 253 | compatible = "allwinner,sun5i-a13-ahb-clk"; |
de7dc935 | 254 | reg = <0x01c20054 0x4>; |
2186df37 | 255 | clocks = <&axi>, <&pll6 3>, <&pll6 1>; |
06067a2f | 256 | clock-output-names = "ahb"; |
2186df37 CYT |
257 | /* |
258 | * Use PLL6 as parent, instead of CPU/AXI | |
259 | * which has rate changes due to cpufreq | |
260 | */ | |
261 | assigned-clocks = <&ahb>; | |
262 | assigned-clock-parents = <&pll6 3>; | |
de7dc935 MR |
263 | }; |
264 | ||
06067a2f | 265 | ahb_gates: clk@01c20060 { |
de7dc935 MR |
266 | #clock-cells = <1>; |
267 | compatible = "allwinner,sun7i-a20-ahb-gates-clk"; | |
268 | reg = <0x01c20060 0x8>; | |
269 | clocks = <&ahb>; | |
6bfe30b2 MR |
270 | clock-indices = <0>, <1>, |
271 | <2>, <3>, <4>, | |
272 | <5>, <6>, <7>, <8>, | |
273 | <9>, <10>, <11>, <12>, | |
274 | <13>, <14>, <16>, | |
275 | <17>, <18>, <20>, <21>, | |
276 | <22>, <23>, <25>, | |
277 | <28>, <32>, <33>, <34>, | |
278 | <35>, <36>, <37>, <40>, | |
279 | <41>, <42>, <43>, | |
280 | <44>, <45>, <46>, | |
281 | <47>, <49>, <50>, | |
282 | <52>; | |
de7dc935 MR |
283 | clock-output-names = "ahb_usb0", "ahb_ehci0", |
284 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", | |
285 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", | |
286 | "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", | |
287 | "ahb_nand", "ahb_sdram", "ahb_ace", | |
288 | "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", | |
289 | "ahb_spi2", "ahb_spi3", "ahb_sata", | |
290 | "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", | |
291 | "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", | |
292 | "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", | |
293 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
294 | "ahb_de_fe1", "ahb_gmac", "ahb_mp", | |
295 | "ahb_mali"; | |
296 | }; | |
297 | ||
298 | apb0: apb0@01c20054 { | |
299 | #clock-cells = <0>; | |
bf6534a1 | 300 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
de7dc935 MR |
301 | reg = <0x01c20054 0x4>; |
302 | clocks = <&ahb>; | |
06067a2f | 303 | clock-output-names = "apb0"; |
de7dc935 MR |
304 | }; |
305 | ||
06067a2f | 306 | apb0_gates: clk@01c20068 { |
de7dc935 MR |
307 | #clock-cells = <1>; |
308 | compatible = "allwinner,sun7i-a20-apb0-gates-clk"; | |
309 | reg = <0x01c20068 0x4>; | |
310 | clocks = <&apb0>; | |
6bfe30b2 MR |
311 | clock-indices = <0>, <1>, |
312 | <2>, <3>, <4>, | |
313 | <5>, <6>, <7>, | |
314 | <8>, <10>; | |
de7dc935 MR |
315 | clock-output-names = "apb0_codec", "apb0_spdif", |
316 | "apb0_ac97", "apb0_iis0", "apb0_iis1", | |
317 | "apb0_pio", "apb0_ir0", "apb0_ir1", | |
318 | "apb0_iis2", "apb0_keypad"; | |
319 | }; | |
320 | ||
acbcc0f0 | 321 | apb1: clk@01c20058 { |
de7dc935 | 322 | #clock-cells = <0>; |
bf6534a1 | 323 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
de7dc935 | 324 | reg = <0x01c20058 0x4>; |
acbcc0f0 | 325 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
06067a2f | 326 | clock-output-names = "apb1"; |
de7dc935 MR |
327 | }; |
328 | ||
06067a2f | 329 | apb1_gates: clk@01c2006c { |
de7dc935 MR |
330 | #clock-cells = <1>; |
331 | compatible = "allwinner,sun7i-a20-apb1-gates-clk"; | |
332 | reg = <0x01c2006c 0x4>; | |
333 | clocks = <&apb1>; | |
6bfe30b2 MR |
334 | clock-indices = <0>, <1>, |
335 | <2>, <3>, <4>, | |
336 | <5>, <6>, <7>, | |
337 | <15>, <16>, <17>, | |
338 | <18>, <19>, <20>, | |
339 | <21>, <22>, <23>; | |
de7dc935 MR |
340 | clock-output-names = "apb1_i2c0", "apb1_i2c1", |
341 | "apb1_i2c2", "apb1_i2c3", "apb1_can", | |
342 | "apb1_scr", "apb1_ps20", "apb1_ps21", | |
343 | "apb1_i2c4", "apb1_uart0", "apb1_uart1", | |
344 | "apb1_uart2", "apb1_uart3", "apb1_uart4", | |
345 | "apb1_uart5", "apb1_uart6", "apb1_uart7"; | |
346 | }; | |
1c92b95b EL |
347 | |
348 | nand_clk: clk@01c20080 { | |
349 | #clock-cells = <0>; | |
bf6534a1 | 350 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
351 | reg = <0x01c20080 0x4>; |
352 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
353 | clock-output-names = "nand"; | |
354 | }; | |
355 | ||
356 | ms_clk: clk@01c20084 { | |
357 | #clock-cells = <0>; | |
bf6534a1 | 358 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
359 | reg = <0x01c20084 0x4>; |
360 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
361 | clock-output-names = "ms"; | |
362 | }; | |
363 | ||
364 | mmc0_clk: clk@01c20088 { | |
d8c3a392 MR |
365 | #clock-cells = <1>; |
366 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
1c92b95b EL |
367 | reg = <0x01c20088 0x4>; |
368 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
369 | clock-output-names = "mmc0", |
370 | "mmc0_output", | |
371 | "mmc0_sample"; | |
1c92b95b EL |
372 | }; |
373 | ||
374 | mmc1_clk: clk@01c2008c { | |
d8c3a392 MR |
375 | #clock-cells = <1>; |
376 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
1c92b95b EL |
377 | reg = <0x01c2008c 0x4>; |
378 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
379 | clock-output-names = "mmc1", |
380 | "mmc1_output", | |
381 | "mmc1_sample"; | |
1c92b95b EL |
382 | }; |
383 | ||
384 | mmc2_clk: clk@01c20090 { | |
d8c3a392 MR |
385 | #clock-cells = <1>; |
386 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
1c92b95b EL |
387 | reg = <0x01c20090 0x4>; |
388 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
389 | clock-output-names = "mmc2", |
390 | "mmc2_output", | |
391 | "mmc2_sample"; | |
1c92b95b EL |
392 | }; |
393 | ||
394 | mmc3_clk: clk@01c20094 { | |
d8c3a392 MR |
395 | #clock-cells = <1>; |
396 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
1c92b95b EL |
397 | reg = <0x01c20094 0x4>; |
398 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
399 | clock-output-names = "mmc3", |
400 | "mmc3_output", | |
401 | "mmc3_sample"; | |
1c92b95b EL |
402 | }; |
403 | ||
404 | ts_clk: clk@01c20098 { | |
405 | #clock-cells = <0>; | |
bf6534a1 | 406 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
407 | reg = <0x01c20098 0x4>; |
408 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
409 | clock-output-names = "ts"; | |
410 | }; | |
411 | ||
412 | ss_clk: clk@01c2009c { | |
413 | #clock-cells = <0>; | |
bf6534a1 | 414 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
415 | reg = <0x01c2009c 0x4>; |
416 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
417 | clock-output-names = "ss"; | |
418 | }; | |
419 | ||
420 | spi0_clk: clk@01c200a0 { | |
421 | #clock-cells = <0>; | |
bf6534a1 | 422 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
423 | reg = <0x01c200a0 0x4>; |
424 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
425 | clock-output-names = "spi0"; | |
426 | }; | |
427 | ||
428 | spi1_clk: clk@01c200a4 { | |
429 | #clock-cells = <0>; | |
bf6534a1 | 430 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
431 | reg = <0x01c200a4 0x4>; |
432 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
433 | clock-output-names = "spi1"; | |
434 | }; | |
435 | ||
436 | spi2_clk: clk@01c200a8 { | |
437 | #clock-cells = <0>; | |
bf6534a1 | 438 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
439 | reg = <0x01c200a8 0x4>; |
440 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
441 | clock-output-names = "spi2"; | |
442 | }; | |
443 | ||
444 | pata_clk: clk@01c200ac { | |
445 | #clock-cells = <0>; | |
bf6534a1 | 446 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
447 | reg = <0x01c200ac 0x4>; |
448 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
449 | clock-output-names = "pata"; | |
450 | }; | |
451 | ||
452 | ir0_clk: clk@01c200b0 { | |
453 | #clock-cells = <0>; | |
bf6534a1 | 454 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
455 | reg = <0x01c200b0 0x4>; |
456 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
457 | clock-output-names = "ir0"; | |
458 | }; | |
459 | ||
460 | ir1_clk: clk@01c200b4 { | |
461 | #clock-cells = <0>; | |
bf6534a1 | 462 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
463 | reg = <0x01c200b4 0x4>; |
464 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
465 | clock-output-names = "ir1"; | |
466 | }; | |
467 | ||
434e41b3 RB |
468 | usb_clk: clk@01c200cc { |
469 | #clock-cells = <1>; | |
8358aada | 470 | #reset-cells = <1>; |
434e41b3 RB |
471 | compatible = "allwinner,sun4i-a10-usb-clk"; |
472 | reg = <0x01c200cc 0x4>; | |
473 | clocks = <&pll6 1>; | |
d8cacaa3 MR |
474 | clock-output-names = "usb_ohci0", "usb_ohci1", |
475 | "usb_phy"; | |
434e41b3 RB |
476 | }; |
477 | ||
1c92b95b EL |
478 | spi3_clk: clk@01c200d4 { |
479 | #clock-cells = <0>; | |
bf6534a1 | 480 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
481 | reg = <0x01c200d4 0x4>; |
482 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
483 | clock-output-names = "spi3"; | |
484 | }; | |
118c07ae EL |
485 | |
486 | mbus_clk: clk@01c2015c { | |
487 | #clock-cells = <0>; | |
7868c5eb | 488 | compatible = "allwinner,sun5i-a13-mbus-clk"; |
118c07ae EL |
489 | reg = <0x01c2015c 0x4>; |
490 | clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; | |
491 | clock-output-names = "mbus"; | |
492 | }; | |
0aff0370 | 493 | |
daed5a81 | 494 | /* |
d8cacaa3 MR |
495 | * The following two are dummy clocks, placeholders |
496 | * used in the gmac_tx clock. The gmac driver will | |
497 | * choose one parent depending on the PHY interface | |
498 | * mode, using clk_set_rate auto-reparenting. | |
499 | * | |
500 | * The actual TX clock rate is not controlled by the | |
501 | * gmac_tx clock. | |
daed5a81 CYT |
502 | */ |
503 | mii_phy_tx_clk: clk@2 { | |
504 | #clock-cells = <0>; | |
505 | compatible = "fixed-clock"; | |
506 | clock-frequency = <25000000>; | |
507 | clock-output-names = "mii_phy_tx"; | |
508 | }; | |
509 | ||
510 | gmac_int_tx_clk: clk@3 { | |
511 | #clock-cells = <0>; | |
512 | compatible = "fixed-clock"; | |
513 | clock-frequency = <125000000>; | |
514 | clock-output-names = "gmac_int_tx"; | |
515 | }; | |
516 | ||
517 | gmac_tx_clk: clk@01c20164 { | |
518 | #clock-cells = <0>; | |
519 | compatible = "allwinner,sun7i-a20-gmac-clk"; | |
520 | reg = <0x01c20164 0x4>; | |
521 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; | |
522 | clock-output-names = "gmac_tx"; | |
523 | }; | |
524 | ||
0aff0370 CYT |
525 | /* |
526 | * Dummy clock used by output clocks | |
527 | */ | |
528 | osc24M_32k: clk@1 { | |
529 | #clock-cells = <0>; | |
530 | compatible = "fixed-factor-clock"; | |
531 | clock-div = <750>; | |
532 | clock-mult = <1>; | |
533 | clocks = <&osc24M>; | |
534 | clock-output-names = "osc24M_32k"; | |
535 | }; | |
536 | ||
537 | clk_out_a: clk@01c201f0 { | |
538 | #clock-cells = <0>; | |
539 | compatible = "allwinner,sun7i-a20-out-clk"; | |
540 | reg = <0x01c201f0 0x4>; | |
541 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; | |
542 | clock-output-names = "clk_out_a"; | |
543 | }; | |
544 | ||
545 | clk_out_b: clk@01c201f4 { | |
546 | #clock-cells = <0>; | |
547 | compatible = "allwinner,sun7i-a20-out-clk"; | |
548 | reg = <0x01c201f4 0x4>; | |
549 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; | |
550 | clock-output-names = "clk_out_b"; | |
551 | }; | |
4790ecfa MR |
552 | }; |
553 | ||
554 | soc@01c00000 { | |
555 | compatible = "simple-bus"; | |
556 | #address-cells = <1>; | |
557 | #size-cells = <1>; | |
558 | ranges; | |
559 | ||
0eb14a8d MR |
560 | sram-controller@01c00000 { |
561 | compatible = "allwinner,sun4i-a10-sram-controller"; | |
562 | reg = <0x01c00000 0x30>; | |
563 | #address-cells = <1>; | |
564 | #size-cells = <1>; | |
565 | ranges; | |
566 | ||
567 | sram_a: sram@00000000 { | |
568 | compatible = "mmio-sram"; | |
569 | reg = <0x00000000 0xc000>; | |
570 | #address-cells = <1>; | |
571 | #size-cells = <1>; | |
572 | ranges = <0 0x00000000 0xc000>; | |
573 | ||
574 | emac_sram: sram-section@8000 { | |
575 | compatible = "allwinner,sun4i-a10-sram-a3-a4"; | |
576 | reg = <0x8000 0x4000>; | |
577 | status = "disabled"; | |
578 | }; | |
579 | }; | |
580 | ||
581 | sram_d: sram@00010000 { | |
582 | compatible = "mmio-sram"; | |
583 | reg = <0x00010000 0x1000>; | |
584 | #address-cells = <1>; | |
585 | #size-cells = <1>; | |
586 | ranges = <0 0x00010000 0x1000>; | |
587 | ||
588 | otg_sram: sram-section@0000 { | |
589 | compatible = "allwinner,sun4i-a10-sram-d"; | |
590 | reg = <0x0000 0x1000>; | |
591 | status = "disabled"; | |
592 | }; | |
593 | }; | |
594 | }; | |
595 | ||
8ff973a2 CC |
596 | nmi_intc: interrupt-controller@01c00030 { |
597 | compatible = "allwinner,sun7i-a20-sc-nmi"; | |
598 | interrupt-controller; | |
599 | #interrupt-cells = <2>; | |
600 | reg = <0x01c00030 0x0c>; | |
19882b84 | 601 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
8ff973a2 CC |
602 | }; |
603 | ||
316e0b0e EL |
604 | dma: dma-controller@01c02000 { |
605 | compatible = "allwinner,sun4i-a10-dma"; | |
606 | reg = <0x01c02000 0x1000>; | |
19882b84 | 607 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
316e0b0e EL |
608 | clocks = <&ahb_gates 6>; |
609 | #dma-cells = <2>; | |
610 | }; | |
611 | ||
36ab3e73 MR |
612 | spi0: spi@01c05000 { |
613 | compatible = "allwinner,sun4i-a10-spi"; | |
614 | reg = <0x01c05000 0x1000>; | |
19882b84 | 615 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
36ab3e73 MR |
616 | clocks = <&ahb_gates 20>, <&spi0_clk>; |
617 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
618 | dmas = <&dma SUN4I_DMA_DEDICATED 27>, |
619 | <&dma SUN4I_DMA_DEDICATED 26>; | |
ffec7210 | 620 | dma-names = "rx", "tx"; |
36ab3e73 MR |
621 | status = "disabled"; |
622 | #address-cells = <1>; | |
623 | #size-cells = <0>; | |
624 | }; | |
625 | ||
626 | spi1: spi@01c06000 { | |
627 | compatible = "allwinner,sun4i-a10-spi"; | |
628 | reg = <0x01c06000 0x1000>; | |
19882b84 | 629 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
36ab3e73 MR |
630 | clocks = <&ahb_gates 21>, <&spi1_clk>; |
631 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
632 | dmas = <&dma SUN4I_DMA_DEDICATED 9>, |
633 | <&dma SUN4I_DMA_DEDICATED 8>; | |
ffec7210 | 634 | dma-names = "rx", "tx"; |
36ab3e73 MR |
635 | status = "disabled"; |
636 | #address-cells = <1>; | |
637 | #size-cells = <0>; | |
638 | }; | |
639 | ||
2e804d03 | 640 | emac: ethernet@01c0b000 { |
1c70e099 | 641 | compatible = "allwinner,sun4i-a10-emac"; |
2e804d03 | 642 | reg = <0x01c0b000 0x1000>; |
19882b84 | 643 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
2e804d03 | 644 | clocks = <&ahb_gates 17>; |
0eb14a8d | 645 | allwinner,sram = <&emac_sram 1>; |
2e804d03 MR |
646 | status = "disabled"; |
647 | }; | |
648 | ||
92395f56 | 649 | mdio: mdio@01c0b080 { |
1c70e099 | 650 | compatible = "allwinner,sun4i-a10-mdio"; |
2e804d03 MR |
651 | reg = <0x01c0b080 0x14>; |
652 | status = "disabled"; | |
653 | #address-cells = <1>; | |
654 | #size-cells = <0>; | |
655 | }; | |
656 | ||
dd29ce53 HG |
657 | mmc0: mmc@01c0f000 { |
658 | compatible = "allwinner,sun5i-a13-mmc"; | |
659 | reg = <0x01c0f000 0x1000>; | |
d8c3a392 MR |
660 | clocks = <&ahb_gates 8>, |
661 | <&mmc0_clk 0>, | |
662 | <&mmc0_clk 1>, | |
663 | <&mmc0_clk 2>; | |
664 | clock-names = "ahb", | |
665 | "mmc", | |
666 | "output", | |
667 | "sample"; | |
19882b84 | 668 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
dd29ce53 | 669 | status = "disabled"; |
4c1bb9c3 HG |
670 | #address-cells = <1>; |
671 | #size-cells = <0>; | |
dd29ce53 HG |
672 | }; |
673 | ||
674 | mmc1: mmc@01c10000 { | |
675 | compatible = "allwinner,sun5i-a13-mmc"; | |
676 | reg = <0x01c10000 0x1000>; | |
d8c3a392 MR |
677 | clocks = <&ahb_gates 9>, |
678 | <&mmc1_clk 0>, | |
679 | <&mmc1_clk 1>, | |
680 | <&mmc1_clk 2>; | |
681 | clock-names = "ahb", | |
682 | "mmc", | |
683 | "output", | |
684 | "sample"; | |
19882b84 | 685 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
dd29ce53 | 686 | status = "disabled"; |
4c1bb9c3 HG |
687 | #address-cells = <1>; |
688 | #size-cells = <0>; | |
dd29ce53 HG |
689 | }; |
690 | ||
691 | mmc2: mmc@01c11000 { | |
692 | compatible = "allwinner,sun5i-a13-mmc"; | |
693 | reg = <0x01c11000 0x1000>; | |
d8c3a392 MR |
694 | clocks = <&ahb_gates 10>, |
695 | <&mmc2_clk 0>, | |
696 | <&mmc2_clk 1>, | |
697 | <&mmc2_clk 2>; | |
698 | clock-names = "ahb", | |
699 | "mmc", | |
700 | "output", | |
701 | "sample"; | |
19882b84 | 702 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
dd29ce53 | 703 | status = "disabled"; |
4c1bb9c3 HG |
704 | #address-cells = <1>; |
705 | #size-cells = <0>; | |
dd29ce53 HG |
706 | }; |
707 | ||
708 | mmc3: mmc@01c12000 { | |
709 | compatible = "allwinner,sun5i-a13-mmc"; | |
710 | reg = <0x01c12000 0x1000>; | |
d8c3a392 MR |
711 | clocks = <&ahb_gates 11>, |
712 | <&mmc3_clk 0>, | |
713 | <&mmc3_clk 1>, | |
714 | <&mmc3_clk 2>; | |
715 | clock-names = "ahb", | |
716 | "mmc", | |
717 | "output", | |
718 | "sample"; | |
19882b84 | 719 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
dd29ce53 | 720 | status = "disabled"; |
4c1bb9c3 HG |
721 | #address-cells = <1>; |
722 | #size-cells = <0>; | |
dd29ce53 HG |
723 | }; |
724 | ||
9debd0a2 RB |
725 | usbphy: phy@01c13400 { |
726 | #phy-cells = <1>; | |
727 | compatible = "allwinner,sun7i-a20-usb-phy"; | |
728 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
729 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
730 | clocks = <&usb_clk 8>; | |
731 | clock-names = "usb_phy"; | |
134c60ad RB |
732 | resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; |
733 | reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; | |
9debd0a2 RB |
734 | status = "disabled"; |
735 | }; | |
736 | ||
737 | ehci0: usb@01c14000 { | |
738 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; | |
739 | reg = <0x01c14000 0x100>; | |
19882b84 | 740 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
9debd0a2 RB |
741 | clocks = <&ahb_gates 1>; |
742 | phys = <&usbphy 1>; | |
743 | phy-names = "usb"; | |
744 | status = "disabled"; | |
745 | }; | |
746 | ||
747 | ohci0: usb@01c14400 { | |
748 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; | |
749 | reg = <0x01c14400 0x100>; | |
19882b84 | 750 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
9debd0a2 RB |
751 | clocks = <&usb_clk 6>, <&ahb_gates 2>; |
752 | phys = <&usbphy 1>; | |
753 | phy-names = "usb"; | |
754 | status = "disabled"; | |
755 | }; | |
756 | ||
110d4e25 LC |
757 | crypto: crypto-engine@01c15000 { |
758 | compatible = "allwinner,sun4i-a10-crypto"; | |
759 | reg = <0x01c15000 0x1000>; | |
760 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
761 | clocks = <&ahb_gates 5>, <&ss_clk>; | |
762 | clock-names = "ahb", "mod"; | |
763 | }; | |
764 | ||
36ab3e73 MR |
765 | spi2: spi@01c17000 { |
766 | compatible = "allwinner,sun4i-a10-spi"; | |
767 | reg = <0x01c17000 0x1000>; | |
19882b84 | 768 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
36ab3e73 MR |
769 | clocks = <&ahb_gates 22>, <&spi2_clk>; |
770 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
771 | dmas = <&dma SUN4I_DMA_DEDICATED 29>, |
772 | <&dma SUN4I_DMA_DEDICATED 28>; | |
ffec7210 | 773 | dma-names = "rx", "tx"; |
36ab3e73 MR |
774 | status = "disabled"; |
775 | #address-cells = <1>; | |
776 | #size-cells = <0>; | |
777 | }; | |
778 | ||
902febf9 HG |
779 | ahci: sata@01c18000 { |
780 | compatible = "allwinner,sun4i-a10-ahci"; | |
781 | reg = <0x01c18000 0x1000>; | |
19882b84 | 782 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
902febf9 HG |
783 | clocks = <&pll6 0>, <&ahb_gates 25>; |
784 | status = "disabled"; | |
785 | }; | |
786 | ||
9debd0a2 RB |
787 | ehci1: usb@01c1c000 { |
788 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; | |
789 | reg = <0x01c1c000 0x100>; | |
19882b84 | 790 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
9debd0a2 RB |
791 | clocks = <&ahb_gates 3>; |
792 | phys = <&usbphy 2>; | |
793 | phy-names = "usb"; | |
794 | status = "disabled"; | |
795 | }; | |
796 | ||
797 | ohci1: usb@01c1c400 { | |
798 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; | |
799 | reg = <0x01c1c400 0x100>; | |
19882b84 | 800 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
9debd0a2 RB |
801 | clocks = <&usb_clk 7>, <&ahb_gates 4>; |
802 | phys = <&usbphy 2>; | |
803 | phy-names = "usb"; | |
804 | status = "disabled"; | |
805 | }; | |
806 | ||
36ab3e73 MR |
807 | spi3: spi@01c1f000 { |
808 | compatible = "allwinner,sun4i-a10-spi"; | |
809 | reg = <0x01c1f000 0x1000>; | |
19882b84 | 810 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
36ab3e73 MR |
811 | clocks = <&ahb_gates 23>, <&spi3_clk>; |
812 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
813 | dmas = <&dma SUN4I_DMA_DEDICATED 31>, |
814 | <&dma SUN4I_DMA_DEDICATED 30>; | |
ffec7210 | 815 | dma-names = "rx", "tx"; |
36ab3e73 | 816 | status = "disabled"; |
2e804d03 MR |
817 | #address-cells = <1>; |
818 | #size-cells = <0>; | |
819 | }; | |
820 | ||
17eac031 MR |
821 | pio: pinctrl@01c20800 { |
822 | compatible = "allwinner,sun7i-a20-pinctrl"; | |
823 | reg = <0x01c20800 0x400>; | |
19882b84 | 824 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
de7dc935 | 825 | clocks = <&apb0_gates 5>; |
17eac031 MR |
826 | gpio-controller; |
827 | interrupt-controller; | |
7d4ff96d | 828 | #interrupt-cells = <2>; |
17eac031 MR |
829 | #size-cells = <0>; |
830 | #gpio-cells = <3>; | |
9f229ba9 | 831 | |
fd7898a2 AB |
832 | pwm0_pins_a: pwm0@0 { |
833 | allwinner,pins = "PB2"; | |
834 | allwinner,function = "pwm"; | |
092a0c3b MR |
835 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
836 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
fd7898a2 AB |
837 | }; |
838 | ||
839 | pwm1_pins_a: pwm1@0 { | |
840 | allwinner,pins = "PI3"; | |
841 | allwinner,function = "pwm"; | |
092a0c3b MR |
842 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
843 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
fd7898a2 AB |
844 | }; |
845 | ||
9f229ba9 MR |
846 | uart0_pins_a: uart0@0 { |
847 | allwinner,pins = "PB22", "PB23"; | |
848 | allwinner,function = "uart0"; | |
092a0c3b MR |
849 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
850 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
9f229ba9 MR |
851 | }; |
852 | ||
4261ec43 CYT |
853 | uart2_pins_a: uart2@0 { |
854 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; | |
855 | allwinner,function = "uart2"; | |
092a0c3b MR |
856 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
857 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
4261ec43 CYT |
858 | }; |
859 | ||
7b5bace3 WW |
860 | uart3_pins_a: uart3@0 { |
861 | allwinner,pins = "PG6", "PG7", "PG8", "PG9"; | |
862 | allwinner,function = "uart3"; | |
092a0c3b MR |
863 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
864 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
7b5bace3 WW |
865 | }; |
866 | ||
0510e4b5 HG |
867 | uart3_pins_b: uart3@1 { |
868 | allwinner,pins = "PH0", "PH1"; | |
869 | allwinner,function = "uart3"; | |
092a0c3b MR |
870 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
871 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
0510e4b5 HG |
872 | }; |
873 | ||
7b5bace3 WW |
874 | uart4_pins_a: uart4@0 { |
875 | allwinner,pins = "PG10", "PG11"; | |
876 | allwinner,function = "uart4"; | |
092a0c3b MR |
877 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
878 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
7b5bace3 WW |
879 | }; |
880 | ||
869afa7f MR |
881 | uart4_pins_b: uart4@1 { |
882 | allwinner,pins = "PH4", "PH5"; | |
883 | allwinner,function = "uart4"; | |
884 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
885 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
886 | }; | |
887 | ||
7b5bace3 WW |
888 | uart5_pins_a: uart5@0 { |
889 | allwinner,pins = "PI10", "PI11"; | |
890 | allwinner,function = "uart5"; | |
092a0c3b MR |
891 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
892 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
7b5bace3 WW |
893 | }; |
894 | ||
9f229ba9 MR |
895 | uart6_pins_a: uart6@0 { |
896 | allwinner,pins = "PI12", "PI13"; | |
897 | allwinner,function = "uart6"; | |
092a0c3b MR |
898 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
899 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
9f229ba9 MR |
900 | }; |
901 | ||
902 | uart7_pins_a: uart7@0 { | |
903 | allwinner,pins = "PI20", "PI21"; | |
904 | allwinner,function = "uart7"; | |
092a0c3b MR |
905 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
906 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
9f229ba9 | 907 | }; |
756084c5 | 908 | |
e5496a31 MR |
909 | i2c0_pins_a: i2c0@0 { |
910 | allwinner,pins = "PB0", "PB1"; | |
911 | allwinner,function = "i2c0"; | |
092a0c3b MR |
912 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
913 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
e5496a31 MR |
914 | }; |
915 | ||
916 | i2c1_pins_a: i2c1@0 { | |
917 | allwinner,pins = "PB18", "PB19"; | |
918 | allwinner,function = "i2c1"; | |
092a0c3b MR |
919 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
920 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
e5496a31 MR |
921 | }; |
922 | ||
923 | i2c2_pins_a: i2c2@0 { | |
924 | allwinner,pins = "PB20", "PB21"; | |
925 | allwinner,function = "i2c2"; | |
092a0c3b MR |
926 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
927 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
e5496a31 MR |
928 | }; |
929 | ||
7b5bace3 WW |
930 | i2c3_pins_a: i2c3@0 { |
931 | allwinner,pins = "PI0", "PI1"; | |
932 | allwinner,function = "i2c3"; | |
092a0c3b MR |
933 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
934 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
7b5bace3 WW |
935 | }; |
936 | ||
756084c5 MR |
937 | emac_pins_a: emac0@0 { |
938 | allwinner,pins = "PA0", "PA1", "PA2", | |
939 | "PA3", "PA4", "PA5", "PA6", | |
940 | "PA7", "PA8", "PA9", "PA10", | |
941 | "PA11", "PA12", "PA13", "PA14", | |
942 | "PA15", "PA16"; | |
943 | allwinner,function = "emac"; | |
092a0c3b MR |
944 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
945 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
756084c5 | 946 | }; |
f2e0759e CYT |
947 | |
948 | clk_out_a_pins_a: clk_out_a@0 { | |
949 | allwinner,pins = "PI12"; | |
950 | allwinner,function = "clk_out_a"; | |
092a0c3b MR |
951 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
952 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
f2e0759e CYT |
953 | }; |
954 | ||
955 | clk_out_b_pins_a: clk_out_b@0 { | |
956 | allwinner,pins = "PI13"; | |
957 | allwinner,function = "clk_out_b"; | |
092a0c3b MR |
958 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
959 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
f2e0759e | 960 | }; |
129ccbcd CYT |
961 | |
962 | gmac_pins_mii_a: gmac_mii@0 { | |
963 | allwinner,pins = "PA0", "PA1", "PA2", | |
964 | "PA3", "PA4", "PA5", "PA6", | |
965 | "PA7", "PA8", "PA9", "PA10", | |
966 | "PA11", "PA12", "PA13", "PA14", | |
967 | "PA15", "PA16"; | |
968 | allwinner,function = "gmac"; | |
092a0c3b MR |
969 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
970 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
129ccbcd CYT |
971 | }; |
972 | ||
973 | gmac_pins_rgmii_a: gmac_rgmii@0 { | |
974 | allwinner,pins = "PA0", "PA1", "PA2", | |
975 | "PA3", "PA4", "PA5", "PA6", | |
976 | "PA7", "PA8", "PA10", | |
977 | "PA11", "PA12", "PA13", | |
978 | "PA15", "PA16"; | |
979 | allwinner,function = "gmac"; | |
980 | /* | |
981 | * data lines in RGMII mode use DDR mode | |
982 | * and need a higher signal drive strength | |
983 | */ | |
092a0c3b MR |
984 | allwinner,drive = <SUN4I_PINCTRL_40_MA>; |
985 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
129ccbcd | 986 | }; |
412f2c6f | 987 | |
2dad53b5 | 988 | spi0_pins_a: spi0@0 { |
f3022c6c MR |
989 | allwinner,pins = "PI11", "PI12", "PI13"; |
990 | allwinner,function = "spi0"; | |
991 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
992 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
993 | }; | |
994 | ||
995 | spi0_cs0_pins_a: spi0_cs0@0 { | |
996 | allwinner,pins = "PI10"; | |
997 | allwinner,function = "spi0"; | |
998 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
999 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1000 | }; | |
1001 | ||
1002 | spi0_cs1_pins_a: spi0_cs1@0 { | |
1003 | allwinner,pins = "PI14"; | |
2dad53b5 | 1004 | allwinner,function = "spi0"; |
092a0c3b MR |
1005 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1006 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
2dad53b5 HG |
1007 | }; |
1008 | ||
412f2c6f | 1009 | spi1_pins_a: spi1@0 { |
f3022c6c MR |
1010 | allwinner,pins = "PI17", "PI18", "PI19"; |
1011 | allwinner,function = "spi1"; | |
1012 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1013 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1014 | }; | |
1015 | ||
1016 | spi1_cs0_pins_a: spi1_cs0@0 { | |
1017 | allwinner,pins = "PI16"; | |
412f2c6f | 1018 | allwinner,function = "spi1"; |
092a0c3b MR |
1019 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1020 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
412f2c6f MR |
1021 | }; |
1022 | ||
1023 | spi2_pins_a: spi2@0 { | |
f3022c6c | 1024 | allwinner,pins = "PC20", "PC21", "PC22"; |
412f2c6f | 1025 | allwinner,function = "spi2"; |
092a0c3b MR |
1026 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1027 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
7b5bace3 WW |
1028 | }; |
1029 | ||
1030 | spi2_pins_b: spi2@1 { | |
f3022c6c MR |
1031 | allwinner,pins = "PB15", "PB16", "PB17"; |
1032 | allwinner,function = "spi2"; | |
1033 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1034 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1035 | }; | |
1036 | ||
1037 | spi2_cs0_pins_a: spi2_cs0@0 { | |
1038 | allwinner,pins = "PC19"; | |
1039 | allwinner,function = "spi2"; | |
1040 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1041 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1042 | }; | |
1043 | ||
1044 | spi2_cs0_pins_b: spi2_cs0@1 { | |
1045 | allwinner,pins = "PB14"; | |
7b5bace3 | 1046 | allwinner,function = "spi2"; |
092a0c3b MR |
1047 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1048 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
412f2c6f | 1049 | }; |
11fbedf4 HG |
1050 | |
1051 | mmc0_pins_a: mmc0@0 { | |
d8cacaa3 MR |
1052 | allwinner,pins = "PF0", "PF1", "PF2", |
1053 | "PF3", "PF4", "PF5"; | |
11fbedf4 | 1054 | allwinner,function = "mmc0"; |
092a0c3b MR |
1055 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
1056 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
11fbedf4 HG |
1057 | }; |
1058 | ||
1059 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { | |
1060 | allwinner,pins = "PH1"; | |
1061 | allwinner,function = "gpio_in"; | |
092a0c3b MR |
1062 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1063 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
11fbedf4 HG |
1064 | }; |
1065 | ||
8fa82326 | 1066 | mmc2_pins_a: mmc2@0 { |
d8cacaa3 MR |
1067 | allwinner,pins = "PC6", "PC7", "PC8", |
1068 | "PC9", "PC10", "PC11"; | |
8fa82326 | 1069 | allwinner,function = "mmc2"; |
092a0c3b MR |
1070 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
1071 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
8fa82326 HG |
1072 | }; |
1073 | ||
11fbedf4 | 1074 | mmc3_pins_a: mmc3@0 { |
d8cacaa3 MR |
1075 | allwinner,pins = "PI4", "PI5", "PI6", |
1076 | "PI7", "PI8", "PI9"; | |
11fbedf4 | 1077 | allwinner,function = "mmc3"; |
092a0c3b MR |
1078 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
1079 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
11fbedf4 | 1080 | }; |
0fc2b7af | 1081 | |
469a22e6 MC |
1082 | ir0_rx_pins_a: ir0@0 { |
1083 | allwinner,pins = "PB4"; | |
0fc2b7af | 1084 | allwinner,function = "ir0"; |
092a0c3b MR |
1085 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1086 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
0fc2b7af AB |
1087 | }; |
1088 | ||
469a22e6 MC |
1089 | ir0_tx_pins_a: ir0@1 { |
1090 | allwinner,pins = "PB3"; | |
1091 | allwinner,function = "ir0"; | |
1092 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1093 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1094 | }; | |
1095 | ||
1096 | ir1_rx_pins_a: ir1@0 { | |
1097 | allwinner,pins = "PB23"; | |
1098 | allwinner,function = "ir1"; | |
1099 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1100 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1101 | }; | |
1102 | ||
1103 | ir1_tx_pins_a: ir1@1 { | |
1104 | allwinner,pins = "PB22"; | |
0fc2b7af | 1105 | allwinner,function = "ir1"; |
092a0c3b MR |
1106 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1107 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
0fc2b7af | 1108 | }; |
1e8d1567 VP |
1109 | |
1110 | ps20_pins_a: ps20@0 { | |
1111 | allwinner,pins = "PI20", "PI21"; | |
1112 | allwinner,function = "ps2"; | |
1113 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1114 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1115 | }; | |
1116 | ||
1117 | ps21_pins_a: ps21@0 { | |
1118 | allwinner,pins = "PH12", "PH13"; | |
1119 | allwinner,function = "ps2"; | |
1120 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1121 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
0fc2b7af | 1122 | }; |
17eac031 MR |
1123 | }; |
1124 | ||
4790ecfa | 1125 | timer@01c20c00 { |
b4f26440 | 1126 | compatible = "allwinner,sun4i-a10-timer"; |
4790ecfa | 1127 | reg = <0x01c20c00 0x90>; |
19882b84 MR |
1128 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, |
1129 | <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, | |
1130 | <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, | |
1131 | <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, | |
1132 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, | |
1133 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | |
4790ecfa MR |
1134 | clocks = <&osc24M>; |
1135 | }; | |
1136 | ||
1137 | wdt: watchdog@01c20c90 { | |
ca5d04d9 | 1138 | compatible = "allwinner,sun4i-a10-wdt"; |
4790ecfa MR |
1139 | reg = <0x01c20c90 0x10>; |
1140 | }; | |
1141 | ||
b5d905c7 CC |
1142 | rtc: rtc@01c20d00 { |
1143 | compatible = "allwinner,sun7i-a20-rtc"; | |
1144 | reg = <0x01c20d00 0x20>; | |
19882b84 | 1145 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
b5d905c7 CC |
1146 | }; |
1147 | ||
8ec40c25 AB |
1148 | pwm: pwm@01c20e00 { |
1149 | compatible = "allwinner,sun7i-a20-pwm"; | |
1150 | reg = <0x01c20e00 0xc>; | |
1151 | clocks = <&osc24M>; | |
1152 | #pwm-cells = <3>; | |
1153 | status = "disabled"; | |
1154 | }; | |
1155 | ||
c1a0ee3d | 1156 | ir0: ir@01c21800 { |
1715a389 | 1157 | compatible = "allwinner,sun4i-a10-ir"; |
c1a0ee3d AB |
1158 | clocks = <&apb0_gates 6>, <&ir0_clk>; |
1159 | clock-names = "apb", "ir"; | |
19882b84 | 1160 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
c1a0ee3d AB |
1161 | reg = <0x01c21800 0x40>; |
1162 | status = "disabled"; | |
1163 | }; | |
1164 | ||
1165 | ir1: ir@01c21c00 { | |
1715a389 | 1166 | compatible = "allwinner,sun4i-a10-ir"; |
c1a0ee3d AB |
1167 | clocks = <&apb0_gates 7>, <&ir1_clk>; |
1168 | clock-names = "apb", "ir"; | |
19882b84 | 1169 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
c1a0ee3d AB |
1170 | reg = <0x01c21c00 0x40>; |
1171 | status = "disabled"; | |
1172 | }; | |
1173 | ||
a6a2d644 HG |
1174 | lradc: lradc@01c22800 { |
1175 | compatible = "allwinner,sun4i-a10-lradc-keys"; | |
1176 | reg = <0x01c22800 0x100>; | |
19882b84 | 1177 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
a6a2d644 HG |
1178 | status = "disabled"; |
1179 | }; | |
1180 | ||
2bad969f OS |
1181 | sid: eeprom@01c23800 { |
1182 | compatible = "allwinner,sun7i-a20-sid"; | |
1183 | reg = <0x01c23800 0x200>; | |
1184 | }; | |
1185 | ||
00f7ed8d | 1186 | rtp: rtp@01c25000 { |
8bf1b9b3 | 1187 | compatible = "allwinner,sun5i-a13-ts"; |
00f7ed8d | 1188 | reg = <0x01c25000 0x100>; |
19882b84 | 1189 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
41e7afb1 | 1190 | #thermal-sensor-cells = <0>; |
00f7ed8d HG |
1191 | }; |
1192 | ||
4790ecfa MR |
1193 | uart0: serial@01c28000 { |
1194 | compatible = "snps,dw-apb-uart"; | |
1195 | reg = <0x01c28000 0x400>; | |
19882b84 | 1196 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1197 | reg-shift = <2>; |
1198 | reg-io-width = <4>; | |
de7dc935 | 1199 | clocks = <&apb1_gates 16>; |
4790ecfa MR |
1200 | status = "disabled"; |
1201 | }; | |
1202 | ||
1203 | uart1: serial@01c28400 { | |
1204 | compatible = "snps,dw-apb-uart"; | |
1205 | reg = <0x01c28400 0x400>; | |
19882b84 | 1206 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1207 | reg-shift = <2>; |
1208 | reg-io-width = <4>; | |
de7dc935 | 1209 | clocks = <&apb1_gates 17>; |
4790ecfa MR |
1210 | status = "disabled"; |
1211 | }; | |
1212 | ||
1213 | uart2: serial@01c28800 { | |
1214 | compatible = "snps,dw-apb-uart"; | |
1215 | reg = <0x01c28800 0x400>; | |
19882b84 | 1216 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1217 | reg-shift = <2>; |
1218 | reg-io-width = <4>; | |
de7dc935 | 1219 | clocks = <&apb1_gates 18>; |
4790ecfa MR |
1220 | status = "disabled"; |
1221 | }; | |
1222 | ||
1223 | uart3: serial@01c28c00 { | |
1224 | compatible = "snps,dw-apb-uart"; | |
1225 | reg = <0x01c28c00 0x400>; | |
19882b84 | 1226 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1227 | reg-shift = <2>; |
1228 | reg-io-width = <4>; | |
de7dc935 | 1229 | clocks = <&apb1_gates 19>; |
4790ecfa MR |
1230 | status = "disabled"; |
1231 | }; | |
1232 | ||
1233 | uart4: serial@01c29000 { | |
1234 | compatible = "snps,dw-apb-uart"; | |
1235 | reg = <0x01c29000 0x400>; | |
19882b84 | 1236 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1237 | reg-shift = <2>; |
1238 | reg-io-width = <4>; | |
de7dc935 | 1239 | clocks = <&apb1_gates 20>; |
4790ecfa MR |
1240 | status = "disabled"; |
1241 | }; | |
1242 | ||
1243 | uart5: serial@01c29400 { | |
1244 | compatible = "snps,dw-apb-uart"; | |
1245 | reg = <0x01c29400 0x400>; | |
19882b84 | 1246 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1247 | reg-shift = <2>; |
1248 | reg-io-width = <4>; | |
de7dc935 | 1249 | clocks = <&apb1_gates 21>; |
4790ecfa MR |
1250 | status = "disabled"; |
1251 | }; | |
1252 | ||
1253 | uart6: serial@01c29800 { | |
1254 | compatible = "snps,dw-apb-uart"; | |
1255 | reg = <0x01c29800 0x400>; | |
19882b84 | 1256 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1257 | reg-shift = <2>; |
1258 | reg-io-width = <4>; | |
de7dc935 | 1259 | clocks = <&apb1_gates 22>; |
4790ecfa MR |
1260 | status = "disabled"; |
1261 | }; | |
1262 | ||
1263 | uart7: serial@01c29c00 { | |
1264 | compatible = "snps,dw-apb-uart"; | |
1265 | reg = <0x01c29c00 0x400>; | |
19882b84 | 1266 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1267 | reg-shift = <2>; |
1268 | reg-io-width = <4>; | |
de7dc935 | 1269 | clocks = <&apb1_gates 23>; |
4790ecfa MR |
1270 | status = "disabled"; |
1271 | }; | |
1272 | ||
428abbb8 | 1273 | i2c0: i2c@01c2ac00 { |
d8cacaa3 MR |
1274 | compatible = "allwinner,sun7i-a20-i2c", |
1275 | "allwinner,sun4i-a10-i2c"; | |
428abbb8 | 1276 | reg = <0x01c2ac00 0x400>; |
19882b84 | 1277 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
428abbb8 | 1278 | clocks = <&apb1_gates 0>; |
428abbb8 | 1279 | status = "disabled"; |
d1412aed HG |
1280 | #address-cells = <1>; |
1281 | #size-cells = <0>; | |
428abbb8 MR |
1282 | }; |
1283 | ||
1284 | i2c1: i2c@01c2b000 { | |
d8cacaa3 MR |
1285 | compatible = "allwinner,sun7i-a20-i2c", |
1286 | "allwinner,sun4i-a10-i2c"; | |
428abbb8 | 1287 | reg = <0x01c2b000 0x400>; |
19882b84 | 1288 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
428abbb8 | 1289 | clocks = <&apb1_gates 1>; |
428abbb8 | 1290 | status = "disabled"; |
d1412aed HG |
1291 | #address-cells = <1>; |
1292 | #size-cells = <0>; | |
428abbb8 MR |
1293 | }; |
1294 | ||
1295 | i2c2: i2c@01c2b400 { | |
d8cacaa3 MR |
1296 | compatible = "allwinner,sun7i-a20-i2c", |
1297 | "allwinner,sun4i-a10-i2c"; | |
428abbb8 | 1298 | reg = <0x01c2b400 0x400>; |
19882b84 | 1299 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
428abbb8 | 1300 | clocks = <&apb1_gates 2>; |
428abbb8 | 1301 | status = "disabled"; |
d1412aed HG |
1302 | #address-cells = <1>; |
1303 | #size-cells = <0>; | |
428abbb8 MR |
1304 | }; |
1305 | ||
1306 | i2c3: i2c@01c2b800 { | |
d8cacaa3 MR |
1307 | compatible = "allwinner,sun7i-a20-i2c", |
1308 | "allwinner,sun4i-a10-i2c"; | |
428abbb8 | 1309 | reg = <0x01c2b800 0x400>; |
19882b84 | 1310 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
428abbb8 | 1311 | clocks = <&apb1_gates 3>; |
428abbb8 | 1312 | status = "disabled"; |
d1412aed HG |
1313 | #address-cells = <1>; |
1314 | #size-cells = <0>; | |
428abbb8 MR |
1315 | }; |
1316 | ||
a3867045 | 1317 | i2c4: i2c@01c2c000 { |
d8cacaa3 MR |
1318 | compatible = "allwinner,sun7i-a20-i2c", |
1319 | "allwinner,sun4i-a10-i2c"; | |
a3867045 | 1320 | reg = <0x01c2c000 0x400>; |
19882b84 | 1321 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
428abbb8 | 1322 | clocks = <&apb1_gates 15>; |
428abbb8 | 1323 | status = "disabled"; |
d1412aed HG |
1324 | #address-cells = <1>; |
1325 | #size-cells = <0>; | |
428abbb8 MR |
1326 | }; |
1327 | ||
c40b8d58 CYT |
1328 | gmac: ethernet@01c50000 { |
1329 | compatible = "allwinner,sun7i-a20-gmac"; | |
1330 | reg = <0x01c50000 0x10000>; | |
19882b84 | 1331 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
c40b8d58 CYT |
1332 | interrupt-names = "macirq"; |
1333 | clocks = <&ahb_gates 49>, <&gmac_tx_clk>; | |
1334 | clock-names = "stmmaceth", "allwinner_gmac_tx"; | |
1335 | snps,pbl = <2>; | |
1336 | snps,fixed-burst; | |
1337 | snps,force_sf_dma_mode; | |
1338 | status = "disabled"; | |
1339 | #address-cells = <1>; | |
1340 | #size-cells = <0>; | |
1341 | }; | |
1342 | ||
31f8ad38 MR |
1343 | hstimer@01c60000 { |
1344 | compatible = "allwinner,sun7i-a20-hstimer"; | |
1345 | reg = <0x01c60000 0x1000>; | |
19882b84 MR |
1346 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, |
1347 | <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, | |
1348 | <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, | |
1349 | <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
31f8ad38 MR |
1350 | clocks = <&ahb_gates 28>; |
1351 | }; | |
1352 | ||
4790ecfa MR |
1353 | gic: interrupt-controller@01c81000 { |
1354 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
1355 | reg = <0x01c81000 0x1000>, | |
1356 | <0x01c82000 0x1000>, | |
1357 | <0x01c84000 0x2000>, | |
1358 | <0x01c86000 0x2000>; | |
1359 | interrupt-controller; | |
1360 | #interrupt-cells = <3>; | |
19882b84 | 1361 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
4790ecfa | 1362 | }; |
196654ae VP |
1363 | |
1364 | ps20: ps2@01c2a000 { | |
1365 | compatible = "allwinner,sun4i-a10-ps2"; | |
1366 | reg = <0x01c2a000 0x400>; | |
1367 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
1368 | clocks = <&apb1_gates 6>; | |
1369 | status = "disabled"; | |
1370 | }; | |
1371 | ||
1372 | ps21: ps2@01c2a400 { | |
1373 | compatible = "allwinner,sun4i-a10-ps2"; | |
1374 | reg = <0x01c2a400 0x400>; | |
1375 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
1376 | clocks = <&apb1_gates 7>; | |
1377 | status = "disabled"; | |
4790ecfa MR |
1378 | }; |
1379 | }; | |
1380 | }; |