[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / sun8i-a23-a33.dtsi

/*
 * Copyright 2014 Chen-Yu Tsai
 *
 * Chen-Yu Tsai <wens@csie.org>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton.dtsi"

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>

/ {
	interrupt-parent = <&gic>;

	chosen {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		simplefb_lcd: framebuffer@0 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0";
			clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
				 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
				 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
			status = "disabled";
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <24000000>;
		arm,cpu-registers-not-fw-configured;
	};

	cpus {
		enable-method = "allwinner,sun8i-a23";
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc24M: osc24M_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		osc32k: osc32k_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		dma: dma-controller@01c02000 {
			compatible = "allwinner,sun8i-a23-dma";
			reg = <0x01c02000 0x1000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_DMA>;
			resets = <&ccu RST_BUS_DMA>;
			#dma-cells = <1>;
		};

		mmc0: mmc@01c0f000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c0f000 0x1000>;
			clocks = <&ccu CLK_BUS_MMC0>,
				 <&ccu CLK_MMC0>,
				 <&ccu CLK_MMC0_OUTPUT>,
				 <&ccu CLK_MMC0_SAMPLE>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			resets = <&ccu RST_BUS_MMC0>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc1: mmc@01c10000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c10000 0x1000>;
			clocks = <&ccu CLK_BUS_MMC1>,
				 <&ccu CLK_MMC1>,
				 <&ccu CLK_MMC1_OUTPUT>,
				 <&ccu CLK_MMC1_SAMPLE>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			resets = <&ccu RST_BUS_MMC1>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc2: mmc@01c11000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c11000 0x1000>;
			clocks = <&ccu CLK_BUS_MMC2>,
				 <&ccu CLK_MMC2>,
				 <&ccu CLK_MMC2_OUTPUT>,
				 <&ccu CLK_MMC2_SAMPLE>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			resets = <&ccu RST_BUS_MMC2>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		nfc: nand@01c03000 {
			compatible = "allwinner,sun4i-a10-nand";
			reg = <0x01c03000 0x1000>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
			clock-names = "ahb", "mod";
			resets = <&ccu RST_BUS_NAND>;
			reset-names = "ahb";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		ehci0: usb@01c1a000 {
			compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
			reg = <0x01c1a000 0x100>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_EHCI>;
			resets = <&ccu RST_BUS_EHCI>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci0: usb@01c1a400 {
			compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
			reg = <0x01c1a400 0x100>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
			resets = <&ccu RST_BUS_OHCI>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		ccu: clock@01c20000 {
			reg = <0x01c20000 0x400>;
			clocks = <&osc24M>, <&osc32k>;
			clock-names = "hosc", "losc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		pio: pinctrl@01c20800 {
			/* compatible gets set in SoC specific dtsi file */
			reg = <0x01c20800 0x400>;
			/* interrupts get set in SoC specific dtsi file */
			clocks = <&ccu CLK_BUS_PIO>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <3>;
			#gpio-cells = <3>;

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PF2", "PF4";
				allwinner,function = "uart0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			mmc0_pins_a: mmc0@0 {
				allwinner,pins = "PF0", "PF1", "PF2",
						 "PF3", "PF4", "PF5";
				allwinner,function = "mmc0";
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			mmc1_pins_a: mmc1@0 {
				allwinner,pins = "PG0", "PG1", "PG2",
						 "PG3", "PG4", "PG5";
				allwinner,function = "mmc1";
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			mmc2_8bit_pins: mmc2_8bit {
				allwinner,pins = "PC5", "PC6", "PC8",
						 "PC9", "PC10", "PC11",
						 "PC12", "PC13", "PC14",
						 "PC15", "PC16";
				allwinner,function = "mmc2";
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			pwm0_pins: pwm0 {
				allwinner,pins = "PH0";
				allwinner,function = "pwm0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			i2c0_pins_a: i2c0@0 {
				allwinner,pins = "PH2", "PH3";
				allwinner,function = "i2c0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			i2c1_pins_a: i2c1@0 {
				allwinner,pins = "PH4", "PH5";
				allwinner,function = "i2c1";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			i2c2_pins_a: i2c2@0 {
				allwinner,pins = "PE12", "PE13";
				allwinner,function = "i2c2";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x01c20c00 0xa0>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc24M>;
		};

		wdt0: watchdog@01c20ca0 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x01c20ca0 0x20>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
		};

		pwm: pwm@01c21400 {
			compatible = "allwinner,sun7i-a20-pwm";
			reg = <0x01c21400 0xc>;
			clocks = <&osc24M>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		lradc: lradc@01c22800 {
			compatible = "allwinner,sun4i-a10-lradc-keys";
			reg = <0x01c22800 0x100>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART0>;
			resets = <&ccu RST_BUS_UART0>;
			dmas = <&dma 6>, <&dma 6>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART1>;
			resets = <&ccu RST_BUS_UART1>;
			dmas = <&dma 7>, <&dma 7>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART2>;
			resets = <&ccu RST_BUS_UART2>;
			dmas = <&dma 8>, <&dma 8>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART3>;
			resets = <&ccu RST_BUS_UART3>;
			dmas = <&dma 9>, <&dma 9>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART4>;
			resets = <&ccu RST_BUS_UART4>;
			dmas = <&dma 10>, <&dma 10>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		i2c0: i2c@01c2ac00 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C0>;
			resets = <&ccu RST_BUS_I2C0>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@01c2b000 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C1>;
			resets = <&ccu RST_BUS_I2C1>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@01c2b400 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C2>;
			resets = <&ccu RST_BUS_I2C2>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		gic: interrupt-controller@01c81000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x1000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		rtc: rtc@01f00000 {
			compatible = "allwinner,sun6i-a31-rtc";
			reg = <0x01f00000 0x54>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
		};

		nmi_intc: interrupt-controller@01f00c0c {
			compatible = "allwinner,sun6i-a31-sc-nmi";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x01f00c0c 0x38>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		};

		prcm@01f01400 {
			compatible = "allwinner,sun8i-a23-prcm";
			reg = <0x01f01400 0x200>;

			ar100: ar100_clk {
				compatible = "fixed-factor-clock";
				#clock-cells = <0>;
				clock-div = <1>;
				clock-mult = <1>;
				clocks = <&osc24M>;
				clock-output-names = "ar100";
			};

			ahb0: ahb0_clk {
				compatible = "fixed-factor-clock";
				#clock-cells = <0>;
				clock-div = <1>;
				clock-mult = <1>;
				clocks = <&ar100>;
				clock-output-names = "ahb0";
			};

			apb0: apb0_clk {
				compatible = "allwinner,sun8i-a23-apb0-clk";
				#clock-cells = <0>;
				clocks = <&ahb0>;
				clock-output-names = "apb0";
			};

			apb0_gates: apb0_gates_clk {
				compatible = "allwinner,sun8i-a23-apb0-gates-clk";
				#clock-cells = <1>;
				clocks = <&apb0>;
				clock-output-names = "apb0_pio", "apb0_timer",
						"apb0_rsb", "apb0_uart",
						"apb0_i2c";
			};

			apb0_rst: apb0_rst {
				compatible = "allwinner,sun6i-a31-clock-reset";
				#reset-cells = <1>;
			};
		};

		cpucfg@01f01c00 {
			compatible = "allwinner,sun8i-a23-cpuconfig";
			reg = <0x01f01c00 0x300>;
		};

		r_uart: serial@01f02800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01f02800 0x400>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb0_gates 4>;
			resets = <&apb0_rst 4>;
			status = "disabled";
		};

		r_pio: pinctrl@01f02c00 {
			compatible = "allwinner,sun8i-a23-r-pinctrl";
			reg = <0x01f02c00 0x400>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb0_gates 0>;
			resets = <&apb0_rst 0>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <3>;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			r_rsb_pins: r_rsb {
				allwinner,pins = "PL0", "PL1";
				allwinner,function = "s_rsb";
				allwinner,drive = <SUN4I_PINCTRL_20_MA>;
				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
			};

			r_uart_pins_a: r_uart@0 {
				allwinner,pins = "PL2", "PL3";
				allwinner,function = "s_uart";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};
		};

		r_rsb: rsb@01f03400 {
			compatible = "allwinner,sun8i-a23-rsb";
			reg = <0x01f03400 0x400>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb0_gates 3>;
			clock-frequency = <3000000>;
			resets = <&apb0_rst 3>;
			pinctrl-names = "default";
			pinctrl-0 = <&r_rsb_pins>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};
};
Commit	Line	Data
a0e9e9be VP	1	/*
	2	* Copyright 2014 Chen-Yu Tsai
	3	*
	4	* Chen-Yu Tsai <wens@csie.org>
	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
	11	* a) This file is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This file is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* Or, alternatively,
	22	*
	23	* b) Permission is hereby granted, free of charge, to any person
	24	* obtaining a copy of this software and associated documentation
	25	* files (the "Software"), to deal in the Software without
	26	* restriction, including without limitation the rights to use,
	27	* copy, modify, merge, publish, distribute, sublicense, and/or
	28	* sell copies of the Software, and to permit persons to whom the
	29	* Software is furnished to do so, subject to the following
	30	* conditions:
	31	*
	32	* The above copyright notice and this permission notice shall be
	33	* included in all copies or substantial portions of the Software.
	34	*
	35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	37	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	38	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	39	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	41	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	42	* OTHER DEALINGS IN THE SOFTWARE.
	43	*/
	44
	45	#include "skeleton.dtsi"
	46
	47	#include <dt-bindings/interrupt-controller/arm-gic.h>
	48
2c89ce4f	49	#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
a0e9e9be	50	#include <dt-bindings/pinctrl/sun4i-a10.h>
2c89ce4f	51	#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
a0e9e9be VP	52
	53	/ {
	54	interrupt-parent = <&gic>;
	55
	56	chosen {
	57	#address-cells = <1>;
	58	#size-cells = <1>;
	59	ranges;
	60
aea4c395	61	simplefb_lcd: framebuffer@0 {
a0e9e9be VP	62	compatible = "allwinner,simple-framebuffer",
	63	"simple-framebuffer";
	64	allwinner,pipeline = "de_be0-lcd0";
2c89ce4f MR	65	clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
	66	<&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
	67	<&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
a0e9e9be VP	68	status = "disabled";
	69	};
	70	};
	71
	72	timer {
	73	compatible = "arm,armv7-timer";
	74	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	75	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	76	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	77	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	78	clock-frequency = <24000000>;
	79	arm,cpu-registers-not-fw-configured;
	80	};
	81
	82	cpus {
	83	enable-method = "allwinner,sun8i-a23";
	84	#address-cells = <1>;
	85	#size-cells = <0>;
	86
	87	cpu@0 {
	88	compatible = "arm,cortex-a7";
	89	device_type = "cpu";
	90	reg = <0>;
	91	};
	92
	93	cpu@1 {
	94	compatible = "arm,cortex-a7";
	95	device_type = "cpu";
	96	reg = <1>;
	97	};
	98	};
	99
	100	clocks {
	101	#address-cells = <1>;
	102	#size-cells = <1>;
	103	ranges;
	104
	105	osc24M: osc24M_clk {
	106	#clock-cells = <0>;
	107	compatible = "fixed-clock";
	108	clock-frequency = <24000000>;
	109	clock-output-names = "osc24M";
	110	};
	111
	112	osc32k: osc32k_clk {
	113	#clock-cells = <0>;
	114	compatible = "fixed-clock";
	115	clock-frequency = <32768>;
	116	clock-output-names = "osc32k";
	117	};
a0e9e9be VP	118	};
	119
	120	soc@01c00000 {
	121	compatible = "simple-bus";
	122	#address-cells = <1>;
	123	#size-cells = <1>;
	124	ranges;
	125
	126	dma: dma-controller@01c02000 {
	127	compatible = "allwinner,sun8i-a23-dma";
	128	reg = <0x01c02000 0x1000>;
	129	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
2c89ce4f MR	130	clocks = <&ccu CLK_BUS_DMA>;
2c89ce4f MR	131	resets = <&ccu RST_BUS_DMA>;
a0e9e9be VP	132	#dma-cells = <1>;
	133	};
	134
	135	mmc0: mmc@01c0f000 {
	136	compatible = "allwinner,sun5i-a13-mmc";
	137	reg = <0x01c0f000 0x1000>;
2c89ce4f MR	138	clocks = <&ccu CLK_BUS_MMC0>,
	139	<&ccu CLK_MMC0>,
	140	<&ccu CLK_MMC0_OUTPUT>,
	141	<&ccu CLK_MMC0_SAMPLE>;
a0e9e9be VP	142	clock-names = "ahb",
	143	"mmc",
	144	"output",
	145	"sample";
2c89ce4f	146	resets = <&ccu RST_BUS_MMC0>;
a0e9e9be VP	147	reset-names = "ahb";
	148	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	149	status = "disabled";
	150	#address-cells = <1>;
	151	#size-cells = <0>;
	152	};
	153
	154	mmc1: mmc@01c10000 {
	155	compatible = "allwinner,sun5i-a13-mmc";
	156	reg = <0x01c10000 0x1000>;
2c89ce4f MR	157	clocks = <&ccu CLK_BUS_MMC1>,
	158	<&ccu CLK_MMC1>,
	159	<&ccu CLK_MMC1_OUTPUT>,
	160	<&ccu CLK_MMC1_SAMPLE>;
a0e9e9be VP	161	clock-names = "ahb",
	162	"mmc",
	163	"output",
	164	"sample";
2c89ce4f	165	resets = <&ccu RST_BUS_MMC1>;
a0e9e9be VP	166	reset-names = "ahb";
	167	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	168	status = "disabled";
	169	#address-cells = <1>;
	170	#size-cells = <0>;
	171	};
	172
	173	mmc2: mmc@01c11000 {
	174	compatible = "allwinner,sun5i-a13-mmc";
	175	reg = <0x01c11000 0x1000>;
2c89ce4f MR	176	clocks = <&ccu CLK_BUS_MMC2>,
	177	<&ccu CLK_MMC2>,
	178	<&ccu CLK_MMC2_OUTPUT>,
	179	<&ccu CLK_MMC2_SAMPLE>;
a0e9e9be VP	180	clock-names = "ahb",
	181	"mmc",
	182	"output",
	183	"sample";
2c89ce4f	184	resets = <&ccu RST_BUS_MMC2>;
a0e9e9be VP	185	reset-names = "ahb";
	186	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	187	status = "disabled";
	188	#address-cells = <1>;
	189	#size-cells = <0>;
	190	};
	191
d7b843df IZ	192	nfc: nand@01c03000 {
	193	compatible = "allwinner,sun4i-a10-nand";
	194	reg = <0x01c03000 0x1000>;
	195	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
2c89ce4f	196	clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
d7b843df	197	clock-names = "ahb", "mod";
2c89ce4f	198	resets = <&ccu RST_BUS_NAND>;
d7b843df IZ	199	reset-names = "ahb";
	200	status = "disabled";
	201	#address-cells = <1>;
	202	#size-cells = <0>;
	203	};
	204
e385c09c CYT	205	ehci0: usb@01c1a000 {
	206	compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
	207	reg = <0x01c1a000 0x100>;
	208	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2c89ce4f MR	209	clocks = <&ccu CLK_BUS_EHCI>;
2c89ce4f MR	210	resets = <&ccu RST_BUS_EHCI>;
e385c09c CYT	211	phys = <&usbphy 1>;
	212	phy-names = "usb";
	213	status = "disabled";
	214	};
	215
	216	ohci0: usb@01c1a400 {
	217	compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
	218	reg = <0x01c1a400 0x100>;
	219	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
2c89ce4f MR	220	clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
2c89ce4f MR	221	resets = <&ccu RST_BUS_OHCI>;
e385c09c CYT	222	phys = <&usbphy 1>;
	223	phy-names = "usb";
	224	status = "disabled";
	225	};
	226
2c89ce4f MR	227	ccu: clock@01c20000 {
	228	reg = <0x01c20000 0x400>;
	229	clocks = <&osc24M>, <&osc32k>;
	230	clock-names = "hosc", "losc";
	231	#clock-cells = <1>;
	232	#reset-cells = <1>;
	233	};
	234
a0e9e9be VP	235	pio: pinctrl@01c20800 {
	236	/* compatible gets set in SoC specific dtsi file */
	237	reg = <0x01c20800 0x400>;
	238	/* interrupts get set in SoC specific dtsi file */
2c89ce4f	239	clocks = <&ccu CLK_BUS_PIO>;
a0e9e9be VP	240	gpio-controller;
a0e9e9be VP	241	interrupt-controller;
b03e0816	242	#interrupt-cells = <3>;
a0e9e9be VP	243	#gpio-cells = <3>;
	244
	245	uart0_pins_a: uart0@0 {
	246	allwinner,pins = "PF2", "PF4";
	247	allwinner,function = "uart0";
	248	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	249	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	250	};
	251
	252	mmc0_pins_a: mmc0@0 {
	253	allwinner,pins = "PF0", "PF1", "PF2",
	254	"PF3", "PF4", "PF5";
	255	allwinner,function = "mmc0";
	256	allwinner,drive = <SUN4I_PINCTRL_30_MA>;
	257	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	258	};
	259
	260	mmc1_pins_a: mmc1@0 {
	261	allwinner,pins = "PG0", "PG1", "PG2",
	262	"PG3", "PG4", "PG5";
	263	allwinner,function = "mmc1";
	264	allwinner,drive = <SUN4I_PINCTRL_30_MA>;
	265	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	266	};
	267
93b129d6 CYT	268	mmc2_8bit_pins: mmc2_8bit {
	269	allwinner,pins = "PC5", "PC6", "PC8",
	270	"PC9", "PC10", "PC11",
	271	"PC12", "PC13", "PC14",
3b5d8dce	272	"PC15", "PC16";
93b129d6 CYT	273	allwinner,function = "mmc2";
	274	allwinner,drive = <SUN4I_PINCTRL_30_MA>;
	275	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	276	};
	277
29a0d085 CYT	278	pwm0_pins: pwm0 {
	279	allwinner,pins = "PH0";
	280	allwinner,function = "pwm0";
	281	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	282	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	283	};
	284
a0e9e9be VP	285	i2c0_pins_a: i2c0@0 {
	286	allwinner,pins = "PH2", "PH3";
	287	allwinner,function = "i2c0";
	288	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	289	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	290	};
	291
	292	i2c1_pins_a: i2c1@0 {
	293	allwinner,pins = "PH4", "PH5";
	294	allwinner,function = "i2c1";
	295	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	296	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	297	};
	298
	299	i2c2_pins_a: i2c2@0 {
	300	allwinner,pins = "PE12", "PE13";
	301	allwinner,function = "i2c2";
	302	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	303	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	304	};
	305	};
	306
a0e9e9be VP	307	timer@01c20c00 {
	308	compatible = "allwinner,sun4i-a10-timer";
	309	reg = <0x01c20c00 0xa0>;
	310	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	311	<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	312	clocks = <&osc24M>;
	313	};
	314
	315	wdt0: watchdog@01c20ca0 {
	316	compatible = "allwinner,sun6i-a31-wdt";
	317	reg = <0x01c20ca0 0x20>;
	318	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	319	};
	320
832f977c CYT	321	pwm: pwm@01c21400 {
	322	compatible = "allwinner,sun7i-a20-pwm";
	323	reg = <0x01c21400 0xc>;
	324	clocks = <&osc24M>;
	325	#pwm-cells = <3>;
	326	status = "disabled";
	327	};
	328
a0e9e9be VP	329	lradc: lradc@01c22800 {
	330	compatible = "allwinner,sun4i-a10-lradc-keys";
	331	reg = <0x01c22800 0x100>;
	332	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	333	status = "disabled";
	334	};
	335
	336	uart0: serial@01c28000 {
	337	compatible = "snps,dw-apb-uart";
	338	reg = <0x01c28000 0x400>;
	339	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	340	reg-shift = <2>;
	341	reg-io-width = <4>;
2c89ce4f MR	342	clocks = <&ccu CLK_BUS_UART0>;
2c89ce4f MR	343	resets = <&ccu RST_BUS_UART0>;
a0e9e9be VP	344	dmas = <&dma 6>, <&dma 6>;
	345	dma-names = "rx", "tx";
	346	status = "disabled";
	347	};
	348
	349	uart1: serial@01c28400 {
	350	compatible = "snps,dw-apb-uart";
	351	reg = <0x01c28400 0x400>;
	352	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	353	reg-shift = <2>;
	354	reg-io-width = <4>;
2c89ce4f MR	355	clocks = <&ccu CLK_BUS_UART1>;
2c89ce4f MR	356	resets = <&ccu RST_BUS_UART1>;
a0e9e9be VP	357	dmas = <&dma 7>, <&dma 7>;
	358	dma-names = "rx", "tx";
	359	status = "disabled";
	360	};
	361
	362	uart2: serial@01c28800 {
	363	compatible = "snps,dw-apb-uart";
	364	reg = <0x01c28800 0x400>;
	365	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	366	reg-shift = <2>;
	367	reg-io-width = <4>;
2c89ce4f MR	368	clocks = <&ccu CLK_BUS_UART2>;
2c89ce4f MR	369	resets = <&ccu RST_BUS_UART2>;
a0e9e9be VP	370	dmas = <&dma 8>, <&dma 8>;
	371	dma-names = "rx", "tx";
	372	status = "disabled";
	373	};
	374
	375	uart3: serial@01c28c00 {
	376	compatible = "snps,dw-apb-uart";
	377	reg = <0x01c28c00 0x400>;
	378	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	379	reg-shift = <2>;
	380	reg-io-width = <4>;
2c89ce4f MR	381	clocks = <&ccu CLK_BUS_UART3>;
2c89ce4f MR	382	resets = <&ccu RST_BUS_UART3>;
a0e9e9be VP	383	dmas = <&dma 9>, <&dma 9>;
	384	dma-names = "rx", "tx";
	385	status = "disabled";
	386	};
	387
	388	uart4: serial@01c29000 {
	389	compatible = "snps,dw-apb-uart";
	390	reg = <0x01c29000 0x400>;
	391	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	392	reg-shift = <2>;
	393	reg-io-width = <4>;
2c89ce4f MR	394	clocks = <&ccu CLK_BUS_UART4>;
2c89ce4f MR	395	resets = <&ccu RST_BUS_UART4>;
a0e9e9be VP	396	dmas = <&dma 10>, <&dma 10>;
	397	dma-names = "rx", "tx";
	398	status = "disabled";
	399	};
	400
	401	i2c0: i2c@01c2ac00 {
	402	compatible = "allwinner,sun6i-a31-i2c";
	403	reg = <0x01c2ac00 0x400>;
	404	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2c89ce4f MR	405	clocks = <&ccu CLK_BUS_I2C0>;
2c89ce4f MR	406	resets = <&ccu RST_BUS_I2C0>;
a0e9e9be VP	407	status = "disabled";
	408	#address-cells = <1>;
	409	#size-cells = <0>;
	410	};
	411
	412	i2c1: i2c@01c2b000 {
	413	compatible = "allwinner,sun6i-a31-i2c";
	414	reg = <0x01c2b000 0x400>;
	415	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2c89ce4f MR	416	clocks = <&ccu CLK_BUS_I2C1>;
2c89ce4f MR	417	resets = <&ccu RST_BUS_I2C1>;
a0e9e9be VP	418	status = "disabled";
	419	#address-cells = <1>;
	420	#size-cells = <0>;
	421	};
	422
	423	i2c2: i2c@01c2b400 {
	424	compatible = "allwinner,sun6i-a31-i2c";
	425	reg = <0x01c2b400 0x400>;
	426	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
2c89ce4f MR	427	clocks = <&ccu CLK_BUS_I2C2>;
2c89ce4f MR	428	resets = <&ccu RST_BUS_I2C2>;
a0e9e9be VP	429	status = "disabled";
	430	#address-cells = <1>;
	431	#size-cells = <0>;
	432	};
	433
	434	gic: interrupt-controller@01c81000 {
	435	compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
	436	reg = <0x01c81000 0x1000>,
	437	<0x01c82000 0x1000>,
	438	<0x01c84000 0x2000>,
	439	<0x01c86000 0x2000>;
	440	interrupt-controller;
	441	#interrupt-cells = <3>;
	442	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	443	};
	444
	445	rtc: rtc@01f00000 {
	446	compatible = "allwinner,sun6i-a31-rtc";
	447	reg = <0x01f00000 0x54>;
	448	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	449	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	450	};
	451
6c067963 CYT	452	nmi_intc: interrupt-controller@01f00c0c {
	453	compatible = "allwinner,sun6i-a31-sc-nmi";
	454	interrupt-controller;
	455	#interrupt-cells = <2>;
	456	reg = <0x01f00c0c 0x38>;
	457	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	458	};
	459
a0e9e9be VP	460	prcm@01f01400 {
	461	compatible = "allwinner,sun8i-a23-prcm";
	462	reg = <0x01f01400 0x200>;
	463
	464	ar100: ar100_clk {
	465	compatible = "fixed-factor-clock";
	466	#clock-cells = <0>;
	467	clock-div = <1>;
	468	clock-mult = <1>;
	469	clocks = <&osc24M>;
	470	clock-output-names = "ar100";
	471	};
	472
	473	ahb0: ahb0_clk {
	474	compatible = "fixed-factor-clock";
	475	#clock-cells = <0>;
	476	clock-div = <1>;
	477	clock-mult = <1>;
	478	clocks = <&ar100>;
	479	clock-output-names = "ahb0";
	480	};
	481
	482	apb0: apb0_clk {
	483	compatible = "allwinner,sun8i-a23-apb0-clk";
	484	#clock-cells = <0>;
	485	clocks = <&ahb0>;
	486	clock-output-names = "apb0";
	487	};
	488
	489	apb0_gates: apb0_gates_clk {
	490	compatible = "allwinner,sun8i-a23-apb0-gates-clk";
	491	#clock-cells = <1>;
	492	clocks = <&apb0>;
	493	clock-output-names = "apb0_pio", "apb0_timer",
	494	"apb0_rsb", "apb0_uart",
	495	"apb0_i2c";
	496	};
	497
	498	apb0_rst: apb0_rst {
	499	compatible = "allwinner,sun6i-a31-clock-reset";
	500	#reset-cells = <1>;
	501	};
	502	};
	503
	504	cpucfg@01f01c00 {
	505	compatible = "allwinner,sun8i-a23-cpuconfig";
	506	reg = <0x01f01c00 0x300>;
	507	};
	508
	509	r_uart: serial@01f02800 {
	510	compatible = "snps,dw-apb-uart";
	511	reg = <0x01f02800 0x400>;
	512	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	513	reg-shift = <2>;
	514	reg-io-width = <4>;
	515	clocks = <&apb0_gates 4>;
	516	resets = <&apb0_rst 4>;
	517	status = "disabled";
	518	};
	519
	520	r_pio: pinctrl@01f02c00 {
	521	compatible = "allwinner,sun8i-a23-r-pinctrl";
	522	reg = <0x01f02c00 0x400>;
	523	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
524	clocks = <&apb0_gates 0>;
525	resets = <&apb0_rst 0>;
526	gpio-controller;
527	interrupt-controller;
6d55d339	528	#interrupt-cells = <3>;
a0e9e9be VP	529	#address-cells = <1>;
	530	#size-cells = <0>;
	531	#gpio-cells = <3>;
	532
79d05ec9 CYT	533	r_rsb_pins: r_rsb {
	534	allwinner,pins = "PL0", "PL1";
	535	allwinner,function = "s_rsb";
	536	allwinner,drive = <SUN4I_PINCTRL_20_MA>;
	537	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
	538	};
	539
a0e9e9be VP	540	r_uart_pins_a: r_uart@0 {
	541	allwinner,pins = "PL2", "PL3";
	542	allwinner,function = "s_uart";
	543	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	544	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	545	};
	546	};
79d05ec9 CYT	547
	548	r_rsb: rsb@01f03400 {
	549	compatible = "allwinner,sun8i-a23-rsb";
	550	reg = <0x01f03400 0x400>;
	551	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	552	clocks = <&apb0_gates 3>;
	553	clock-frequency = <3000000>;
	554	resets = <&apb0_rst 3>;
	555	pinctrl-names = "default";
	556	pinctrl-0 = <&r_rsb_pins>;
	557	status = "disabled";
	558	#address-cells = <1>;
	559	#size-cells = <0>;
	560	};
a0e9e9be VP	561	};
a0e9e9be VP	562	};