[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / sun8i-a23.dtsi

/*
 * Copyright 2014 Chen-Yu Tsai
 *
 * Chen-Yu Tsai <wens@csie.org>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "skeleton.dtsi"

/ {
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &r_uart;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};
	};

	memory {
		reg = <0x40000000 0x40000000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc24M: osc24M_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		osc32k: osc32k_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};

		pll1: clk@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun8i-a23-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll1";
		};

		/* dummy clock until actually implemented */
		pll6: pll6_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <600000000>;
			clock-output-names = "pll6";
		};

		cpu: cpu_clk@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-cpu-clk";
			reg = <0x01c20050 0x4>;

			/*
			 * PLL1 is listed twice here.
			 * While it looks suspicious, it's actually documented
			 * that way both in the datasheet and in the code from
			 * Allwinner.
			 */
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
			clock-output-names = "cpu";
		};

		axi: axi_clk@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun8i-a23-axi-clk";
			reg = <0x01c20050 0x4>;
			clocks = <&cpu>;
			clock-output-names = "axi";
		};

		ahb1_mux: ahb1_mux_clk@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
			clock-output-names = "ahb1_mux";
		};

		ahb1: ahb1_clk@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-ahb-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb1_mux>;
			clock-output-names = "ahb1";
		};

		apb1: apb1_clk@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb1>;
			clock-output-names = "apb1";
		};

		ahb1_gates: clk@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb1>;
			clock-output-names = "ahb1_mipidsi", "ahb1_dma",
					"ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
					"ahb1_nand", "ahb1_sdram",
					"ahb1_hstimer", "ahb1_spi0",
					"ahb1_spi1", "ahb1_otg", "ahb1_ehci",
					"ahb1_ohci", "ahb1_ve", "ahb1_lcd",
					"ahb1_csi", "ahb1_be",	"ahb1_fe",
					"ahb1_gpu", "ahb1_spinlock",
					"ahb1_drc";
		};

		apb1_gates: clk@01c20068 {
			#clock-cells = <1>;
			compatible = "allwinner,sun8i-a23-apb1-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb1>;
			clock-output-names = "apb1_codec", "apb1_pio",
					"apb1_daudio0",	"apb1_daudio1";
		};

		apb2_mux: apb2_mux_clk@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb1-mux-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
			clock-output-names = "apb2_mux";
		};

		apb2: apb2_clk@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-apb2-div-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&apb2_mux>;
			clock-output-names = "apb2";
		};

		apb2_gates: clk@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun8i-a23-apb2-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb2>;
			clock-output-names = "apb2_i2c0", "apb2_i2c1",
					"apb2_i2c2", "apb2_uart0",
					"apb2_uart1", "apb2_uart2",
					"apb2_uart3", "apb2_uart4";
		};

		mmc0_clk: clk@01c20088 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c20088 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "mmc0";
		};

		mmc1_clk: clk@01c2008c {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c2008c 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "mmc1";
		};

		mmc2_clk: clk@01c20090 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c20090 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "mmc2";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		mmc0: mmc@01c0f000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c0f000 0x1000>;
			clocks = <&ahb1_gates 8>, <&mmc0_clk>;
			clock-names = "ahb", "mmc";
			resets = <&ahb1_rst 8>;
			reset-names = "ahb";
			interrupts = <0 60 4>;
			status = "disabled";
		};

		mmc1: mmc@01c10000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c10000 0x1000>;
			clocks = <&ahb1_gates 9>, <&mmc1_clk>;
			clock-names = "ahb", "mmc";
			resets = <&ahb1_rst 9>;
			reset-names = "ahb";
			interrupts = <0 61 4>;
			status = "disabled";
		};

		mmc2: mmc@01c11000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c11000 0x1000>;
			clocks = <&ahb1_gates 10>, <&mmc2_clk>;
			clock-names = "ahb", "mmc";
			resets = <&ahb1_rst 10>;
			reset-names = "ahb";
			interrupts = <0 62 4>;
			status = "disabled";
		};

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun8i-a23-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <0 11 4>,
				     <0 15 4>,
				     <0 17 4>;
			clocks = <&apb1_gates 5>;
			gpio-controller;
			interrupt-controller;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PF2", "PF4";
				allwinner,function = "uart0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			mmc0_pins_a: mmc0@0 {
				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
				allwinner,function = "mmc0";
				allwinner,drive = <2>;
				allwinner,pull = <0>;
			};

			mmc1_pins_a: mmc1@0 {
				allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
				allwinner,function = "mmc1";
				allwinner,drive = <2>;
				allwinner,pull = <0>;
			};

			i2c0_pins_a: i2c0@0 {
				allwinner,pins = "PH2", "PH3";
				allwinner,function = "i2c0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c1_pins_a: i2c1@0 {
				allwinner,pins = "PH4", "PH5";
				allwinner,function = "i2c1";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c2_pins_a: i2c2@0 {
				allwinner,pins = "PE12", "PE13";
				allwinner,function = "i2c2";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};
		};

		ahb1_rst: reset@01c202c0 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x01c202c0 0xc>;
		};

		apb1_rst: reset@01c202d0 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x01c202d0 0x4>;
		};

		apb2_rst: reset@01c202d8 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x01c202d8 0x4>;
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x01c20c00 0xa0>;
			interrupts = <0 18 4>,
				     <0 19 4>;
			clocks = <&osc24M>;
		};

		wdt0: watchdog@01c20ca0 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x01c20ca0 0x20>;
			interrupts = <0 25 4>;
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <0 0 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 16>;
			resets = <&apb2_rst 16>;
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <0 1 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 17>;
			resets = <&apb2_rst 17>;
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <0 2 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 18>;
			resets = <&apb2_rst 18>;
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <0 3 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 19>;
			resets = <&apb2_rst 19>;
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <0 4 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 20>;
			resets = <&apb2_rst 20>;
			status = "disabled";
		};

		i2c0: i2c@01c2ac00 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <0 6 4>;
			clocks = <&apb2_gates 0>;
			resets = <&apb2_rst 0>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@01c2b000 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <0 7 4>;
			clocks = <&apb2_gates 1>;
			resets = <&apb2_rst 1>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@01c2b400 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <0 8 4>;
			clocks = <&apb2_gates 2>;
			resets = <&apb2_rst 2>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		gic: interrupt-controller@01c81000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x1000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <1 9 0xf04>;
		};

		rtc: rtc@01f00000 {
			compatible = "allwinner,sun6i-a31-rtc";
			reg = <0x01f00000 0x54>;
			interrupts = <0 40 4>, <0 41 4>;
		};

		prcm@01f01400 {
			compatible = "allwinner,sun8i-a23-prcm";
			reg = <0x01f01400 0x200>;

			ar100: ar100_clk {
				compatible = "fixed-factor-clock";
				#clock-cells = <0>;
				clock-div = <1>;
				clock-mult = <1>;
				clocks = <&osc24M>;
				clock-output-names = "ar100";
			};

			ahb0: ahb0_clk {
				compatible = "fixed-factor-clock";
				#clock-cells = <0>;
				clock-div = <1>;
				clock-mult = <1>;
				clocks = <&ar100>;
				clock-output-names = "ahb0";
			};

			apb0: apb0_clk {
				compatible = "allwinner,sun8i-a23-apb0-clk";
				#clock-cells = <0>;
				clocks = <&ahb0>;
				clock-output-names = "apb0";
			};

			apb0_gates: apb0_gates_clk {
				compatible = "allwinner,sun8i-a23-apb0-gates-clk";
				#clock-cells = <1>;
				clocks = <&apb0>;
				clock-output-names = "apb0_pio", "apb0_timer",
						"apb0_rsb", "apb0_uart",
						"apb0_i2c";
			};

			apb0_rst: apb0_rst {
				compatible = "allwinner,sun6i-a31-clock-reset";
				#reset-cells = <1>;
			};
		};

		r_uart: serial@01f02800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01f02800 0x400>;
			interrupts = <0 38 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb0_gates 4>;
			resets = <&apb0_rst 4>;
			status = "disabled";
		};

		r_pio: pinctrl@01f02c00 {
			compatible = "allwinner,sun8i-a23-r-pinctrl";
			reg = <0x01f02c00 0x400>;
			interrupts = <0 45 4>;
			clocks = <&apb0_gates 0>;
			resets = <&apb0_rst 0>;
			gpio-controller;
			interrupt-controller;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			r_uart_pins_a: r_uart@0 {
				allwinner,pins = "PL2", "PL3";
				allwinner,function = "s_uart";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};
		};
	};
};
Commit	Line	Data
fd6c10fb CYT	1	/*
	2	* Copyright 2014 Chen-Yu Tsai
	3	*
	4	* Chen-Yu Tsai <wens@csie.org>
	5	*
	6	* The code contained herein is licensed under the GNU General Public
	7	* License. You may obtain a copy of the GNU General Public License
	8	* Version 2 or later at the following locations:
	9	*
	10	* http://www.opensource.org/licenses/gpl-license.html
	11	* http://www.gnu.org/copyleft/gpl.html
	12	*/
	13
	14	/include/ "skeleton.dtsi"
	15
	16	/ {
	17	interrupt-parent = <&gic>;
	18
	19	aliases {
	20	serial0 = &uart0;
	21	serial1 = &uart1;
	22	serial2 = &uart2;
	23	serial3 = &uart3;
	24	serial4 = &uart4;
	25	serial5 = &r_uart;
	26	};
	27
	28	cpus {
	29	#address-cells = <1>;
	30	#size-cells = <0>;
	31
	32	cpu@0 {
	33	compatible = "arm,cortex-a7";
	34	device_type = "cpu";
	35	reg = <0>;
	36	};
	37
	38	cpu@1 {
	39	compatible = "arm,cortex-a7";
	40	device_type = "cpu";
	41	reg = <1>;
	42	};
	43	};
	44
	45	memory {
	46	reg = <0x40000000 0x40000000>;
	47	};
	48
	49	clocks {
	50	#address-cells = <1>;
	51	#size-cells = <1>;
	52	ranges;
	53
	54	osc24M: osc24M_clk {
	55	#clock-cells = <0>;
	56	compatible = "fixed-clock";
	57	clock-frequency = <24000000>;
	58	clock-output-names = "osc24M";
	59	};
	60
	61	osc32k: osc32k_clk {
	62	#clock-cells = <0>;
	63	compatible = "fixed-clock";
	64	clock-frequency = <32768>;
65	clock-output-names = "osc32k";
66	};
8e984240 CYT	67
	68	pll1: clk@01c20000 {
	69	#clock-cells = <0>;
	70	compatible = "allwinner,sun8i-a23-pll1-clk";
	71	reg = <0x01c20000 0x4>;
	72	clocks = <&osc24M>;
	73	clock-output-names = "pll1";
	74	};
	75
	76	/* dummy clock until actually implemented */
	77	pll6: pll6_clk {
	78	#clock-cells = <0>;
	79	compatible = "fixed-clock";
	80	clock-frequency = <600000000>;
	81	clock-output-names = "pll6";
	82	};
	83
	84	cpu: cpu_clk@01c20050 {
	85	#clock-cells = <0>;
	86	compatible = "allwinner,sun4i-a10-cpu-clk";
	87	reg = <0x01c20050 0x4>;
	88
	89	/*
	90	* PLL1 is listed twice here.
	91	* While it looks suspicious, it's actually documented
	92	* that way both in the datasheet and in the code from
	93	* Allwinner.
	94	*/
	95	clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
	96	clock-output-names = "cpu";
	97	};
	98
	99	axi: axi_clk@01c20050 {
	100	#clock-cells = <0>;
	101	compatible = "allwinner,sun8i-a23-axi-clk";
	102	reg = <0x01c20050 0x4>;
	103	clocks = <&cpu>;
	104	clock-output-names = "axi";
	105	};
	106
	107	ahb1_mux: ahb1_mux_clk@01c20054 {
	108	#clock-cells = <0>;
	109	compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
	110	reg = <0x01c20054 0x4>;
	111	clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
	112	clock-output-names = "ahb1_mux";
	113	};
	114
	115	ahb1: ahb1_clk@01c20054 {
	116	#clock-cells = <0>;
	117	compatible = "allwinner,sun4i-a10-ahb-clk";
	118	reg = <0x01c20054 0x4>;
	119	clocks = <&ahb1_mux>;
	120	clock-output-names = "ahb1";
	121	};
	122
	123	apb1: apb1_clk@01c20054 {
	124	#clock-cells = <0>;
	125	compatible = "allwinner,sun4i-a10-apb0-clk";
	126	reg = <0x01c20054 0x4>;
	127	clocks = <&ahb1>;
	128	clock-output-names = "apb1";
	129	};
	130
131	ahb1_gates: clk@01c20060 {
132	#clock-cells = <1>;
133	compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
134	reg = <0x01c20060 0x8>;
135	clocks = <&ahb1>;
136	clock-output-names = "ahb1_mipidsi", "ahb1_dma",
137	"ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
138	"ahb1_nand", "ahb1_sdram",
139	"ahb1_hstimer", "ahb1_spi0",
140	"ahb1_spi1", "ahb1_otg", "ahb1_ehci",
141	"ahb1_ohci", "ahb1_ve", "ahb1_lcd",
142	"ahb1_csi", "ahb1_be", "ahb1_fe",
143	"ahb1_gpu", "ahb1_spinlock",
144	"ahb1_drc";
145	};
146
147	apb1_gates: clk@01c20068 {
148	#clock-cells = <1>;
149	compatible = "allwinner,sun8i-a23-apb1-gates-clk";
150	reg = <0x01c20068 0x4>;
151	clocks = <&apb1>;
152	clock-output-names = "apb1_codec", "apb1_pio",
153	"apb1_daudio0", "apb1_daudio1";
154	};
155
156	apb2_mux: apb2_mux_clk@01c20058 {
157	#clock-cells = <0>;
158	compatible = "allwinner,sun4i-a10-apb1-mux-clk";
159	reg = <0x01c20058 0x4>;
160	clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
161	clock-output-names = "apb2_mux";
162	};
163
164	apb2: apb2_clk@01c20058 {
165	#clock-cells = <0>;
166	compatible = "allwinner,sun6i-a31-apb2-div-clk";
167	reg = <0x01c20058 0x4>;
168	clocks = <&apb2_mux>;
169	clock-output-names = "apb2";
170	};
171
172	apb2_gates: clk@01c2006c {
173	#clock-cells = <1>;
174	compatible = "allwinner,sun8i-a23-apb2-gates-clk";
175	reg = <0x01c2006c 0x4>;
176	clocks = <&apb2>;
177	clock-output-names = "apb2_i2c0", "apb2_i2c1",
178	"apb2_i2c2", "apb2_uart0",
179	"apb2_uart1", "apb2_uart2",
180	"apb2_uart3", "apb2_uart4";
181	};
4b7ecb38 CYT	182
	183	mmc0_clk: clk@01c20088 {
	184	#clock-cells = <0>;
	185	compatible = "allwinner,sun4i-a10-mod0-clk";
	186	reg = <0x01c20088 0x4>;
	187	clocks = <&osc24M>, <&pll6>;
	188	clock-output-names = "mmc0";
	189	};
	190
	191	mmc1_clk: clk@01c2008c {
	192	#clock-cells = <0>;
	193	compatible = "allwinner,sun4i-a10-mod0-clk";
	194	reg = <0x01c2008c 0x4>;
	195	clocks = <&osc24M>, <&pll6>;
	196	clock-output-names = "mmc1";
	197	};
	198
	199	mmc2_clk: clk@01c20090 {
	200	#clock-cells = <0>;
	201	compatible = "allwinner,sun4i-a10-mod0-clk";
	202	reg = <0x01c20090 0x4>;
	203	clocks = <&osc24M>, <&pll6>;
	204	clock-output-names = "mmc2";
	205	};
fd6c10fb CYT	206	};
	207
	208	soc@01c00000 {
	209	compatible = "simple-bus";
	210	#address-cells = <1>;
	211	#size-cells = <1>;
	212	ranges;
	213
eacda1f1 CYT	214	mmc0: mmc@01c0f000 {
	215	compatible = "allwinner,sun5i-a13-mmc";
	216	reg = <0x01c0f000 0x1000>;
	217	clocks = <&ahb1_gates 8>, <&mmc0_clk>;
	218	clock-names = "ahb", "mmc";
	219	resets = <&ahb1_rst 8>;
	220	reset-names = "ahb";
	221	interrupts = <0 60 4>;
	222	status = "disabled";
	223	};
	224
	225	mmc1: mmc@01c10000 {
	226	compatible = "allwinner,sun5i-a13-mmc";
	227	reg = <0x01c10000 0x1000>;
	228	clocks = <&ahb1_gates 9>, <&mmc1_clk>;
	229	clock-names = "ahb", "mmc";
	230	resets = <&ahb1_rst 9>;
	231	reset-names = "ahb";
	232	interrupts = <0 61 4>;
	233	status = "disabled";
	234	};
	235
	236	mmc2: mmc@01c11000 {
	237	compatible = "allwinner,sun5i-a13-mmc";
	238	reg = <0x01c11000 0x1000>;
	239	clocks = <&ahb1_gates 10>, <&mmc2_clk>;
	240	clock-names = "ahb", "mmc";
	241	resets = <&ahb1_rst 10>;
	242	reset-names = "ahb";
	243	interrupts = <0 62 4>;
	244	status = "disabled";
	245	};
	246
6b2b16f5 CYT	247	pio: pinctrl@01c20800 {
	248	compatible = "allwinner,sun8i-a23-pinctrl";
	249	reg = <0x01c20800 0x400>;
	250	interrupts = <0 11 4>,
	251	<0 15 4>,
	252	<0 17 4>;
	253	clocks = <&apb1_gates 5>;
	254	gpio-controller;
	255	interrupt-controller;
	256	#address-cells = <1>;
	257	#size-cells = <0>;
	258	#gpio-cells = <3>;
c4021571 CYT	259
	260	uart0_pins_a: uart0@0 {
	261	allwinner,pins = "PF2", "PF4";
	262	allwinner,function = "uart0";
	263	allwinner,drive = <0>;
	264	allwinner,pull = <0>;
	265	};
cdb6fd67 CYT	266
	267	mmc0_pins_a: mmc0@0 {
	268	allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
	269	allwinner,function = "mmc0";
	270	allwinner,drive = <2>;
	271	allwinner,pull = <0>;
	272	};
	273
	274	mmc1_pins_a: mmc1@0 {
	275	allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
	276	allwinner,function = "mmc1";
	277	allwinner,drive = <2>;
	278	allwinner,pull = <0>;
	279	};
1890f518 CYT	280
	281	i2c0_pins_a: i2c0@0 {
	282	allwinner,pins = "PH2", "PH3";
	283	allwinner,function = "i2c0";
	284	allwinner,drive = <0>;
	285	allwinner,pull = <0>;
	286	};
	287
	288	i2c1_pins_a: i2c1@0 {
	289	allwinner,pins = "PH4", "PH5";
	290	allwinner,function = "i2c1";
	291	allwinner,drive = <0>;
	292	allwinner,pull = <0>;
	293	};
	294
	295	i2c2_pins_a: i2c2@0 {
	296	allwinner,pins = "PE12", "PE13";
	297	allwinner,function = "i2c2";
	298	allwinner,drive = <0>;
	299	allwinner,pull = <0>;
	300	};
6b2b16f5 CYT	301	};
6b2b16f5 CYT	302
c571111a CYT	303	ahb1_rst: reset@01c202c0 {
	304	#reset-cells = <1>;
	305	compatible = "allwinner,sun6i-a31-clock-reset";
	306	reg = <0x01c202c0 0xc>;
	307	};
	308
	309	apb1_rst: reset@01c202d0 {
	310	#reset-cells = <1>;
	311	compatible = "allwinner,sun6i-a31-clock-reset";
	312	reg = <0x01c202d0 0x4>;
	313	};
	314
	315	apb2_rst: reset@01c202d8 {
	316	#reset-cells = <1>;
	317	compatible = "allwinner,sun6i-a31-clock-reset";
	318	reg = <0x01c202d8 0x4>;
	319	};
	320
fd6c10fb CYT	321	timer@01c20c00 {
	322	compatible = "allwinner,sun4i-a10-timer";
	323	reg = <0x01c20c00 0xa0>;
	324	interrupts = <0 18 4>,
	325	<0 19 4>;
	326	clocks = <&osc24M>;
	327	};
	328
	329	wdt0: watchdog@01c20ca0 {
	330	compatible = "allwinner,sun6i-a31-wdt";
	331	reg = <0x01c20ca0 0x20>;
	332	interrupts = <0 25 4>;
	333	};
	334
	335	uart0: serial@01c28000 {
	336	compatible = "snps,dw-apb-uart";
	337	reg = <0x01c28000 0x400>;
	338	interrupts = <0 0 4>;
	339	reg-shift = <2>;
	340	reg-io-width = <4>;
8e984240	341	clocks = <&apb2_gates 16>;
c571111a	342	resets = <&apb2_rst 16>;
fd6c10fb CYT	343	status = "disabled";
	344	};
	345
	346	uart1: serial@01c28400 {
	347	compatible = "snps,dw-apb-uart";
	348	reg = <0x01c28400 0x400>;
	349	interrupts = <0 1 4>;
	350	reg-shift = <2>;
	351	reg-io-width = <4>;
8e984240	352	clocks = <&apb2_gates 17>;
c571111a	353	resets = <&apb2_rst 17>;
fd6c10fb CYT	354	status = "disabled";
	355	};
	356
	357	uart2: serial@01c28800 {
	358	compatible = "snps,dw-apb-uart";
	359	reg = <0x01c28800 0x400>;
	360	interrupts = <0 2 4>;
	361	reg-shift = <2>;
	362	reg-io-width = <4>;
8e984240	363	clocks = <&apb2_gates 18>;
c571111a	364	resets = <&apb2_rst 18>;
fd6c10fb CYT	365	status = "disabled";
	366	};
	367
	368	uart3: serial@01c28c00 {
	369	compatible = "snps,dw-apb-uart";
	370	reg = <0x01c28c00 0x400>;
	371	interrupts = <0 3 4>;
	372	reg-shift = <2>;
	373	reg-io-width = <4>;
8e984240	374	clocks = <&apb2_gates 19>;
c571111a	375	resets = <&apb2_rst 19>;
fd6c10fb CYT	376	status = "disabled";
	377	};
	378
	379	uart4: serial@01c29000 {
	380	compatible = "snps,dw-apb-uart";
	381	reg = <0x01c29000 0x400>;
	382	interrupts = <0 4 4>;
	383	reg-shift = <2>;
	384	reg-io-width = <4>;
8e984240	385	clocks = <&apb2_gates 20>;
c571111a	386	resets = <&apb2_rst 20>;
fd6c10fb CYT	387	status = "disabled";
	388	};
	389
0a97ea3b CYT	390	i2c0: i2c@01c2ac00 {
	391	compatible = "allwinner,sun6i-a31-i2c";
	392	reg = <0x01c2ac00 0x400>;
	393	interrupts = <0 6 4>;
	394	clocks = <&apb2_gates 0>;
	395	resets = <&apb2_rst 0>;
	396	status = "disabled";
	397	#address-cells = <1>;
	398	#size-cells = <0>;
	399	};
	400
	401	i2c1: i2c@01c2b000 {
	402	compatible = "allwinner,sun6i-a31-i2c";
	403	reg = <0x01c2b000 0x400>;
	404	interrupts = <0 7 4>;
	405	clocks = <&apb2_gates 1>;
	406	resets = <&apb2_rst 1>;
	407	status = "disabled";
	408	#address-cells = <1>;
	409	#size-cells = <0>;
	410	};
	411
	412	i2c2: i2c@01c2b400 {
	413	compatible = "allwinner,sun6i-a31-i2c";
	414	reg = <0x01c2b400 0x400>;
	415	interrupts = <0 8 4>;
	416	clocks = <&apb2_gates 2>;
	417	resets = <&apb2_rst 2>;
	418	status = "disabled";
	419	#address-cells = <1>;
	420	#size-cells = <0>;
	421	};
	422
fd6c10fb CYT	423	gic: interrupt-controller@01c81000 {
	424	compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
	425	reg = <0x01c81000 0x1000>,
	426	<0x01c82000 0x1000>,
	427	<0x01c84000 0x2000>,
	428	<0x01c86000 0x2000>;
	429	interrupt-controller;
	430	#interrupt-cells = <3>;
	431	interrupts = <1 9 0xf04>;
	432	};
	433
3b1213f5 CYT	434	rtc: rtc@01f00000 {
	435	compatible = "allwinner,sun6i-a31-rtc";
	436	reg = <0x01f00000 0x54>;
	437	interrupts = <0 40 4>, <0 41 4>;
	438	};
	439
df02dd82 CYT	440	prcm@01f01400 {
	441	compatible = "allwinner,sun8i-a23-prcm";
	442	reg = <0x01f01400 0x200>;
	443
	444	ar100: ar100_clk {
	445	compatible = "fixed-factor-clock";
	446	#clock-cells = <0>;
	447	clock-div = <1>;
	448	clock-mult = <1>;
	449	clocks = <&osc24M>;
	450	clock-output-names = "ar100";
	451	};
	452
	453	ahb0: ahb0_clk {
	454	compatible = "fixed-factor-clock";
	455	#clock-cells = <0>;
	456	clock-div = <1>;
	457	clock-mult = <1>;
	458	clocks = <&ar100>;
	459	clock-output-names = "ahb0";
	460	};
	461
	462	apb0: apb0_clk {
	463	compatible = "allwinner,sun8i-a23-apb0-clk";
	464	#clock-cells = <0>;
	465	clocks = <&ahb0>;
	466	clock-output-names = "apb0";
	467	};
	468
	469	apb0_gates: apb0_gates_clk {
	470	compatible = "allwinner,sun8i-a23-apb0-gates-clk";
	471	#clock-cells = <1>;
	472	clocks = <&apb0>;
	473	clock-output-names = "apb0_pio", "apb0_timer",
	474	"apb0_rsb", "apb0_uart",
	475	"apb0_i2c";
	476	};
	477
	478	apb0_rst: apb0_rst {
	479	compatible = "allwinner,sun6i-a31-clock-reset";
	480	#reset-cells = <1>;
	481	};
	482	};
	483
fd6c10fb CYT	484	r_uart: serial@01f02800 {
	485	compatible = "snps,dw-apb-uart";
	486	reg = <0x01f02800 0x400>;
	487	interrupts = <0 38 4>;
	488	reg-shift = <2>;
	489	reg-io-width = <4>;
df02dd82 CYT	490	clocks = <&apb0_gates 4>;
df02dd82 CYT	491	resets = <&apb0_rst 4>;
fd6c10fb CYT	492	status = "disabled";
fd6c10fb CYT	493	};
b6a87112 CYT	494
	495	r_pio: pinctrl@01f02c00 {
	496	compatible = "allwinner,sun8i-a23-r-pinctrl";
	497	reg = <0x01f02c00 0x400>;
	498	interrupts = <0 45 4>;
	499	clocks = <&apb0_gates 0>;
	500	resets = <&apb0_rst 0>;
	501	gpio-controller;
	502	interrupt-controller;
	503	#address-cells = <1>;
	504	#size-cells = <0>;
	505	#gpio-cells = <3>;
81309791 CYT	506
	507	r_uart_pins_a: r_uart@0 {
	508	allwinner,pins = "PL2", "PL3";
	509	allwinner,function = "s_uart";
	510	allwinner,drive = <0>;
	511	allwinner,pull = <0>;
	512	};
b6a87112	513	};
fd6c10fb CYT	514	};
fd6c10fb CYT	515	};