projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| fd6c10fb CYT |
1 | /* |
| 2 | * Copyright 2014 Chen-Yu Tsai | |
| 3 | * | |
| 4 | * Chen-Yu Tsai <wens@csie.org> | |
| 5 | * | |
| 6 | * The code contained herein is licensed under the GNU General Public | |
| 7 | * License. You may obtain a copy of the GNU General Public License | |
| 8 | * Version 2 or later at the following locations: | |
| 9 | * | |
| 10 | * http://www.opensource.org/licenses/gpl-license.html | |
| 11 | * http://www.gnu.org/copyleft/gpl.html | |
| 12 | */ | |
| 13 | ||
| 14 | /include/ "skeleton.dtsi" | |
| 15 | ||
| 16 | / { | |
| 17 | interrupt-parent = <&gic>; | |
| 18 | ||
| 19 | aliases { | |
| 20 | serial0 = &uart0; | |
| 21 | serial1 = &uart1; | |
| 22 | serial2 = &uart2; | |
| 23 | serial3 = &uart3; | |
| 24 | serial4 = &uart4; | |
| 25 | serial5 = &r_uart; | |
| 26 | }; | |
| 27 | ||
| 28 | cpus { | |
| 29 | #address-cells = <1>; | |
| 30 | #size-cells = <0>; | |
| 31 | ||
| 32 | cpu@0 { | |
| 33 | compatible = "arm,cortex-a7"; | |
| 34 | device_type = "cpu"; | |
| 35 | reg = <0>; | |
| 36 | }; | |
| 37 | ||
| 38 | cpu@1 { | |
| 39 | compatible = "arm,cortex-a7"; | |
| 40 | device_type = "cpu"; | |
| 41 | reg = <1>; | |
| 42 | }; | |
| 43 | }; | |
| 44 | ||
| 45 | memory { | |
| 46 | reg = <0x40000000 0x40000000>; | |
| 47 | }; | |
| 48 | ||
| 49 | clocks { | |
| 50 | #address-cells = <1>; | |
| 51 | #size-cells = <1>; | |
| 52 | ranges; | |
| 53 | ||
| 54 | osc24M: osc24M_clk { | |
| 55 | #clock-cells = <0>; | |
| 56 | compatible = "fixed-clock"; | |
| 57 | clock-frequency = <24000000>; | |
| 58 | clock-output-names = "osc24M"; | |
| 59 | }; | |
| 60 | ||
| 61 | osc32k: osc32k_clk { | |
| 62 | #clock-cells = <0>; | |
| 63 | compatible = "fixed-clock"; | |
| 64 | clock-frequency = <32768>; | |
| 65 | clock-output-names = "osc32k"; | |
| 66 | }; | |
| 67 | }; | |
| 68 | ||
| 69 | soc@01c00000 { | |
| 70 | compatible = "simple-bus"; | |
| 71 | #address-cells = <1>; | |
| 72 | #size-cells = <1>; | |
| 73 | ranges; | |
| 74 | ||
| 75 | timer@01c20c00 { | |
| 76 | compatible = "allwinner,sun4i-a10-timer"; | |
| 77 | reg = <0x01c20c00 0xa0>; | |
| 78 | interrupts = <0 18 4>, | |
| 79 | <0 19 4>; | |
| 80 | clocks = <&osc24M>; | |
| 81 | }; | |
| 82 | ||
| 83 | wdt0: watchdog@01c20ca0 { | |
| 84 | compatible = "allwinner,sun6i-a31-wdt"; | |
| 85 | reg = <0x01c20ca0 0x20>; | |
| 86 | interrupts = <0 25 4>; | |
| 87 | }; | |
| 88 | ||
| 89 | uart0: serial@01c28000 { | |
| 90 | compatible = "snps,dw-apb-uart"; | |
| 91 | reg = <0x01c28000 0x400>; | |
| 92 | interrupts = <0 0 4>; | |
| 93 | reg-shift = <2>; | |
| 94 | reg-io-width = <4>; | |
| 95 | clocks = <&osc24M>; | |
| 96 | status = "disabled"; | |
| 97 | }; | |
| 98 | ||
| 99 | uart1: serial@01c28400 { | |
| 100 | compatible = "snps,dw-apb-uart"; | |
| 101 | reg = <0x01c28400 0x400>; | |
| 102 | interrupts = <0 1 4>; | |
| 103 | reg-shift = <2>; | |
| 104 | reg-io-width = <4>; | |
| 105 | clocks = <&osc24M>; | |
| 106 | status = "disabled"; | |
| 107 | }; | |
| 108 | ||
| 109 | uart2: serial@01c28800 { | |
| 110 | compatible = "snps,dw-apb-uart"; | |
| 111 | reg = <0x01c28800 0x400>; | |
| 112 | interrupts = <0 2 4>; | |
| 113 | reg-shift = <2>; | |
| 114 | reg-io-width = <4>; | |
| 115 | clocks = <&osc24M>; | |
| 116 | status = "disabled"; | |
| 117 | }; | |
| 118 | ||
| 119 | uart3: serial@01c28c00 { | |
| 120 | compatible = "snps,dw-apb-uart"; | |
| 121 | reg = <0x01c28c00 0x400>; | |
| 122 | interrupts = <0 3 4>; | |
| 123 | reg-shift = <2>; | |
| 124 | reg-io-width = <4>; | |
| 125 | clocks = <&osc24M>; | |
| 126 | status = "disabled"; | |
| 127 | }; | |
| 128 | ||
| 129 | uart4: serial@01c29000 { | |
| 130 | compatible = "snps,dw-apb-uart"; | |
| 131 | reg = <0x01c29000 0x400>; | |
| 132 | interrupts = <0 4 4>; | |
| 133 | reg-shift = <2>; | |
| 134 | reg-io-width = <4>; | |
| 135 | clocks = <&osc24M>; | |
| 136 | status = "disabled"; | |
| 137 | }; | |
| 138 | ||
| 139 | gic: interrupt-controller@01c81000 { | |
| 140 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
| 141 | reg = <0x01c81000 0x1000>, | |
| 142 | <0x01c82000 0x1000>, | |
| 143 | <0x01c84000 0x2000>, | |
| 144 | <0x01c86000 0x2000>; | |
| 145 | interrupt-controller; | |
| 146 | #interrupt-cells = <3>; | |
| 147 | interrupts = <1 9 0xf04>; | |
| 148 | }; | |
| 149 | ||
| 150 | r_uart: serial@01f02800 { | |
| 151 | compatible = "snps,dw-apb-uart"; | |
| 152 | reg = <0x01f02800 0x400>; | |
| 153 | interrupts = <0 38 4>; | |
| 154 | reg-shift = <2>; | |
| 155 | reg-io-width = <4>; | |
| 156 | clocks = <&osc24M>; | |
| 157 | status = "disabled"; | |
| 158 | }; | |
| 159 | }; | |
| 160 | }; |