[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / sun8i-a83t-bananapi-m3.dts

/*
 * Copyright 2017 Chen-Yu Tsai
 *
 * Chen-Yu Tsai <wens@csie.org>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;
#include "sun8i-a83t.dtsi"

#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Banana Pi BPI-M3";
	compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";

	aliases {
		ethernet0 = &emac;
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	leds {
		compatible = "gpio-leds";

		blue {
			label = "bananapi-m3:blue:usr";
			gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>;
		};

		green {
			label = "bananapi-m3:green:usr";
			gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>;
		};
	};

	reg_usb1_vbus: reg-usb1-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb1-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
		enable-active-high;
		gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
	};

	wifi_pwrseq: wifi_pwrseq {
		compatible = "mmc-pwrseq-simple";
		clocks = <&ac100_rtc 1>;
		clock-names = "ext_clock";
		/* The WiFi low power clock must be 32768 Hz */
		assigned-clocks = <&ac100_rtc 1>;
		assigned-clock-rates = <32768>;
		/* enables internal regulator and de-asserts reset */
		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
	};
};

&ehci0 {
	/* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
	status = "okay";

	/* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */
};

&emac {
	pinctrl-names = "default";
	pinctrl-0 = <&emac_rgmii_pins>;
	phy-supply = <&reg_sw>;
	phy-handle = <&rgmii_phy>;
	phy-mode = "rgmii";
	allwinner,rx-delay-ps = <700>;
	allwinner,tx-delay-ps = <700>;
	status = "okay";
};

&mdio {
	rgmii_phy: ethernet-phy@1 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <1>;
	};
};

&mmc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	vmmc-supply = <&reg_dcdc1>;
	bus-width = <4>;
	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
	cd-inverted;
	status = "okay";
};

&mmc1 {
	vmmc-supply = <&reg_dldo1>;
	vqmmc-supply = <&reg_dldo1>;
	mmc-pwrseq = <&wifi_pwrseq>;
	bus-width = <4>;
	non-removable;
	status = "okay";

	brcmf: wifi@1 {
		reg = <1>;
		compatible = "brcm,bcm4329-fmac";
		interrupt-parent = <&r_pio>;
		interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "host-wake";
	};
};

&mmc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc2_8bit_emmc_pins>;
	vmmc-supply = <&reg_dcdc1>;
	vqmmc-supply = <&reg_dcdc1>;
	bus-width = <8>;
	non-removable;
	cap-mmc-hw-reset;
	status = "okay";
};

&r_rsb {
	status = "okay";

	axp81x: pmic@3a3 {
		compatible = "x-powers,axp813";
		reg = <0x3a3>;
		interrupt-parent = <&r_intc>;
		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
		eldoin-supply = <&reg_dcdc1>;
		fldoin-supply = <&reg_dcdc5>;
		swin-supply = <&reg_dcdc1>;
		x-powers,drive-vbus-en;
	};

	ac100: codec@e89 {
		compatible = "x-powers,ac100";
		reg = <0xe89>;

		ac100_codec: codec {
			compatible = "x-powers,ac100-codec";
			interrupt-parent = <&r_pio>;
			interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
			#clock-cells = <0>;
			clock-output-names = "4M_adda";
		};

		ac100_rtc: rtc {
			compatible = "x-powers,ac100-rtc";
			interrupt-parent = <&r_intc>;
			interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&ac100_codec>;
			#clock-cells = <1>;
			clock-output-names = "cko1_rtc",
					     "cko2_rtc",
					     "cko3_rtc";
		};
	};
};

#include "axp81x.dtsi"

&reg_aldo1 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "vcc-1v8";
};

&reg_aldo2 {
	regulator-always-on;
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-name = "dram-pll";
};

&reg_aldo3 {
	regulator-always-on;
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
	regulator-name = "avcc";
};

&reg_dcdc1 {
	/* schematics says 3.1V but FEX file says 3.3V */
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-3v3";
};

&reg_dcdc2 {
	regulator-always-on;
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1100000>;
	regulator-name = "vdd-cpua";
};

&reg_dcdc3 {
	regulator-always-on;
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1100000>;
	regulator-name = "vdd-cpub";
};

&reg_dcdc4 {
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1100000>;
	regulator-name = "vdd-gpu";
};

&reg_dcdc5 {
	regulator-always-on;
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-name = "vcc-dram";
};

&reg_dcdc6 {
	regulator-always-on;
	regulator-min-microvolt = <900000>;
	regulator-max-microvolt = <900000>;
	regulator-name = "vdd-sys";
};

&reg_dldo1 {
	/*
	 * This powers both the WiFi/BT module's main power, I/O supply,
	 * and external pull-ups on all the data lines. It should be set
	 * to the same voltage as the I/O supply (DCDC1 in this case) to
	 * avoid any leakage or mismatch.
	 */
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-wifi";
};

&reg_dldo3 {
	regulator-always-on;
	regulator-min-microvolt = <2500000>;
	regulator-max-microvolt = <2500000>;
	regulator-name = "vcc-pd";
};

&reg_drivevbus {
	regulator-name = "usb0-vbus";
	status = "okay";
};

&reg_fldo1 {
	regulator-min-microvolt = <1080000>;
	regulator-max-microvolt = <1320000>;
	regulator-name = "vdd12-hsic";
};

&reg_fldo2 {
	/*
	 * Despite the embedded CPUs core not being used in any way,
	 * this must remain on or the system will hang.
	 */
	regulator-always-on;
	regulator-min-microvolt = <700000>;
	regulator-max-microvolt = <1100000>;
	regulator-name = "vdd-cpus";
};

&reg_rtc_ldo {
	regulator-name = "vcc-rtc";
};

&reg_sw {
	/*
	 * The PHY requires 20ms after all voltages
	 * are applied until core logic is ready and
	 * 30ms after the reset pin is de-asserted.
	 * Set a 100ms delay to account for PMIC
	 * ramp time and board traces.
	 */
	regulator-enable-ramp-delay = <100000>;
	regulator-name = "vcc-ephy";
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pb_pins>;
	status = "okay";
};

&usbphy {
	usb1_vbus-supply = <&reg_usb1_vbus>;
	status = "okay";
};
Commit	Line	Data
359b5a1e CYT	1	/*
	2	* Copyright 2017 Chen-Yu Tsai
	3	*
	4	* Chen-Yu Tsai <wens@csie.org>
	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
	11	* a) This file is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This file is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* Or, alternatively,
	22	*
	23	* b) Permission is hereby granted, free of charge, to any person
	24	* obtaining a copy of this software and associated documentation
	25	* files (the "Software"), to deal in the Software without
	26	* restriction, including without limitation the rights to use,
	27	* copy, modify, merge, publish, distribute, sublicense, and/or
	28	* sell copies of the Software, and to permit persons to whom the
	29	* Software is furnished to do so, subject to the following
	30	* conditions:
	31	*
	32	* The above copyright notice and this permission notice shall be
	33	* included in all copies or substantial portions of the Software.
	34	*
	35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	37	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	38	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	39	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	41	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	42	* OTHER DEALINGS IN THE SOFTWARE.
	43	*/
	44
	45	/dts-v1/;
	46	#include "sun8i-a83t.dtsi"
359b5a1e CYT	47
	48	#include <dt-bindings/gpio/gpio.h>
	49
	50	/ {
	51	model = "Banana Pi BPI-M3";
	52	compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
	53
	54	aliases {
03935994	55	ethernet0 = &emac;
359b5a1e CYT	56	serial0 = &uart0;
	57	};
	58
	59	chosen {
	60	stdout-path = "serial0:115200n8";
	61	};
d7c5f686	62
9ae65654 CYT	63	leds {
	64	compatible = "gpio-leds";
	65
	66	blue {
	67	label = "bananapi-m3:blue:usr";
	68	gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>;
	69	};
	70
	71	green {
	72	label = "bananapi-m3:green:usr";
	73	gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>;
	74	};
	75	};
	76
d7c5f686 CYT	77	reg_usb1_vbus: reg-usb1-vbus {
	78	compatible = "regulator-fixed";
	79	regulator-name = "usb1-vbus";
	80	regulator-min-microvolt = <5000000>;
	81	regulator-max-microvolt = <5000000>;
	82	regulator-boot-on;
	83	enable-active-high;
	84	gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
	85	};
337cce7e CYT	86
	87	wifi_pwrseq: wifi_pwrseq {
	88	compatible = "mmc-pwrseq-simple";
	89	clocks = <&ac100_rtc 1>;
	90	clock-names = "ext_clock";
	91	/* The WiFi low power clock must be 32768 Hz */
	92	assigned-clocks = <&ac100_rtc 1>;
	93	assigned-clock-rates = <32768>;
	94	/* enables internal regulator and de-asserts reset */
	95	reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
	96	};
359b5a1e CYT	97	};
	98
	99	&ehci0 {
	100	/* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
	101	status = "okay";
	102
	103	/* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */
	104	};
	105
03935994 CYT	106	&emac {
	107	pinctrl-names = "default";
	108	pinctrl-0 = <&emac_rgmii_pins>;
	109	phy-supply = <&reg_sw>;
	110	phy-handle = <&rgmii_phy>;
	111	phy-mode = "rgmii";
	112	allwinner,rx-delay-ps = <700>;
	113	allwinner,tx-delay-ps = <700>;
	114	status = "okay";
	115	};
	116
	117	&mdio {
	118	rgmii_phy: ethernet-phy@1 {
	119	compatible = "ethernet-phy-ieee802.3-c22";
	120	reg = <1>;
	121	};
	122	};
	123
359b5a1e CYT	124	&mmc0 {
	125	pinctrl-names = "default";
	126	pinctrl-0 = <&mmc0_pins>;
d7c5f686	127	vmmc-supply = <&reg_dcdc1>;
359b5a1e CYT	128	bus-width = <4>;
	129	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
	130	cd-inverted;
	131	status = "okay";
	132	};
	133
337cce7e CYT	134	&mmc1 {
	135	vmmc-supply = <&reg_dldo1>;
	136	vqmmc-supply = <&reg_dldo1>;
	137	mmc-pwrseq = <&wifi_pwrseq>;
	138	bus-width = <4>;
	139	non-removable;
	140	status = "okay";
	141
	142	brcmf: wifi@1 {
	143	reg = <1>;
	144	compatible = "brcm,bcm4329-fmac";
	145	interrupt-parent = <&r_pio>;
	146	interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>;
	147	interrupt-names = "host-wake";
	148	};
	149	};
	150
359b5a1e CYT	151	&mmc2 {
	152	pinctrl-names = "default";
	153	pinctrl-0 = <&mmc2_8bit_emmc_pins>;
d7c5f686 CYT	154	vmmc-supply = <&reg_dcdc1>;
d7c5f686 CYT	155	vqmmc-supply = <&reg_dcdc1>;
359b5a1e CYT	156	bus-width = <8>;
	157	non-removable;
	158	cap-mmc-hw-reset;
	159	status = "okay";
	160	};
	161
	162	&r_rsb {
	163	status = "okay";
	164
	165	axp81x: pmic@3a3 {
	166	compatible = "x-powers,axp813";
	167	reg = <0x3a3>;
	168	interrupt-parent = <&r_intc>;
	169	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
d7c5f686 CYT	170	eldoin-supply = <&reg_dcdc1>;
	171	fldoin-supply = <&reg_dcdc5>;
	172	swin-supply = <&reg_dcdc1>;
	173	x-powers,drive-vbus-en;
359b5a1e CYT	174	};
	175
	176	ac100: codec@e89 {
	177	compatible = "x-powers,ac100";
	178	reg = <0xe89>;
	179
	180	ac100_codec: codec {
	181	compatible = "x-powers,ac100-codec";
	182	interrupt-parent = <&r_pio>;
	183	interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
	184	#clock-cells = <0>;
	185	clock-output-names = "4M_adda";
	186	};
	187
	188	ac100_rtc: rtc {
	189	compatible = "x-powers,ac100-rtc";
	190	interrupt-parent = <&r_intc>;
	191	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	192	clocks = <&ac100_codec>;
	193	#clock-cells = <1>;
	194	clock-output-names = "cko1_rtc",
	195	"cko2_rtc",
	196	"cko3_rtc";
	197	};
	198	};
	199	};
	200
d7c5f686 CYT	201	#include "axp81x.dtsi"
	202
	203	&reg_aldo1 {
	204	regulator-always-on;
	205	regulator-min-microvolt = <1800000>;
	206	regulator-max-microvolt = <1800000>;
	207	regulator-name = "vcc-1v8";
	208	};
	209
	210	&reg_aldo2 {
	211	regulator-always-on;
	212	regulator-min-microvolt = <1800000>;
	213	regulator-max-microvolt = <1800000>;
	214	regulator-name = "dram-pll";
	215	};
	216
	217	&reg_aldo3 {
	218	regulator-always-on;
	219	regulator-min-microvolt = <3000000>;
	220	regulator-max-microvolt = <3000000>;
	221	regulator-name = "avcc";
	222	};
	223
	224	&reg_dcdc1 {
	225	/* schematics says 3.1V but FEX file says 3.3V */
	226	regulator-always-on;
	227	regulator-min-microvolt = <3300000>;
	228	regulator-max-microvolt = <3300000>;
	229	regulator-name = "vcc-3v3";
	230	};
	231
	232	&reg_dcdc2 {
	233	regulator-always-on;
	234	regulator-min-microvolt = <700000>;
	235	regulator-max-microvolt = <1100000>;
	236	regulator-name = "vdd-cpua";
	237	};
	238
	239	&reg_dcdc3 {
	240	regulator-always-on;
	241	regulator-min-microvolt = <700000>;
	242	regulator-max-microvolt = <1100000>;
	243	regulator-name = "vdd-cpub";
	244	};
	245
	246	&reg_dcdc4 {
	247	regulator-min-microvolt = <700000>;
	248	regulator-max-microvolt = <1100000>;
	249	regulator-name = "vdd-gpu";
	250	};
	251
	252	&reg_dcdc5 {
	253	regulator-always-on;
	254	regulator-min-microvolt = <1200000>;
	255	regulator-max-microvolt = <1200000>;
	256	regulator-name = "vcc-dram";
	257	};
	258
	259	&reg_dcdc6 {
	260	regulator-always-on;
	261	regulator-min-microvolt = <900000>;
	262	regulator-max-microvolt = <900000>;
	263	regulator-name = "vdd-sys";
	264	};
265
266	&reg_dldo1 {
267	/*
268	* This powers both the WiFi/BT module's main power, I/O supply,
269	* and external pull-ups on all the data lines. It should be set
270	* to the same voltage as the I/O supply (DCDC1 in this case) to
271	* avoid any leakage or mismatch.
272	*/
273	regulator-min-microvolt = <3300000>;
274	regulator-max-microvolt = <3300000>;
275	regulator-name = "vcc-wifi";
276	};
277
278	&reg_dldo3 {
279	regulator-always-on;
280	regulator-min-microvolt = <2500000>;
281	regulator-max-microvolt = <2500000>;
282	regulator-name = "vcc-pd";
283	};
284
285	&reg_drivevbus {
286	regulator-name = "usb0-vbus";
359b5a1e CYT	287	status = "okay";
	288	};
	289
d7c5f686 CYT	290	&reg_fldo1 {
	291	regulator-min-microvolt = <1080000>;
	292	regulator-max-microvolt = <1320000>;
	293	regulator-name = "vdd12-hsic";
	294	};
	295
	296	&reg_fldo2 {
	297	/*
	298	* Despite the embedded CPUs core not being used in any way,
	299	* this must remain on or the system will hang.
	300	*/
	301	regulator-always-on;
	302	regulator-min-microvolt = <700000>;
	303	regulator-max-microvolt = <1100000>;
	304	regulator-name = "vdd-cpus";
	305	};
	306
	307	&reg_rtc_ldo {
	308	regulator-name = "vcc-rtc";
359b5a1e CYT	309	};
359b5a1e CYT	310
d7c5f686 CYT	311	&reg_sw {
	312	/*
	313	* The PHY requires 20ms after all voltages
	314	* are applied until core logic is ready and
	315	* 30ms after the reset pin is de-asserted.
	316	* Set a 100ms delay to account for PMIC
	317	* ramp time and board traces.
	318	*/
	319	regulator-enable-ramp-delay = <100000>;
	320	regulator-name = "vcc-ephy";
359b5a1e CYT	321	};
	322
	323	&uart0 {
	324	pinctrl-names = "default";
	325	pinctrl-0 = <&uart0_pb_pins>;
	326	status = "okay";
	327	};
	328
	329	&usbphy {
	330	usb1_vbus-supply = <&reg_usb1_vbus>;
	331	status = "okay";
	332	};