[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / sun8i-a83t.dtsi

/*
 * Copyright 2015 Vishnu Patekar
 *
 * Vishnu Patekar <vishnupatekar0510@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/sun8i-a83t-ccu.h>
#include <dt-bindings/clock/sun8i-r-ccu.h>
#include <dt-bindings/reset/sun8i-a83t-ccu.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
	};

	chosen {
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};

		cpu@2 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <3>;
		};

		cpu@100 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x100>;
		};

		cpu@101 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x101>;
		};

		cpu@102 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x102>;
		};

		cpu@103 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x103>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* TODO: PRCM block has a mux for this. */
		osc24M: osc24M_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
			clock-accuracy = <50000>;
			clock-output-names = "osc24M";
		};

		/*
		 * This is called "internal OSC" in some places.
		 * It is an internal RC-based oscillator.
		 * TODO: Its controls are in the PRCM block.
		 */
		osc16M: osc16M_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <16000000>;
			clock-output-names = "osc16M";
		};

		osc16Md512: osc16Md512_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <512>;
			clock-mult = <1>;
			clocks = <&osc16M>;
			clock-output-names = "osc16M-d512";
		};
	};

	memory {
		reg = <0x40000000 0x80000000>;
		device_type = "memory";
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		syscon: syscon@1c00000 {
			compatible = "allwinner,sun8i-a83t-system-controller",
				"syscon";
			reg = <0x01c00000 0x1000>;
		};

		dma: dma-controller@1c02000 {
			compatible = "allwinner,sun8i-a83t-dma";
			reg = <0x01c02000 0x1000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_DMA>;
			resets = <&ccu RST_BUS_DMA>;
			#dma-cells = <1>;
		};

		ccu: clock@1c20000 {
			compatible = "allwinner,sun8i-a83t-ccu";
			reg = <0x01c20000 0x400>;
			clocks = <&osc24M>, <&osc16Md512>;
			clock-names = "hosc", "losc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		pio: pinctrl@1c20800 {
			compatible = "allwinner,sun8i-a83t-pinctrl";
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x01c20800 0x400>;
			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
			clock-names = "apb", "hosc", "losc";
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <3>;
			#gpio-cells = <3>;

			mmc0_pins: mmc0-pins {
				pins = "PF0", "PF1", "PF2",
				       "PF3", "PF4", "PF5";
				function = "mmc0";
				drive-strength = <30>;
				bias-pull-up;
			};

			spdif_tx_pin: spdif-tx-pin {
				pins = "PE18";
				function = "spdif";
			};

			uart0_pb_pins: uart0-pb-pins {
				pins = "PB9", "PB10";
				function = "uart0";
			};

			uart0_pf_pins: uart0-pf-pins {
				pins = "PF2", "PF4";
				function = "uart0";
			};
		};

		timer@1c20c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x01c20c00 0xa0>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc24M>;
		};

		watchdog@1c20ca0 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x01c20ca0 0x20>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc24M>;
		};

		spdif: spdif@1c21000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sun8i-a83t-spdif",
				     "allwinner,sun8i-h3-spdif";
			reg = <0x01c21000 0x400>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
			resets = <&ccu RST_BUS_SPDIF>;
			clock-names = "apb", "spdif";
			dmas = <&dma 2>;
			dma-names = "tx";
			pinctrl-names = "default";
			pinctrl-0 = <&spdif_tx_pin>;
			status = "disabled";
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART0>;
			resets = <&ccu RST_BUS_UART0>;
			status = "disabled";
		};

		gic: interrupt-controller@1c81000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x2000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		r_ccu: clock@1f01400 {
			compatible = "allwinner,sun8i-a83t-r-ccu";
			reg = <0x01f01400 0x400>;
			clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
				 <&ccu 6>;
			clock-names = "hosc", "losc", "iosc", "pll-periph";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		r_pio: pinctrl@1f02c00 {
			compatible = "allwinner,sun8i-a83t-r-pinctrl";
			reg = <0x01f02c00 0x400>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
				 <&osc16Md512>;
			clock-names = "apb", "hosc", "losc";
			gpio-controller;
			#gpio-cells = <3>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};
	};
};
Commit	Line	Data
7c929aa6 VP	1	/*
	2	* Copyright 2015 Vishnu Patekar
	3	*
	4	* Vishnu Patekar <vishnupatekar0510@gmail.com>
	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
	11	* a) This file is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This file is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* Or, alternatively,
	22	*
	23	* b) Permission is hereby granted, free of charge, to any person
	24	* obtaining a copy of this software and associated documentation
	25	* files (the "Software"), to deal in the Software without
	26	* restriction, including without limitation the rights to use,
	27	* copy, modify, merge, publish, distribute, sublicense, and/or
	28	* sell copies of the Software, and to permit persons to whom the
	29	* Software is furnished to do so, subject to the following
	30	* conditions:
	31	*
	32	* The above copyright notice and this permission notice shall be
	33	* included in all copies or substantial portions of the Software.
	34	*
	35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	37	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	38	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	39	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	41	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	42	* OTHER DEALINGS IN THE SOFTWARE.
7c929aa6 VP	43	*/
7c929aa6 VP	44
7c929aa6 VP	45	#include <dt-bindings/interrupt-controller/arm-gic.h>
7c929aa6 VP	46
c50f9fb6	47	#include <dt-bindings/clock/sun8i-a83t-ccu.h>
694ca10c	48	#include <dt-bindings/clock/sun8i-r-ccu.h>
c50f9fb6	49	#include <dt-bindings/reset/sun8i-a83t-ccu.h>
694ca10c	50
7c929aa6 VP	51	/ {
7c929aa6 VP	52	interrupt-parent = <&gic>;
802139d0 CYT	53	#address-cells = <1>;
	54	#size-cells = <1>;
	55
	56	aliases {
	57	};
	58
	59	chosen {
	60	};
7c929aa6 VP	61
	62	cpus {
	63	#address-cells = <1>;
	64	#size-cells = <0>;
	65
	66	cpu@0 {
	67	compatible = "arm,cortex-a7";
	68	device_type = "cpu";
	69	reg = <0>;
	70	};
	71
	72	cpu@1 {
	73	compatible = "arm,cortex-a7";
	74	device_type = "cpu";
	75	reg = <1>;
	76	};
	77
	78	cpu@2 {
	79	compatible = "arm,cortex-a7";
	80	device_type = "cpu";
	81	reg = <2>;
	82	};
	83
	84	cpu@3 {
	85	compatible = "arm,cortex-a7";
	86	device_type = "cpu";
	87	reg = <3>;
	88	};
	89
	90	cpu@100 {
	91	compatible = "arm,cortex-a7";
	92	device_type = "cpu";
	93	reg = <0x100>;
	94	};
	95
	96	cpu@101 {
	97	compatible = "arm,cortex-a7";
	98	device_type = "cpu";
	99	reg = <0x101>;
	100	};
	101
	102	cpu@102 {
	103	compatible = "arm,cortex-a7";
	104	device_type = "cpu";
	105	reg = <0x102>;
	106	};
	107
	108	cpu@103 {
	109	compatible = "arm,cortex-a7";
	110	device_type = "cpu";
	111	reg = <0x103>;
	112	};
	113	};
	114
	115	timer {
	116	compatible = "arm,armv7-timer";
	117	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
	118	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
	119	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
	120	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>;
	121	};
	122
	123	clocks {
	124	#address-cells = <1>;
125	#size-cells = <1>;
126	ranges;
127
c5dee34e	128	/* TODO: PRCM block has a mux for this. */
7c929aa6 VP	129	osc24M: osc24M_clk {
	130	#clock-cells = <0>;
	131	compatible = "fixed-clock";
	132	clock-frequency = <24000000>;
c31d4884	133	clock-accuracy = <50000>;
7c929aa6 VP	134	clock-output-names = "osc24M";
	135	};
	136
c5dee34e CYT	137	/*
	138	* This is called "internal OSC" in some places.
	139	* It is an internal RC-based oscillator.
	140	* TODO: Its controls are in the PRCM block.
	141	*/
	142	osc16M: osc16M_clk {
7c929aa6 VP	143	#clock-cells = <0>;
7c929aa6 VP	144	compatible = "fixed-clock";
c5dee34e CYT	145	clock-frequency = <16000000>;
	146	clock-output-names = "osc16M";
	147	};
	148
	149	osc16Md512: osc16Md512_clk {
	150	#clock-cells = <0>;
	151	compatible = "fixed-factor-clock";
	152	clock-div = <512>;
	153	clock-mult = <1>;
	154	clocks = <&osc16M>;
	155	clock-output-names = "osc16M-d512";
7c929aa6 VP	156	};
	157	};
	158
802139d0 CYT	159	memory {
	160	reg = <0x40000000 0x80000000>;
	161	device_type = "memory";
	162	};
	163
7c929aa6 VP	164	soc {
	165	compatible = "simple-bus";
	166	#address-cells = <1>;
	167	#size-cells = <1>;
	168	ranges;
	169
0e9d528f CL	170	syscon: syscon@1c00000 {
	171	compatible = "allwinner,sun8i-a83t-system-controller",
	172	"syscon";
	173	reg = <0x01c00000 0x1000>;
	174	};
	175
749b7a97 CYT	176	dma: dma-controller@1c02000 {
	177	compatible = "allwinner,sun8i-a83t-dma";
	178	reg = <0x01c02000 0x1000>;
	179	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
c50f9fb6 CYT	180	clocks = <&ccu CLK_BUS_DMA>;
c50f9fb6 CYT	181	resets = <&ccu RST_BUS_DMA>;
749b7a97 CYT	182	#dma-cells = <1>;
	183	};
	184
1a8c176b CYT	185	ccu: clock@1c20000 {
	186	compatible = "allwinner,sun8i-a83t-ccu";
	187	reg = <0x01c20000 0x400>;
	188	clocks = <&osc24M>, <&osc16Md512>;
	189	clock-names = "hosc", "losc";
	190	#clock-cells = <1>;
	191	#reset-cells = <1>;
	192	};
	193
e407e25d	194	pio: pinctrl@1c20800 {
7c929aa6 VP	195	compatible = "allwinner,sun8i-a83t-pinctrl";
	196	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	197	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	198	<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	199	reg = <0x01c20800 0x400>;
c50f9fb6	200	clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
1a8c176b	201	clock-names = "apb", "hosc", "losc";
7c929aa6 VP	202	gpio-controller;
	203	interrupt-controller;
	204	#interrupt-cells = <3>;
	205	#gpio-cells = <3>;
	206
62628be2	207	mmc0_pins: mmc0-pins {
1edcd36f MR	208	pins = "PF0", "PF1", "PF2",
	209	"PF3", "PF4", "PF5";
	210	function = "mmc0";
	211	drive-strength = <30>;
80ee72e7	212	bias-pull-up;
7c929aa6 VP	213	};
7c929aa6 VP	214
9ecf1230 CYT	215	spdif_tx_pin: spdif-tx-pin {
	216	pins = "PE18";
	217	function = "spdif";
	218	};
	219
62628be2	220	uart0_pb_pins: uart0-pb-pins {
e53bfb02	221	pins = "PB9", "PB10";
1edcd36f	222	function = "uart0";
7c929aa6 VP	223	};
7c929aa6 VP	224
62628be2	225	uart0_pf_pins: uart0-pf-pins {
e53bfb02	226	pins = "PF2", "PF4";
1edcd36f	227	function = "uart0";
7c929aa6 VP	228	};
	229	};
	230
e407e25d	231	timer@1c20c00 {
85c19acf VP	232	compatible = "allwinner,sun4i-a10-timer";
	233	reg = <0x01c20c00 0xa0>;
	234	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	235	<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	236	clocks = <&osc24M>;
	237	};
	238
e407e25d	239	watchdog@1c20ca0 {
b1dc902f CYT	240	compatible = "allwinner,sun6i-a31-wdt";
	241	reg = <0x01c20ca0 0x20>;
	242	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	243	clocks = <&osc24M>;
	244	};
	245
9ecf1230 CYT	246	spdif: spdif@1c21000 {
	247	#sound-dai-cells = <0>;
	248	compatible = "allwinner,sun8i-a83t-spdif",
	249	"allwinner,sun8i-h3-spdif";
	250	reg = <0x01c21000 0x400>;
	251	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
c50f9fb6 CYT	252	clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
c50f9fb6 CYT	253	resets = <&ccu RST_BUS_SPDIF>;
9ecf1230 CYT	254	clock-names = "apb", "spdif";
	255	dmas = <&dma 2>;
	256	dma-names = "tx";
	257	pinctrl-names = "default";
	258	pinctrl-0 = <&spdif_tx_pin>;
	259	status = "disabled";
	260	};
	261
7c929aa6 VP	262	uart0: serial@01c28000 {
	263	compatible = "snps,dw-apb-uart";
	264	reg = <0x01c28000 0x400>;
	265	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	266	reg-shift = <2>;
	267	reg-io-width = <4>;
c50f9fb6 CYT	268	clocks = <&ccu CLK_BUS_UART0>;
c50f9fb6 CYT	269	resets = <&ccu RST_BUS_UART0>;
7c929aa6 VP	270	status = "disabled";
	271	};
	272
e407e25d	273	gic: interrupt-controller@1c81000 {
7c929aa6 VP	274	compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
7c929aa6 VP	275	reg = <0x01c81000 0x1000>,
387720c9	276	<0x01c82000 0x2000>,
7c929aa6 VP	277	<0x01c84000 0x2000>,
	278	<0x01c86000 0x2000>;
	279	interrupt-controller;
	280	#interrupt-cells = <3>;
	281	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_HIGH)>;
	282	};
c80aec5e CYT	283
	284	r_ccu: clock@1f01400 {
	285	compatible = "allwinner,sun8i-a83t-r-ccu";
	286	reg = <0x01f01400 0x400>;
	287	clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
	288	<&ccu 6>;
	289	clock-names = "hosc", "losc", "iosc", "pll-periph";
	290	#clock-cells = <1>;
	291	#reset-cells = <1>;
	292	};
694ca10c CYT	293
	294	r_pio: pinctrl@1f02c00 {
	295	compatible = "allwinner,sun8i-a83t-r-pinctrl";
	296	reg = <0x01f02c00 0x400>;
	297	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	298	clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
	299	<&osc16Md512>;
	300	clock-names = "apb", "hosc", "losc";
	301	gpio-controller;
	302	#gpio-cells = <3>;
	303	interrupt-controller;
	304	#interrupt-cells = <3>;
	305	};
7c929aa6 VP	306	};
7c929aa6 VP	307	};