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318d93bc JK |
1 | /* |
2 | * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> | |
3 | * | |
4 | * This file is dual-licensed: you can use it either under the terms | |
5 | * of the GPL or the X11 license, at your option. Note that this dual | |
6 | * licensing only applies to this file, and not this project as a | |
7 | * whole. | |
8 | * | |
9 | * a) This file is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of the | |
12 | * License, or (at your option) any later version. | |
13 | * | |
14 | * This file is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * Or, alternatively, | |
20 | * | |
21 | * b) Permission is hereby granted, free of charge, to any person | |
22 | * obtaining a copy of this software and associated documentation | |
23 | * files (the "Software"), to deal in the Software without | |
24 | * restriction, including without limitation the rights to use, | |
25 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
26 | * sell copies of the Software, and to permit persons to whom the | |
27 | * Software is furnished to do so, subject to the following | |
28 | * conditions: | |
29 | * | |
30 | * The above copyright notice and this permission notice shall be | |
31 | * included in all copies or substantial portions of the Software. | |
32 | * | |
33 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
34 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
35 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
36 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
37 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
38 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
39 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
40 | * OTHER DEALINGS IN THE SOFTWARE. | |
41 | */ | |
42 | ||
43 | #include "skeleton.dtsi" | |
44 | ||
45 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
46 | #include <dt-bindings/pinctrl/sun4i-a10.h> | |
47 | ||
48 | / { | |
49 | interrupt-parent = <&gic>; | |
50 | ||
51 | cpus { | |
52 | #address-cells = <1>; | |
53 | #size-cells = <0>; | |
54 | ||
55 | cpu@0 { | |
56 | compatible = "arm,cortex-a7"; | |
57 | device_type = "cpu"; | |
58 | reg = <0>; | |
59 | }; | |
60 | ||
61 | cpu@1 { | |
62 | compatible = "arm,cortex-a7"; | |
63 | device_type = "cpu"; | |
64 | reg = <1>; | |
65 | }; | |
66 | ||
67 | cpu@2 { | |
68 | compatible = "arm,cortex-a7"; | |
69 | device_type = "cpu"; | |
70 | reg = <2>; | |
71 | }; | |
72 | ||
73 | cpu@3 { | |
74 | compatible = "arm,cortex-a7"; | |
75 | device_type = "cpu"; | |
76 | reg = <3>; | |
77 | }; | |
78 | }; | |
79 | ||
80 | timer { | |
81 | compatible = "arm,armv7-timer"; | |
82 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
83 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
84 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
85 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
86 | }; | |
87 | ||
88 | clocks { | |
89 | #address-cells = <1>; | |
90 | #size-cells = <1>; | |
91 | ranges; | |
92 | ||
93 | osc24M: osc24M_clk { | |
94 | #clock-cells = <0>; | |
95 | compatible = "fixed-clock"; | |
96 | clock-frequency = <24000000>; | |
97 | clock-output-names = "osc24M"; | |
98 | }; | |
99 | ||
100 | osc32k: osc32k_clk { | |
101 | #clock-cells = <0>; | |
102 | compatible = "fixed-clock"; | |
103 | clock-frequency = <32768>; | |
104 | clock-output-names = "osc32k"; | |
105 | }; | |
106 | ||
107 | pll1: clk@01c20000 { | |
108 | #clock-cells = <0>; | |
109 | compatible = "allwinner,sun8i-a23-pll1-clk"; | |
110 | reg = <0x01c20000 0x4>; | |
111 | clocks = <&osc24M>; | |
112 | clock-output-names = "pll1"; | |
113 | }; | |
114 | ||
115 | /* dummy clock until actually implemented */ | |
116 | pll5: pll5_clk { | |
117 | #clock-cells = <0>; | |
118 | compatible = "fixed-clock"; | |
119 | clock-frequency = <0>; | |
120 | clock-output-names = "pll5"; | |
121 | }; | |
122 | ||
123 | pll6: clk@01c20028 { | |
124 | #clock-cells = <1>; | |
125 | compatible = "allwinner,sun6i-a31-pll6-clk"; | |
126 | reg = <0x01c20028 0x4>; | |
127 | clocks = <&osc24M>; | |
128 | clock-output-names = "pll6", "pll6x2"; | |
129 | }; | |
130 | ||
131 | pll6d2: pll6d2_clk { | |
132 | #clock-cells = <0>; | |
133 | compatible = "fixed-factor-clock"; | |
134 | clock-div = <2>; | |
135 | clock-mult = <1>; | |
136 | clocks = <&pll6 0>; | |
137 | clock-output-names = "pll6d2"; | |
138 | }; | |
139 | ||
140 | /* dummy clock until pll6 can be reused */ | |
141 | pll8: pll8_clk { | |
142 | #clock-cells = <0>; | |
143 | compatible = "fixed-clock"; | |
144 | clock-frequency = <1>; | |
145 | clock-output-names = "pll8"; | |
146 | }; | |
147 | ||
148 | cpu: cpu_clk@01c20050 { | |
149 | #clock-cells = <0>; | |
150 | compatible = "allwinner,sun4i-a10-cpu-clk"; | |
151 | reg = <0x01c20050 0x4>; | |
152 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; | |
153 | clock-output-names = "cpu"; | |
154 | }; | |
155 | ||
156 | axi: axi_clk@01c20050 { | |
157 | #clock-cells = <0>; | |
158 | compatible = "allwinner,sun4i-a10-axi-clk"; | |
159 | reg = <0x01c20050 0x4>; | |
160 | clocks = <&cpu>; | |
161 | clock-output-names = "axi"; | |
162 | }; | |
163 | ||
164 | ahb1: ahb1_clk@01c20054 { | |
165 | #clock-cells = <0>; | |
166 | compatible = "allwinner,sun6i-a31-ahb1-clk"; | |
167 | reg = <0x01c20054 0x4>; | |
168 | clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; | |
169 | clock-output-names = "ahb1"; | |
170 | }; | |
171 | ||
172 | ahb2: ahb2_clk@01c2005c { | |
173 | #clock-cells = <0>; | |
174 | compatible = "allwinner,sun8i-h3-ahb2-clk"; | |
175 | reg = <0x01c2005c 0x4>; | |
176 | clocks = <&ahb1>, <&pll6d2>; | |
177 | clock-output-names = "ahb2"; | |
178 | }; | |
179 | ||
180 | apb1: apb1_clk@01c20054 { | |
181 | #clock-cells = <0>; | |
182 | compatible = "allwinner,sun4i-a10-apb0-clk"; | |
183 | reg = <0x01c20054 0x4>; | |
184 | clocks = <&ahb1>; | |
185 | clock-output-names = "apb1"; | |
186 | }; | |
187 | ||
188 | apb2: apb2_clk@01c20058 { | |
189 | #clock-cells = <0>; | |
190 | compatible = "allwinner,sun4i-a10-apb1-clk"; | |
191 | reg = <0x01c20058 0x4>; | |
192 | clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; | |
193 | clock-output-names = "apb2"; | |
194 | }; | |
195 | ||
196 | bus_gates: clk@01c20060 { | |
197 | #clock-cells = <1>; | |
198 | compatible = "allwinner,sun8i-h3-bus-gates-clk"; | |
199 | reg = <0x01c20060 0x14>; | |
200 | clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; | |
201 | clock-names = "ahb1", "ahb2", "apb1", "apb2"; | |
202 | clock-indices = <5>, <6>, <8>, | |
203 | <9>, <10>, <13>, | |
204 | <14>, <17>, <18>, | |
205 | <19>, <20>, | |
206 | <21>, <23>, | |
207 | <24>, <25>, | |
208 | <26>, <27>, | |
209 | <28>, <29>, | |
210 | <30>, <31>, <32>, | |
211 | <35>, <36>, <37>, | |
212 | <40>, <41>, <43>, | |
213 | <44>, <52>, <53>, | |
214 | <54>, <64>, | |
215 | <65>, <69>, <72>, | |
216 | <76>, <77>, <78>, | |
217 | <96>, <97>, <98>, | |
218 | <112>, <113>, | |
219 | <114>, <115>, | |
220 | <116>, <128>, <135>; | |
221 | clock-output-names = "bus_ce", "bus_dma", "bus_mmc0", | |
222 | "bus_mmc1", "bus_mmc2", "bus_nand", | |
223 | "bus_sdram", "bus_gmac", "bus_ts", | |
224 | "bus_hstimer", "bus_spi0", | |
225 | "bus_spi1", "bus_otg", | |
226 | "bus_otg_ehci0", "bus_ehci1", | |
227 | "bus_ehci2", "bus_ehci3", | |
228 | "bus_otg_ohci0", "bus_ohci1", | |
229 | "bus_ohci2", "bus_ohci3", "bus_ve", | |
230 | "bus_lcd0", "bus_lcd1", "bus_deint", | |
231 | "bus_csi", "bus_tve", "bus_hdmi", | |
232 | "bus_de", "bus_gpu", "bus_msgbox", | |
233 | "bus_spinlock", "bus_codec", | |
234 | "bus_spdif", "bus_pio", "bus_ths", | |
235 | "bus_i2s0", "bus_i2s1", "bus_i2s2", | |
236 | "bus_i2c0", "bus_i2c1", "bus_i2c2", | |
237 | "bus_uart0", "bus_uart1", | |
238 | "bus_uart2", "bus_uart3", | |
239 | "bus_scr", "bus_ephy", "bus_dbg"; | |
240 | }; | |
241 | ||
242 | mmc0_clk: clk@01c20088 { | |
243 | #clock-cells = <1>; | |
244 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
245 | reg = <0x01c20088 0x4>; | |
246 | clocks = <&osc24M>, <&pll6 0>, <&pll8>; | |
247 | clock-output-names = "mmc0", | |
248 | "mmc0_output", | |
249 | "mmc0_sample"; | |
250 | }; | |
251 | ||
252 | mmc1_clk: clk@01c2008c { | |
253 | #clock-cells = <1>; | |
254 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
255 | reg = <0x01c2008c 0x4>; | |
256 | clocks = <&osc24M>, <&pll6 0>, <&pll8>; | |
257 | clock-output-names = "mmc1", | |
258 | "mmc1_output", | |
259 | "mmc1_sample"; | |
260 | }; | |
261 | ||
262 | mmc2_clk: clk@01c20090 { | |
263 | #clock-cells = <1>; | |
264 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
265 | reg = <0x01c20090 0x4>; | |
266 | clocks = <&osc24M>, <&pll6 0>, <&pll8>; | |
267 | clock-output-names = "mmc2", | |
268 | "mmc2_output", | |
269 | "mmc2_sample"; | |
270 | }; | |
271 | ||
272 | mbus_clk: clk@01c2015c { | |
273 | #clock-cells = <0>; | |
274 | compatible = "allwinner,sun8i-a23-mbus-clk"; | |
275 | reg = <0x01c2015c 0x4>; | |
276 | clocks = <&osc24M>, <&pll6 1>, <&pll5>; | |
277 | clock-output-names = "mbus"; | |
278 | }; | |
09787294 KA |
279 | |
280 | apb0: apb0_clk { | |
281 | compatible = "fixed-factor-clock"; | |
282 | #clock-cells = <0>; | |
283 | clock-div = <1>; | |
284 | clock-mult = <1>; | |
285 | clocks = <&osc24M>; | |
286 | clock-output-names = "apb0"; | |
287 | }; | |
288 | ||
289 | apb0_gates: clk@01f01428 { | |
290 | compatible = "allwinner,sun8i-h3-apb0-gates-clk", | |
291 | "allwinner,sun4i-a10-gates-clk"; | |
292 | reg = <0x01f01428 0x4>; | |
293 | #clock-cells = <1>; | |
294 | clocks = <&apb0>; | |
295 | clock-indices = <0>, <1>; | |
296 | clock-output-names = "apb0_pio", "apb0_ir"; | |
297 | }; | |
318d93bc JK |
298 | }; |
299 | ||
300 | soc { | |
301 | compatible = "simple-bus"; | |
302 | #address-cells = <1>; | |
303 | #size-cells = <1>; | |
304 | ranges; | |
305 | ||
306 | dma: dma-controller@01c02000 { | |
307 | compatible = "allwinner,sun8i-h3-dma"; | |
308 | reg = <0x01c02000 0x1000>; | |
309 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; | |
310 | clocks = <&bus_gates 6>; | |
311 | resets = <&ahb_rst 6>; | |
312 | #dma-cells = <1>; | |
313 | }; | |
314 | ||
315 | mmc0: mmc@01c0f000 { | |
316 | compatible = "allwinner,sun5i-a13-mmc"; | |
317 | reg = <0x01c0f000 0x1000>; | |
318 | clocks = <&bus_gates 8>, | |
319 | <&mmc0_clk 0>, | |
320 | <&mmc0_clk 1>, | |
321 | <&mmc0_clk 2>; | |
322 | clock-names = "ahb", | |
323 | "mmc", | |
324 | "output", | |
325 | "sample"; | |
326 | resets = <&ahb_rst 8>; | |
327 | reset-names = "ahb"; | |
328 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; | |
329 | status = "disabled"; | |
330 | #address-cells = <1>; | |
331 | #size-cells = <0>; | |
332 | }; | |
333 | ||
334 | mmc1: mmc@01c10000 { | |
335 | compatible = "allwinner,sun5i-a13-mmc"; | |
336 | reg = <0x01c10000 0x1000>; | |
337 | clocks = <&bus_gates 9>, | |
338 | <&mmc1_clk 0>, | |
339 | <&mmc1_clk 1>, | |
340 | <&mmc1_clk 2>; | |
341 | clock-names = "ahb", | |
342 | "mmc", | |
343 | "output", | |
344 | "sample"; | |
345 | resets = <&ahb_rst 9>; | |
346 | reset-names = "ahb"; | |
347 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
348 | status = "disabled"; | |
349 | #address-cells = <1>; | |
350 | #size-cells = <0>; | |
351 | }; | |
352 | ||
353 | mmc2: mmc@01c11000 { | |
354 | compatible = "allwinner,sun5i-a13-mmc"; | |
355 | reg = <0x01c11000 0x1000>; | |
356 | clocks = <&bus_gates 10>, | |
357 | <&mmc2_clk 0>, | |
358 | <&mmc2_clk 1>, | |
359 | <&mmc2_clk 2>; | |
360 | clock-names = "ahb", | |
361 | "mmc", | |
362 | "output", | |
363 | "sample"; | |
364 | resets = <&ahb_rst 10>; | |
365 | reset-names = "ahb"; | |
366 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
367 | status = "disabled"; | |
368 | #address-cells = <1>; | |
369 | #size-cells = <0>; | |
370 | }; | |
371 | ||
372 | pio: pinctrl@01c20800 { | |
373 | compatible = "allwinner,sun8i-h3-pinctrl"; | |
374 | reg = <0x01c20800 0x400>; | |
375 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, | |
376 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
377 | clocks = <&bus_gates 69>; | |
378 | gpio-controller; | |
379 | #gpio-cells = <3>; | |
380 | interrupt-controller; | |
5bcaf95c | 381 | #interrupt-cells = <3>; |
318d93bc JK |
382 | |
383 | uart0_pins_a: uart0@0 { | |
384 | allwinner,pins = "PA4", "PA5"; | |
385 | allwinner,function = "uart0"; | |
386 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
387 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
388 | }; | |
389 | ||
390 | mmc0_pins_a: mmc0@0 { | |
391 | allwinner,pins = "PF0", "PF1", "PF2", "PF3", | |
392 | "PF4", "PF5"; | |
393 | allwinner,function = "mmc0"; | |
394 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; | |
395 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
396 | }; | |
397 | ||
398 | mmc0_cd_pin: mmc0_cd_pin@0 { | |
399 | allwinner,pins = "PF6"; | |
400 | allwinner,function = "gpio_in"; | |
401 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
402 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
403 | }; | |
404 | ||
405 | mmc1_pins_a: mmc1@0 { | |
406 | allwinner,pins = "PG0", "PG1", "PG2", "PG3", | |
407 | "PG4", "PG5"; | |
408 | allwinner,function = "mmc1"; | |
409 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; | |
410 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
411 | }; | |
412 | }; | |
413 | ||
414 | ahb_rst: reset@01c202c0 { | |
415 | #reset-cells = <1>; | |
416 | compatible = "allwinner,sun6i-a31-ahb1-reset"; | |
417 | reg = <0x01c202c0 0xc>; | |
418 | }; | |
419 | ||
420 | apb1_rst: reset@01c202d0 { | |
421 | #reset-cells = <1>; | |
422 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
423 | reg = <0x01c202d0 0x4>; | |
424 | }; | |
425 | ||
426 | apb2_rst: reset@01c202d8 { | |
427 | #reset-cells = <1>; | |
428 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
429 | reg = <0x01c202d8 0x4>; | |
430 | }; | |
431 | ||
432 | timer@01c20c00 { | |
433 | compatible = "allwinner,sun4i-a10-timer"; | |
434 | reg = <0x01c20c00 0xa0>; | |
435 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, | |
436 | <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; | |
437 | clocks = <&osc24M>; | |
438 | }; | |
439 | ||
440 | wdt0: watchdog@01c20ca0 { | |
441 | compatible = "allwinner,sun6i-a31-wdt"; | |
442 | reg = <0x01c20ca0 0x20>; | |
443 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
444 | }; | |
445 | ||
446 | uart0: serial@01c28000 { | |
447 | compatible = "snps,dw-apb-uart"; | |
448 | reg = <0x01c28000 0x400>; | |
449 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; | |
450 | reg-shift = <2>; | |
451 | reg-io-width = <4>; | |
452 | clocks = <&bus_gates 112>; | |
453 | resets = <&apb2_rst 16>; | |
454 | dmas = <&dma 6>, <&dma 6>; | |
455 | dma-names = "rx", "tx"; | |
456 | status = "disabled"; | |
457 | }; | |
458 | ||
459 | uart1: serial@01c28400 { | |
460 | compatible = "snps,dw-apb-uart"; | |
461 | reg = <0x01c28400 0x400>; | |
462 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
463 | reg-shift = <2>; | |
464 | reg-io-width = <4>; | |
465 | clocks = <&bus_gates 113>; | |
466 | resets = <&apb2_rst 17>; | |
467 | dmas = <&dma 7>, <&dma 7>; | |
468 | dma-names = "rx", "tx"; | |
469 | status = "disabled"; | |
470 | }; | |
471 | ||
472 | uart2: serial@01c28800 { | |
473 | compatible = "snps,dw-apb-uart"; | |
474 | reg = <0x01c28800 0x400>; | |
475 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; | |
476 | reg-shift = <2>; | |
477 | reg-io-width = <4>; | |
478 | clocks = <&bus_gates 114>; | |
479 | resets = <&apb2_rst 18>; | |
480 | dmas = <&dma 8>, <&dma 8>; | |
481 | dma-names = "rx", "tx"; | |
482 | status = "disabled"; | |
483 | }; | |
484 | ||
485 | uart3: serial@01c28c00 { | |
486 | compatible = "snps,dw-apb-uart"; | |
487 | reg = <0x01c28c00 0x400>; | |
488 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
489 | reg-shift = <2>; | |
490 | reg-io-width = <4>; | |
491 | clocks = <&bus_gates 115>; | |
492 | resets = <&apb2_rst 19>; | |
493 | dmas = <&dma 9>, <&dma 9>; | |
494 | dma-names = "rx", "tx"; | |
495 | status = "disabled"; | |
496 | }; | |
497 | ||
498 | gic: interrupt-controller@01c81000 { | |
499 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
500 | reg = <0x01c81000 0x1000>, | |
501 | <0x01c82000 0x1000>, | |
502 | <0x01c84000 0x2000>, | |
503 | <0x01c86000 0x2000>; | |
504 | interrupt-controller; | |
505 | #interrupt-cells = <3>; | |
506 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
507 | }; | |
508 | ||
509 | rtc: rtc@01f00000 { | |
510 | compatible = "allwinner,sun6i-a31-rtc"; | |
511 | reg = <0x01f00000 0x54>; | |
512 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
513 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
514 | }; | |
09787294 KA |
515 | |
516 | apb0_reset: reset@01f014b0 { | |
517 | reg = <0x01f014b0 0x4>; | |
518 | compatible = "allwinner,sun6i-a31-clock-reset"; | |
519 | #reset-cells = <1>; | |
520 | }; | |
318d93bc JK |
521 | }; |
522 | }; |