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Merge tag 'mips_fixes_5.1_1' into mips-next
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / sunxi-h3-h5.dtsi
CommitLineData
0127216f
AP		 1/*
2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
d8c6f1f0 43#include <dt-bindings/clock/sun8i-de2.h>
0127216f 44#include <dt-bindings/clock/sun8i-h3-ccu.h>
98d87eb5 45#include <dt-bindings/clock/sun8i-r-ccu.h>
0127216f 46#include <dt-bindings/interrupt-controller/arm-gic.h>
d8c6f1f0 47#include <dt-bindings/reset/sun8i-de2.h>
0127216f 48#include <dt-bindings/reset/sun8i-h3-ccu.h>
98d87eb5 49#include <dt-bindings/reset/sun8i-r-ccu.h>
0127216f
AP		 50
51/ {
52 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <1>;
55
9b9931e5
IZ		 56 chosen {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges;
60
61 framebuffer-hdmi {
62 compatible = "allwinner,simple-framebuffer",
63 "simple-framebuffer";
64 allwinner,pipeline = "mixer0-lcd0-hdmi";
65 clocks = <&display_clocks CLK_MIXER0>,
66 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
67 status = "disabled";
68 };
69
70 framebuffer-tve {
71 compatible = "allwinner,simple-framebuffer",
72 "simple-framebuffer";
73 allwinner,pipeline = "mixer1-lcd1-tve";
74 clocks = <&display_clocks CLK_MIXER1>,
75 <&ccu CLK_TVE>;
76 status = "disabled";
77 };
78 };
79
0127216f
AP		 80 clocks {
81 #address-cells = <1>;
82 #size-cells = <1>;
83 ranges;
84
85 osc24M: osc24M_clk {
86 #clock-cells = <0>;
87 compatible = "fixed-clock";
88 clock-frequency = <24000000>;
772c3a45 89 clock-accuracy = <50000>;
0127216f
AP		 90 clock-output-names = "osc24M";
91 };
92
93 osc32k: osc32k_clk {
94 #clock-cells = <0>;
95 compatible = "fixed-clock";
96 clock-frequency = <32768>;
772c3a45 97 clock-accuracy = <50000>;
507c6e89 98 clock-output-names = "ext_osc32k";
0127216f
AP		 99 };
100 };
101
cb34d825
JS		 102 de: display-engine {
103 compatible = "allwinner,sun8i-h3-display-engine";
104 allwinner,pipelines = <&mixer0>;
105 status = "disabled";
106 };
107
0127216f
AP		 108 soc {
109 compatible = "simple-bus";
110 #address-cells = <1>;
111 #size-cells = <1>;
112 ranges;
113
d8c6f1f0
IZ		 114 display_clocks: clock@1000000 {
115 /* compatible is in per SoC .dtsi file */
116 reg = <0x01000000 0x100000>;
117 clocks = <&ccu CLK_DE>,
118 <&ccu CLK_BUS_DE>;
119 clock-names = "mod",
120 "bus";
121 resets = <&ccu RST_BUS_DE>;
122 #clock-cells = <1>;
123 #reset-cells = <1>;
124 };
125
cb34d825
JS		 126 mixer0: mixer@1100000 {
127 compatible = "allwinner,sun8i-h3-de2-mixer-0";
128 reg = <0x01100000 0x100000>;
129 clocks = <&display_clocks CLK_BUS_MIXER0>,
130 <&display_clocks CLK_MIXER0>;
131 clock-names = "bus",
132 "mod";
133 resets = <&display_clocks RST_MIXER0>;
134
135 ports {
136 #address-cells = <1>;
137 #size-cells = <0>;
138
139 mixer0_out: port@1 {
140 reg = <1>;
141
142 mixer0_out_tcon0: endpoint {
143 remote-endpoint = <&tcon0_in_mixer0>;
144 };
145 };
146 };
147 };
148
a3fd57f5 149 dma: dma-controller@1c02000 {
0127216f
AP		 150 compatible = "allwinner,sun8i-h3-dma";
151 reg = <0x01c02000 0x1000>;
152 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
153 clocks = <&ccu CLK_BUS_DMA>;
154 resets = <&ccu RST_BUS_DMA>;
155 #dma-cells = <1>;
156 };
157
cb34d825
JS		 158 tcon0: lcd-controller@1c0c000 {
159 compatible = "allwinner,sun8i-h3-tcon-tv",
160 "allwinner,sun8i-a83t-tcon-tv";
161 reg = <0x01c0c000 0x1000>;
162 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
164 clock-names = "ahb", "tcon-ch1";
165 resets = <&ccu RST_BUS_TCON0>;
166 reset-names = "lcd";
167
168 ports {
169 #address-cells = <1>;
170 #size-cells = <0>;
171
172 tcon0_in: port@0 {
173 reg = <0>;
174
175 tcon0_in_mixer0: endpoint {
176 remote-endpoint = <&mixer0_out_tcon0>;
177 };
178 };
179
180 tcon0_out: port@1 {
181 #address-cells = <1>;
182 #size-cells = <0>;
183 reg = <1>;
184
185 tcon0_out_hdmi: endpoint@1 {
186 reg = <1>;
187 remote-endpoint = <&hdmi_in_tcon0>;
188 };
189 };
190 };
191 };
192
a3fd57f5 193 mmc0: mmc@1c0f000 {
0127216f
AP		 194 /* compatible and clocks are in per SoC .dtsi file */
195 reg = <0x01c0f000 0x1000>;
50caa756 196 pinctrl-names = "default";
8566df71 197 pinctrl-0 = <&mmc0_pins>;
0127216f
AP		 198 resets = <&ccu RST_BUS_MMC0>;
199 reset-names = "ahb";
200 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
201 status = "disabled";
202 #address-cells = <1>;
203 #size-cells = <0>;
204 };
205
a3fd57f5 206 mmc1: mmc@1c10000 {
0127216f
AP		 207 /* compatible and clocks are in per SoC .dtsi file */
208 reg = <0x01c10000 0x1000>;
e607b605 209 pinctrl-names = "default";
8566df71 210 pinctrl-0 = <&mmc1_pins>;
0127216f
AP		 211 resets = <&ccu RST_BUS_MMC1>;
212 reset-names = "ahb";
213 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
214 status = "disabled";
215 #address-cells = <1>;
216 #size-cells = <0>;
217 };
218
a3fd57f5 219 mmc2: mmc@1c11000 {
0127216f
AP		 220 /* compatible and clocks are in per SoC .dtsi file */
221 reg = <0x01c11000 0x1000>;
222 resets = <&ccu RST_BUS_MMC2>;
223 reset-names = "ahb";
224 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
225 status = "disabled";
226 #address-cells = <1>;
227 #size-cells = <0>;
228 };
229
a3fd57f5 230 usb_otg: usb@1c19000 {
da89e1d5
IZ		 231 compatible = "allwinner,sun8i-h3-musb";
232 reg = <0x01c19000 0x400>;
233 clocks = <&ccu CLK_BUS_OTG>;
234 resets = <&ccu RST_BUS_OTG>;
235 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
236 interrupt-names = "mc";
237 phys = <&usbphy 0>;
238 phy-names = "usb";
239 extcon = <&usbphy 0>;
240 status = "disabled";
241 };
242
a3fd57f5 243 usbphy: phy@1c19400 {
0127216f
AP		 244 compatible = "allwinner,sun8i-h3-usb-phy";
245 reg = <0x01c19400 0x2c>,
246 <0x01c1a800 0x4>,
247 <0x01c1b800 0x4>,
248 <0x01c1c800 0x4>,
249 <0x01c1d800 0x4>;
250 reg-names = "phy_ctrl",
251 "pmu0",
252 "pmu1",
253 "pmu2",
254 "pmu3";
255 clocks = <&ccu CLK_USB_PHY0>,
256 <&ccu CLK_USB_PHY1>,
257 <&ccu CLK_USB_PHY2>,
258 <&ccu CLK_USB_PHY3>;
259 clock-names = "usb0_phy",
260 "usb1_phy",
261 "usb2_phy",
262 "usb3_phy";
263 resets = <&ccu RST_USB_PHY0>,
264 <&ccu RST_USB_PHY1>,
265 <&ccu RST_USB_PHY2>,
266 <&ccu RST_USB_PHY3>;
267 reset-names = "usb0_reset",
268 "usb1_reset",
269 "usb2_reset",
270 "usb3_reset";
271 status = "disabled";
272 #phy-cells = <1>;
273 };
274
a3fd57f5 275 ehci0: usb@1c1a000 {
da89e1d5
IZ		 276 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
277 reg = <0x01c1a000 0x100>;
278 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
280 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
281 status = "disabled";
282 };
283
a3fd57f5 284 ohci0: usb@1c1a400 {
da89e1d5
IZ		 285 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
286 reg = <0x01c1a400 0x100>;
287 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
289 <&ccu CLK_USB_OHCI0>;
290 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
291 status = "disabled";
292 };
293
a3fd57f5 294 ehci1: usb@1c1b000 {
0127216f
AP		 295 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
296 reg = <0x01c1b000 0x100>;
297 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
299 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
300 phys = <&usbphy 1>;
301 phy-names = "usb";
302 status = "disabled";
303 };
304
a3fd57f5 305 ohci1: usb@1c1b400 {
0127216f
AP		 306 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
307 reg = <0x01c1b400 0x100>;
308 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
310 <&ccu CLK_USB_OHCI1>;
311 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
312 phys = <&usbphy 1>;
313 phy-names = "usb";
314 status = "disabled";
315 };
316
a3fd57f5 317 ehci2: usb@1c1c000 {
0127216f
AP		 318 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
319 reg = <0x01c1c000 0x100>;
320 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
322 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
323 phys = <&usbphy 2>;
324 phy-names = "usb";
325 status = "disabled";
326 };
327
a3fd57f5 328 ohci2: usb@1c1c400 {
0127216f
AP		 329 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
330 reg = <0x01c1c400 0x100>;
331 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
333 <&ccu CLK_USB_OHCI2>;
334 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
335 phys = <&usbphy 2>;
336 phy-names = "usb";
337 status = "disabled";
338 };
339
a3fd57f5 340 ehci3: usb@1c1d000 {
0127216f
AP		 341 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
342 reg = <0x01c1d000 0x100>;
343 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
345 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
346 phys = <&usbphy 3>;
347 phy-names = "usb";
348 status = "disabled";
349 };
350
a3fd57f5 351 ohci3: usb@1c1d400 {
0127216f
AP		 352 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
353 reg = <0x01c1d400 0x100>;
354 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
356 <&ccu CLK_USB_OHCI3>;
357 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
358 phys = <&usbphy 3>;
359 phy-names = "usb";
360 status = "disabled";
361 };
362
a3fd57f5 363 ccu: clock@1c20000 {
0127216f
AP		 364 /* compatible is in per SoC .dtsi file */
365 reg = <0x01c20000 0x400>;
507c6e89 366 clocks = <&osc24M>, <&rtc 0>;
0127216f
AP		 367 clock-names = "hosc", "losc";
368 #clock-cells = <1>;
369 #reset-cells = <1>;
370 };
371
a3fd57f5 372 pio: pinctrl@1c20800 {
0127216f
AP		 373 /* compatible is in per SoC .dtsi file */
374 reg = <0x01c20800 0x400>;
375 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
507c6e89 377 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
0127216f
AP		 378 clock-names = "apb", "hosc", "losc";
379 gpio-controller;
380 #gpio-cells = <3>;
381 interrupt-controller;
382 #interrupt-cells = <3>;
383
f89120b6
MJ		 384 csi_pins: csi {
385 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
386 "PE6", "PE7", "PE8", "PE9", "PE10",
387 "PE11";
388 function = "csi";
389 };
390
0eba511a
CL		 391 emac_rgmii_pins: emac0 {
392 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
393 "PD5", "PD7", "PD8", "PD9", "PD10",
394 "PD12", "PD13", "PD15", "PD16", "PD17";
395 function = "emac";
396 drive-strength = <40>;
397 };
398
0127216f
AP		 399 i2c0_pins: i2c0 {
400 pins = "PA11", "PA12";
401 function = "i2c0";
402 };
403
404 i2c1_pins: i2c1 {
405 pins = "PA18", "PA19";
406 function = "i2c1";
407 };
408
409 i2c2_pins: i2c2 {
410 pins = "PE12", "PE13";
411 function = "i2c2";
412 };
413
8566df71 414 mmc0_pins: mmc0 {
0127216f
AP		 415 pins = "PF0", "PF1", "PF2", "PF3",
416 "PF4", "PF5";
417 function = "mmc0";
418 drive-strength = <30>;
419 bias-pull-up;
420 };
421
8566df71 422 mmc1_pins: mmc1 {
0127216f
AP		 423 pins = "PG0", "PG1", "PG2", "PG3",
424 "PG4", "PG5";
425 function = "mmc1";
426 drive-strength = <30>;
427 bias-pull-up;
428 };
429
430 mmc2_8bit_pins: mmc2_8bit {
431 pins = "PC5", "PC6", "PC8",
432 "PC9", "PC10", "PC11",
433 "PC12", "PC13", "PC14",
434 "PC15", "PC16";
435 function = "mmc2";
436 drive-strength = <30>;
437 bias-pull-up;
438 };
439
31e79286 440 spdif_tx_pins_a: spdif {
0127216f
AP		 441 pins = "PA17";
442 function = "spdif";
443 };
444
445 spi0_pins: spi0 {
446 pins = "PC0", "PC1", "PC2", "PC3";
447 function = "spi0";
448 };
449
450 spi1_pins: spi1 {
451 pins = "PA15", "PA16", "PA14", "PA13";
452 function = "spi1";
453 };
454
31e79286 455 uart0_pins_a: uart0 {
0127216f
AP		 456 pins = "PA4", "PA5";
457 function = "uart0";
458 };
459
460 uart1_pins: uart1 {
461 pins = "PG6", "PG7";
462 function = "uart1";
463 };
464
465 uart1_rts_cts_pins: uart1_rts_cts {
466 pins = "PG8", "PG9";
467 function = "uart1";
468 };
469
470 uart2_pins: uart2 {
471 pins = "PA0", "PA1";
472 function = "uart2";
473 };
474
475 uart3_pins: uart3 {
476 pins = "PA13", "PA14";
477 function = "uart3";
478 };
5a8e62eb
PR		 479
480 uart3_rts_cts_pins: uart3_rts_cts {
481 pins = "PA15", "PA16";
482 function = "uart3";
483 };
0127216f
AP		 484 };
485
a3fd57f5 486 timer@1c20c00 {
0127216f
AP		 487 compatible = "allwinner,sun4i-a10-timer";
488 reg = <0x01c20c00 0xa0>;
489 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
490 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&osc24M>;
492 };
493
4b236a0f
CL		 494 emac: ethernet@1c30000 {
495 compatible = "allwinner,sun8i-h3-emac";
496 syscon = <&syscon>;
497 reg = <0x01c30000 0x10000>;
498 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
499 interrupt-names = "macirq";
500 resets = <&ccu RST_BUS_EMAC>;
501 reset-names = "stmmaceth";
502 clocks = <&ccu CLK_BUS_EMAC>;
503 clock-names = "stmmaceth";
4b236a0f
CL		 504 status = "disabled";
505
506 mdio: mdio {
507 #address-cells = <1>;
508 #size-cells = <0>;
776245ae
CL		 509 compatible = "snps,dwmac-mdio";
510 };
511
512 mdio-mux {
513 compatible = "allwinner,sun8i-h3-mdio-mux";
514 #address-cells = <1>;
515 #size-cells = <0>;
516
517 mdio-parent-bus = <&mdio>;
518 /* Only one MDIO is usable at the time */
519 internal_mdio: mdio@1 {
520 compatible = "allwinner,sun8i-h3-mdio-internal";
4b236a0f 521 reg = <1>;
776245ae
CL		 522 #address-cells = <1>;
523 #size-cells = <0>;
524
525 int_mii_phy: ethernet-phy@1 {
526 compatible = "ethernet-phy-ieee802.3-c22";
527 reg = <1>;
528 clocks = <&ccu CLK_BUS_EPHY>;
529 resets = <&ccu RST_BUS_EPHY>;
530 };
531 };
532
533 external_mdio: mdio@2 {
534 reg = <2>;
535 #address-cells = <1>;
536 #size-cells = <0>;
4b236a0f
CL		 537 };
538 };
539 };
540
a3fd57f5 541 spi0: spi@1c68000 {
0127216f
AP		 542 compatible = "allwinner,sun8i-h3-spi";
543 reg = <0x01c68000 0x1000>;
544 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
546 clock-names = "ahb", "mod";
547 dmas = <&dma 23>, <&dma 23>;
548 dma-names = "rx", "tx";
549 pinctrl-names = "default";
550 pinctrl-0 = <&spi0_pins>;
551 resets = <&ccu RST_BUS_SPI0>;
552 status = "disabled";
553 #address-cells = <1>;
554 #size-cells = <0>;
555 };
556
a3fd57f5 557 spi1: spi@1c69000 {
0127216f
AP		 558 compatible = "allwinner,sun8i-h3-spi";
559 reg = <0x01c69000 0x1000>;
560 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
562 clock-names = "ahb", "mod";
563 dmas = <&dma 24>, <&dma 24>;
564 dma-names = "rx", "tx";
565 pinctrl-names = "default";
566 pinctrl-0 = <&spi1_pins>;
567 resets = <&ccu RST_BUS_SPI1>;
568 status = "disabled";
569 #address-cells = <1>;
570 #size-cells = <0>;
571 };
572
a3fd57f5 573 wdt0: watchdog@1c20ca0 {
0127216f
AP		 574 compatible = "allwinner,sun6i-a31-wdt";
575 reg = <0x01c20ca0 0x20>;
576 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
577 };
578
a3fd57f5 579 spdif: spdif@1c21000 {
0127216f
AP		 580 #sound-dai-cells = <0>;
581 compatible = "allwinner,sun8i-h3-spdif";
582 reg = <0x01c21000 0x400>;
583 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
585 resets = <&ccu RST_BUS_SPDIF>;
586 clock-names = "apb", "spdif";
587 dmas = <&dma 2>;
588 dma-names = "tx";
589 status = "disabled";
590 };
591
a3fd57f5 592 pwm: pwm@1c21400 {
0127216f
AP		 593 compatible = "allwinner,sun8i-h3-pwm";
594 reg = <0x01c21400 0x8>;
595 clocks = <&osc24M>;
596 #pwm-cells = <3>;
597 status = "disabled";
598 };
599
a3fd57f5 600 i2s0: i2s@1c22000 {
ef19098a
MC		 601 #sound-dai-cells = <0>;
602 compatible = "allwinner,sun8i-h3-i2s";
603 reg = <0x01c22000 0x400>;
604 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
606 clock-names = "apb", "mod";
607 dmas = <&dma 3>, <&dma 3>;
608 resets = <&ccu RST_BUS_I2S0>;
609 dma-names = "rx", "tx";
610 status = "disabled";
611 };
612
a3fd57f5 613 i2s1: i2s@1c22400 {
ef19098a
MC		 614 #sound-dai-cells = <0>;
615 compatible = "allwinner,sun8i-h3-i2s";
616 reg = <0x01c22400 0x400>;
617 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
619 clock-names = "apb", "mod";
620 dmas = <&dma 4>, <&dma 4>;
621 resets = <&ccu RST_BUS_I2S1>;
622 dma-names = "rx", "tx";
623 status = "disabled";
624 };
625
a3fd57f5 626 codec: codec@1c22c00 {
0127216f
AP		 627 #sound-dai-cells = <0>;
628 compatible = "allwinner,sun8i-h3-codec";
629 reg = <0x01c22c00 0x400>;
630 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
632 clock-names = "apb", "codec";
633 resets = <&ccu RST_BUS_CODEC>;
634 dmas = <&dma 15>, <&dma 15>;
635 dma-names = "rx", "tx";
636 allwinner,codec-analog-controls = <&codec_analog>;
637 status = "disabled";
638 };
639
a3fd57f5 640 uart0: serial@1c28000 {
0127216f
AP		 641 compatible = "snps,dw-apb-uart";
642 reg = <0x01c28000 0x400>;
643 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
644 reg-shift = <2>;
645 reg-io-width = <4>;
646 clocks = <&ccu CLK_BUS_UART0>;
647 resets = <&ccu RST_BUS_UART0>;
648 dmas = <&dma 6>, <&dma 6>;
649 dma-names = "rx", "tx";
650 status = "disabled";
651 };
652
a3fd57f5 653 uart1: serial@1c28400 {
0127216f
AP		 654 compatible = "snps,dw-apb-uart";
655 reg = <0x01c28400 0x400>;
656 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
657 reg-shift = <2>;
658 reg-io-width = <4>;
659 clocks = <&ccu CLK_BUS_UART1>;
660 resets = <&ccu RST_BUS_UART1>;
661 dmas = <&dma 7>, <&dma 7>;
662 dma-names = "rx", "tx";
663 status = "disabled";
664 };
665
a3fd57f5 666 uart2: serial@1c28800 {
0127216f
AP		 667 compatible = "snps,dw-apb-uart";
668 reg = <0x01c28800 0x400>;
669 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
670 reg-shift = <2>;
671 reg-io-width = <4>;
672 clocks = <&ccu CLK_BUS_UART2>;
673 resets = <&ccu RST_BUS_UART2>;
674 dmas = <&dma 8>, <&dma 8>;
675 dma-names = "rx", "tx";
676 status = "disabled";
677 };
678
a3fd57f5 679 uart3: serial@1c28c00 {
0127216f
AP		 680 compatible = "snps,dw-apb-uart";
681 reg = <0x01c28c00 0x400>;
682 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
683 reg-shift = <2>;
684 reg-io-width = <4>;
685 clocks = <&ccu CLK_BUS_UART3>;
686 resets = <&ccu RST_BUS_UART3>;
687 dmas = <&dma 9>, <&dma 9>;
688 dma-names = "rx", "tx";
689 status = "disabled";
690 };
691
a3fd57f5 692 i2c0: i2c@1c2ac00 {
0127216f
AP		 693 compatible = "allwinner,sun6i-a31-i2c";
694 reg = <0x01c2ac00 0x400>;
695 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&ccu CLK_BUS_I2C0>;
697 resets = <&ccu RST_BUS_I2C0>;
698 pinctrl-names = "default";
699 pinctrl-0 = <&i2c0_pins>;
700 status = "disabled";
701 #address-cells = <1>;
702 #size-cells = <0>;
703 };
704
a3fd57f5 705 i2c1: i2c@1c2b000 {
0127216f
AP		 706 compatible = "allwinner,sun6i-a31-i2c";
707 reg = <0x01c2b000 0x400>;
708 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&ccu CLK_BUS_I2C1>;
710 resets = <&ccu RST_BUS_I2C1>;
711 pinctrl-names = "default";
712 pinctrl-0 = <&i2c1_pins>;
713 status = "disabled";
714 #address-cells = <1>;
715 #size-cells = <0>;
716 };
717
a3fd57f5 718 i2c2: i2c@1c2b400 {
0127216f 719 compatible = "allwinner,sun6i-a31-i2c";
4d2ee8d5 720 reg = <0x01c2b400 0x400>;
0127216f
AP		 721 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&ccu CLK_BUS_I2C2>;
723 resets = <&ccu RST_BUS_I2C2>;
724 pinctrl-names = "default";
725 pinctrl-0 = <&i2c2_pins>;
726 status = "disabled";
727 #address-cells = <1>;
728 #size-cells = <0>;
729 };
730
a3fd57f5 731 gic: interrupt-controller@1c81000 {
0127216f
AP		 732 compatible = "arm,gic-400";
733 reg = <0x01c81000 0x1000>,
734 <0x01c82000 0x2000>,
735 <0x01c84000 0x2000>,
736 <0x01c86000 0x2000>;
737 interrupt-controller;
738 #interrupt-cells = <3>;
739 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
740 };
741
f89120b6 742 csi: camera@1cb0000 {
4d1796ef 743 compatible = "allwinner,sun8i-h3-csi";
f89120b6
MJ		 744 reg = <0x01cb0000 0x1000>;
745 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
746 clocks = <&ccu CLK_BUS_CSI>,
747 <&ccu CLK_CSI_SCLK>,
748 <&ccu CLK_DRAM_CSI>;
749 clock-names = "bus", "mod", "ram";
750 resets = <&ccu RST_BUS_CSI>;
751 pinctrl-names = "default";
752 pinctrl-0 = <&csi_pins>;
753 status = "disabled";
754 };
755
cb34d825
JS		 756 hdmi: hdmi@1ee0000 {
757 compatible = "allwinner,sun8i-h3-dw-hdmi",
758 "allwinner,sun8i-a83t-dw-hdmi";
759 reg = <0x01ee0000 0x10000>;
760 reg-io-width = <1>;
761 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
762 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
763 <&ccu CLK_HDMI>;
764 clock-names = "iahb", "isfr", "tmds";
765 resets = <&ccu RST_BUS_HDMI1>;
766 reset-names = "ctrl";
767 phys = <&hdmi_phy>;
768 phy-names = "hdmi-phy";
769 status = "disabled";
770
771 ports {
772 #address-cells = <1>;
773 #size-cells = <0>;
774
775 hdmi_in: port@0 {
776 reg = <0>;
777
778 hdmi_in_tcon0: endpoint {
779 remote-endpoint = <&tcon0_out_hdmi>;
780 };
781 };
782
783 hdmi_out: port@1 {
784 reg = <1>;
785 };
786 };
787 };
788
789 hdmi_phy: hdmi-phy@1ef0000 {
790 compatible = "allwinner,sun8i-h3-hdmi-phy";
791 reg = <0x01ef0000 0x10000>;
792 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
793 <&ccu 6>;
794 clock-names = "bus", "mod", "pll-0";
795 resets = <&ccu RST_BUS_HDMI0>;
796 reset-names = "phy";
797 #phy-cells = <0>;
798 };
799
a3fd57f5 800 rtc: rtc@1f00000 {
507c6e89
CYT		 801 /* compatible is in per SoC .dtsi file */
802 reg = <0x01f00000 0x400>;
0127216f
AP		 803 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
804 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
507c6e89
CYT		 805 clock-output-names = "osc32k", "osc32k-out", "iosc";
806 clocks = <&osc32k>;
807 #clock-cells = <1>;
0127216f
AP		 808 };
809
d7bb5b96 810 r_ccu: clock@1f01400 {
a27b49b8 811 compatible = "allwinner,sun8i-h3-r-ccu";
d7bb5b96 812 reg = <0x01f01400 0x100>;
507c6e89 813 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 9>;
77125a70 814 clock-names = "hosc", "losc", "iosc", "pll-periph";
d7bb5b96 815 #clock-cells = <1>;
0127216f
AP		 816 #reset-cells = <1>;
817 };
818
a3fd57f5 819 codec_analog: codec-analog@1f015c0 {
0127216f
AP		 820 compatible = "allwinner,sun8i-h3-codec-analog";
821 reg = <0x01f015c0 0x4>;
822 };
823
a3fd57f5 824 ir: ir@1f02000 {
0127216f 825 compatible = "allwinner,sun5i-a13-ir";
98d87eb5 826 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
0127216f 827 clock-names = "apb", "ir";
98d87eb5 828 resets = <&r_ccu RST_APB0_IR>;
0127216f 829 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
6c700289 830 reg = <0x01f02000 0x400>;
0127216f
AP		 831 status = "disabled";
832 };
833
7824fcb3
OJ		 834 r_i2c: i2c@1f02400 {
835 compatible = "allwinner,sun6i-a31-i2c";
836 reg = <0x01f02400 0x400>;
837 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
838 pinctrl-names = "default";
839 pinctrl-0 = <&r_i2c_pins>;
840 clocks = <&r_ccu CLK_APB0_I2C>;
841 resets = <&r_ccu RST_APB0_I2C>;
842 status = "disabled";
843 #address-cells = <1>;
844 #size-cells = <0>;
845 };
846
a3fd57f5 847 r_pio: pinctrl@1f02c00 {
0127216f
AP		 848 compatible = "allwinner,sun8i-h3-r-pinctrl";
849 reg = <0x01f02c00 0x400>;
850 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
507c6e89 851 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>;
0127216f 852 clock-names = "apb", "hosc", "losc";
0127216f
AP		 853 gpio-controller;
854 #gpio-cells = <3>;
855 interrupt-controller;
856 #interrupt-cells = <3>;
857
31e79286 858 ir_pins_a: ir {
0127216f
AP		 859 pins = "PL11";
860 function = "s_cir_rx";
861 };
4b877d4a
OJ		 862
863 r_i2c_pins: r-i2c {
864 pins = "PL0", "PL1";
865 function = "s_i2c";
866 };
0127216f
AP		 867 };
868 };
869};
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