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ARM: dts: sun8i: h2-plus: remove unnecessary mmc1_pins node
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / sunxi-h3-h5.dtsi
CommitLineData
0127216f
AP		 1/*
2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
d8c6f1f0 43#include <dt-bindings/clock/sun8i-de2.h>
0127216f 44#include <dt-bindings/clock/sun8i-h3-ccu.h>
98d87eb5 45#include <dt-bindings/clock/sun8i-r-ccu.h>
0127216f 46#include <dt-bindings/interrupt-controller/arm-gic.h>
d8c6f1f0 47#include <dt-bindings/reset/sun8i-de2.h>
0127216f 48#include <dt-bindings/reset/sun8i-h3-ccu.h>
98d87eb5 49#include <dt-bindings/reset/sun8i-r-ccu.h>
0127216f
AP		 50
51/ {
52 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <1>;
55
9b9931e5
IZ		 56 chosen {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges;
60
61 framebuffer-hdmi {
62 compatible = "allwinner,simple-framebuffer",
63 "simple-framebuffer";
64 allwinner,pipeline = "mixer0-lcd0-hdmi";
65 clocks = <&display_clocks CLK_MIXER0>,
66 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
67 status = "disabled";
68 };
69
70 framebuffer-tve {
71 compatible = "allwinner,simple-framebuffer",
72 "simple-framebuffer";
73 allwinner,pipeline = "mixer1-lcd1-tve";
74 clocks = <&display_clocks CLK_MIXER1>,
75 <&ccu CLK_TVE>;
76 status = "disabled";
77 };
78 };
79
0127216f
AP		 80 clocks {
81 #address-cells = <1>;
82 #size-cells = <1>;
83 ranges;
84
85 osc24M: osc24M_clk {
86 #clock-cells = <0>;
87 compatible = "fixed-clock";
88 clock-frequency = <24000000>;
89 clock-output-names = "osc24M";
90 };
91
92 osc32k: osc32k_clk {
93 #clock-cells = <0>;
94 compatible = "fixed-clock";
95 clock-frequency = <32768>;
96 clock-output-names = "osc32k";
97 };
98
d7bb5b96 99 iosc: internal-osc-clk {
0127216f 100 #clock-cells = <0>;
d7bb5b96
IZ		 101 compatible = "fixed-clock";
102 clock-frequency = <16000000>;
103 clock-accuracy = <300000000>;
104 clock-output-names = "iosc";
0127216f
AP		 105 };
106 };
107
108 soc {
109 compatible = "simple-bus";
110 #address-cells = <1>;
111 #size-cells = <1>;
112 ranges;
113
d8c6f1f0
IZ		 114 display_clocks: clock@1000000 {
115 /* compatible is in per SoC .dtsi file */
116 reg = <0x01000000 0x100000>;
117 clocks = <&ccu CLK_DE>,
118 <&ccu CLK_BUS_DE>;
119 clock-names = "mod",
120 "bus";
121 resets = <&ccu RST_BUS_DE>;
122 #clock-cells = <1>;
123 #reset-cells = <1>;
124 };
125
d91d3daf
CL		 126 syscon: syscon@1c00000 {
127 compatible = "allwinner,sun8i-h3-system-controller",
128 "syscon";
129 reg = <0x01c00000 0x1000>;
130 };
131
a3fd57f5 132 dma: dma-controller@1c02000 {
0127216f
AP		 133 compatible = "allwinner,sun8i-h3-dma";
134 reg = <0x01c02000 0x1000>;
135 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&ccu CLK_BUS_DMA>;
137 resets = <&ccu RST_BUS_DMA>;
138 #dma-cells = <1>;
139 };
140
a3fd57f5 141 mmc0: mmc@1c0f000 {
0127216f
AP		 142 /* compatible and clocks are in per SoC .dtsi file */
143 reg = <0x01c0f000 0x1000>;
50caa756 144 pinctrl-names = "default";
8566df71 145 pinctrl-0 = <&mmc0_pins>;
0127216f
AP		 146 resets = <&ccu RST_BUS_MMC0>;
147 reset-names = "ahb";
148 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
149 status = "disabled";
150 #address-cells = <1>;
151 #size-cells = <0>;
152 };
153
a3fd57f5 154 mmc1: mmc@1c10000 {
0127216f
AP		 155 /* compatible and clocks are in per SoC .dtsi file */
156 reg = <0x01c10000 0x1000>;
e607b605 157 pinctrl-names = "default";
8566df71 158 pinctrl-0 = <&mmc1_pins>;
0127216f
AP		 159 resets = <&ccu RST_BUS_MMC1>;
160 reset-names = "ahb";
161 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
162 status = "disabled";
163 #address-cells = <1>;
164 #size-cells = <0>;
165 };
166
a3fd57f5 167 mmc2: mmc@1c11000 {
0127216f
AP		 168 /* compatible and clocks are in per SoC .dtsi file */
169 reg = <0x01c11000 0x1000>;
170 resets = <&ccu RST_BUS_MMC2>;
171 reset-names = "ahb";
172 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
173 status = "disabled";
174 #address-cells = <1>;
175 #size-cells = <0>;
176 };
177
a3fd57f5 178 usb_otg: usb@1c19000 {
da89e1d5
IZ		 179 compatible = "allwinner,sun8i-h3-musb";
180 reg = <0x01c19000 0x400>;
181 clocks = <&ccu CLK_BUS_OTG>;
182 resets = <&ccu RST_BUS_OTG>;
183 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
184 interrupt-names = "mc";
185 phys = <&usbphy 0>;
186 phy-names = "usb";
187 extcon = <&usbphy 0>;
188 status = "disabled";
189 };
190
a3fd57f5 191 usbphy: phy@1c19400 {
0127216f
AP		 192 compatible = "allwinner,sun8i-h3-usb-phy";
193 reg = <0x01c19400 0x2c>,
194 <0x01c1a800 0x4>,
195 <0x01c1b800 0x4>,
196 <0x01c1c800 0x4>,
197 <0x01c1d800 0x4>;
198 reg-names = "phy_ctrl",
199 "pmu0",
200 "pmu1",
201 "pmu2",
202 "pmu3";
203 clocks = <&ccu CLK_USB_PHY0>,
204 <&ccu CLK_USB_PHY1>,
205 <&ccu CLK_USB_PHY2>,
206 <&ccu CLK_USB_PHY3>;
207 clock-names = "usb0_phy",
208 "usb1_phy",
209 "usb2_phy",
210 "usb3_phy";
211 resets = <&ccu RST_USB_PHY0>,
212 <&ccu RST_USB_PHY1>,
213 <&ccu RST_USB_PHY2>,
214 <&ccu RST_USB_PHY3>;
215 reset-names = "usb0_reset",
216 "usb1_reset",
217 "usb2_reset",
218 "usb3_reset";
219 status = "disabled";
220 #phy-cells = <1>;
221 };
222
a3fd57f5 223 ehci0: usb@1c1a000 {
da89e1d5
IZ		 224 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
225 reg = <0x01c1a000 0x100>;
226 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
228 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
229 status = "disabled";
230 };
231
a3fd57f5 232 ohci0: usb@1c1a400 {
da89e1d5
IZ		 233 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
234 reg = <0x01c1a400 0x100>;
235 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
237 <&ccu CLK_USB_OHCI0>;
238 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
239 status = "disabled";
240 };
241
a3fd57f5 242 ehci1: usb@1c1b000 {
0127216f
AP		 243 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
244 reg = <0x01c1b000 0x100>;
245 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
247 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
248 phys = <&usbphy 1>;
249 phy-names = "usb";
250 status = "disabled";
251 };
252
a3fd57f5 253 ohci1: usb@1c1b400 {
0127216f
AP		 254 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
255 reg = <0x01c1b400 0x100>;
256 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
258 <&ccu CLK_USB_OHCI1>;
259 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
260 phys = <&usbphy 1>;
261 phy-names = "usb";
262 status = "disabled";
263 };
264
a3fd57f5 265 ehci2: usb@1c1c000 {
0127216f
AP		 266 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
267 reg = <0x01c1c000 0x100>;
268 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
270 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
271 phys = <&usbphy 2>;
272 phy-names = "usb";
273 status = "disabled";
274 };
275
a3fd57f5 276 ohci2: usb@1c1c400 {
0127216f
AP		 277 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
278 reg = <0x01c1c400 0x100>;
279 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
281 <&ccu CLK_USB_OHCI2>;
282 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
283 phys = <&usbphy 2>;
284 phy-names = "usb";
285 status = "disabled";
286 };
287
a3fd57f5 288 ehci3: usb@1c1d000 {
0127216f
AP		 289 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
290 reg = <0x01c1d000 0x100>;
291 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
293 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
294 phys = <&usbphy 3>;
295 phy-names = "usb";
296 status = "disabled";
297 };
298
a3fd57f5 299 ohci3: usb@1c1d400 {
0127216f
AP		 300 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
301 reg = <0x01c1d400 0x100>;
302 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
304 <&ccu CLK_USB_OHCI3>;
305 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
306 phys = <&usbphy 3>;
307 phy-names = "usb";
308 status = "disabled";
309 };
310
a3fd57f5 311 ccu: clock@1c20000 {
0127216f
AP		 312 /* compatible is in per SoC .dtsi file */
313 reg = <0x01c20000 0x400>;
314 clocks = <&osc24M>, <&osc32k>;
315 clock-names = "hosc", "losc";
316 #clock-cells = <1>;
317 #reset-cells = <1>;
318 };
319
a3fd57f5 320 pio: pinctrl@1c20800 {
0127216f
AP		 321 /* compatible is in per SoC .dtsi file */
322 reg = <0x01c20800 0x400>;
323 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
326 clock-names = "apb", "hosc", "losc";
327 gpio-controller;
328 #gpio-cells = <3>;
329 interrupt-controller;
330 #interrupt-cells = <3>;
331
0eba511a
CL		 332 emac_rgmii_pins: emac0 {
333 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
334 "PD5", "PD7", "PD8", "PD9", "PD10",
335 "PD12", "PD13", "PD15", "PD16", "PD17";
336 function = "emac";
337 drive-strength = <40>;
338 };
339
0127216f
AP		 340 i2c0_pins: i2c0 {
341 pins = "PA11", "PA12";
342 function = "i2c0";
343 };
344
345 i2c1_pins: i2c1 {
346 pins = "PA18", "PA19";
347 function = "i2c1";
348 };
349
350 i2c2_pins: i2c2 {
351 pins = "PE12", "PE13";
352 function = "i2c2";
353 };
354
8566df71 355 mmc0_pins: mmc0 {
0127216f
AP		 356 pins = "PF0", "PF1", "PF2", "PF3",
357 "PF4", "PF5";
358 function = "mmc0";
359 drive-strength = <30>;
360 bias-pull-up;
361 };
362
8566df71 363 mmc1_pins: mmc1 {
0127216f
AP		 364 pins = "PG0", "PG1", "PG2", "PG3",
365 "PG4", "PG5";
366 function = "mmc1";
367 drive-strength = <30>;
368 bias-pull-up;
369 };
370
371 mmc2_8bit_pins: mmc2_8bit {
372 pins = "PC5", "PC6", "PC8",
373 "PC9", "PC10", "PC11",
374 "PC12", "PC13", "PC14",
375 "PC15", "PC16";
376 function = "mmc2";
377 drive-strength = <30>;
378 bias-pull-up;
379 };
380
31e79286 381 spdif_tx_pins_a: spdif {
0127216f
AP		 382 pins = "PA17";
383 function = "spdif";
384 };
385
386 spi0_pins: spi0 {
387 pins = "PC0", "PC1", "PC2", "PC3";
388 function = "spi0";
389 };
390
391 spi1_pins: spi1 {
392 pins = "PA15", "PA16", "PA14", "PA13";
393 function = "spi1";
394 };
395
31e79286 396 uart0_pins_a: uart0 {
0127216f
AP		 397 pins = "PA4", "PA5";
398 function = "uart0";
399 };
400
401 uart1_pins: uart1 {
402 pins = "PG6", "PG7";
403 function = "uart1";
404 };
405
406 uart1_rts_cts_pins: uart1_rts_cts {
407 pins = "PG8", "PG9";
408 function = "uart1";
409 };
410
411 uart2_pins: uart2 {
412 pins = "PA0", "PA1";
413 function = "uart2";
414 };
415
416 uart3_pins: uart3 {
417 pins = "PA13", "PA14";
418 function = "uart3";
419 };
5a8e62eb
PR		 420
421 uart3_rts_cts_pins: uart3_rts_cts {
422 pins = "PA15", "PA16";
423 function = "uart3";
424 };
0127216f
AP		 425 };
426
a3fd57f5 427 timer@1c20c00 {
0127216f
AP		 428 compatible = "allwinner,sun4i-a10-timer";
429 reg = <0x01c20c00 0xa0>;
430 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&osc24M>;
433 };
434
4b236a0f
CL		 435 emac: ethernet@1c30000 {
436 compatible = "allwinner,sun8i-h3-emac";
437 syscon = <&syscon>;
438 reg = <0x01c30000 0x10000>;
439 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
440 interrupt-names = "macirq";
441 resets = <&ccu RST_BUS_EMAC>;
442 reset-names = "stmmaceth";
443 clocks = <&ccu CLK_BUS_EMAC>;
444 clock-names = "stmmaceth";
445 #address-cells = <1>;
446 #size-cells = <0>;
447 status = "disabled";
448
449 mdio: mdio {
450 #address-cells = <1>;
451 #size-cells = <0>;
776245ae
CL		 452 compatible = "snps,dwmac-mdio";
453 };
454
455 mdio-mux {
456 compatible = "allwinner,sun8i-h3-mdio-mux";
457 #address-cells = <1>;
458 #size-cells = <0>;
459
460 mdio-parent-bus = <&mdio>;
461 /* Only one MDIO is usable at the time */
462 internal_mdio: mdio@1 {
463 compatible = "allwinner,sun8i-h3-mdio-internal";
4b236a0f 464 reg = <1>;
776245ae
CL		 465 #address-cells = <1>;
466 #size-cells = <0>;
467
468 int_mii_phy: ethernet-phy@1 {
469 compatible = "ethernet-phy-ieee802.3-c22";
470 reg = <1>;
471 clocks = <&ccu CLK_BUS_EPHY>;
472 resets = <&ccu RST_BUS_EPHY>;
473 };
474 };
475
476 external_mdio: mdio@2 {
477 reg = <2>;
478 #address-cells = <1>;
479 #size-cells = <0>;
4b236a0f
CL		 480 };
481 };
482 };
483
a3fd57f5 484 spi0: spi@1c68000 {
0127216f
AP		 485 compatible = "allwinner,sun8i-h3-spi";
486 reg = <0x01c68000 0x1000>;
487 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
489 clock-names = "ahb", "mod";
490 dmas = <&dma 23>, <&dma 23>;
491 dma-names = "rx", "tx";
492 pinctrl-names = "default";
493 pinctrl-0 = <&spi0_pins>;
494 resets = <&ccu RST_BUS_SPI0>;
495 status = "disabled";
496 #address-cells = <1>;
497 #size-cells = <0>;
498 };
499
a3fd57f5 500 spi1: spi@1c69000 {
0127216f
AP		 501 compatible = "allwinner,sun8i-h3-spi";
502 reg = <0x01c69000 0x1000>;
503 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
505 clock-names = "ahb", "mod";
506 dmas = <&dma 24>, <&dma 24>;
507 dma-names = "rx", "tx";
508 pinctrl-names = "default";
509 pinctrl-0 = <&spi1_pins>;
510 resets = <&ccu RST_BUS_SPI1>;
511 status = "disabled";
512 #address-cells = <1>;
513 #size-cells = <0>;
514 };
515
a3fd57f5 516 wdt0: watchdog@1c20ca0 {
0127216f
AP		 517 compatible = "allwinner,sun6i-a31-wdt";
518 reg = <0x01c20ca0 0x20>;
519 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
520 };
521
a3fd57f5 522 spdif: spdif@1c21000 {
0127216f
AP		 523 #sound-dai-cells = <0>;
524 compatible = "allwinner,sun8i-h3-spdif";
525 reg = <0x01c21000 0x400>;
526 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
528 resets = <&ccu RST_BUS_SPDIF>;
529 clock-names = "apb", "spdif";
530 dmas = <&dma 2>;
531 dma-names = "tx";
532 status = "disabled";
533 };
534
a3fd57f5 535 pwm: pwm@1c21400 {
0127216f
AP		 536 compatible = "allwinner,sun8i-h3-pwm";
537 reg = <0x01c21400 0x8>;
538 clocks = <&osc24M>;
539 #pwm-cells = <3>;
540 status = "disabled";
541 };
542
a3fd57f5 543 i2s0: i2s@1c22000 {
ef19098a
MC		 544 #sound-dai-cells = <0>;
545 compatible = "allwinner,sun8i-h3-i2s";
546 reg = <0x01c22000 0x400>;
547 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
549 clock-names = "apb", "mod";
550 dmas = <&dma 3>, <&dma 3>;
551 resets = <&ccu RST_BUS_I2S0>;
552 dma-names = "rx", "tx";
553 status = "disabled";
554 };
555
a3fd57f5 556 i2s1: i2s@1c22400 {
ef19098a
MC		 557 #sound-dai-cells = <0>;
558 compatible = "allwinner,sun8i-h3-i2s";
559 reg = <0x01c22400 0x400>;
560 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
562 clock-names = "apb", "mod";
563 dmas = <&dma 4>, <&dma 4>;
564 resets = <&ccu RST_BUS_I2S1>;
565 dma-names = "rx", "tx";
566 status = "disabled";
567 };
568
a3fd57f5 569 codec: codec@1c22c00 {
0127216f
AP		 570 #sound-dai-cells = <0>;
571 compatible = "allwinner,sun8i-h3-codec";
572 reg = <0x01c22c00 0x400>;
573 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
575 clock-names = "apb", "codec";
576 resets = <&ccu RST_BUS_CODEC>;
577 dmas = <&dma 15>, <&dma 15>;
578 dma-names = "rx", "tx";
579 allwinner,codec-analog-controls = <&codec_analog>;
580 status = "disabled";
581 };
582
a3fd57f5 583 uart0: serial@1c28000 {
0127216f
AP		 584 compatible = "snps,dw-apb-uart";
585 reg = <0x01c28000 0x400>;
586 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
587 reg-shift = <2>;
588 reg-io-width = <4>;
589 clocks = <&ccu CLK_BUS_UART0>;
590 resets = <&ccu RST_BUS_UART0>;
591 dmas = <&dma 6>, <&dma 6>;
592 dma-names = "rx", "tx";
593 status = "disabled";
594 };
595
a3fd57f5 596 uart1: serial@1c28400 {
0127216f
AP		 597 compatible = "snps,dw-apb-uart";
598 reg = <0x01c28400 0x400>;
599 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
600 reg-shift = <2>;
601 reg-io-width = <4>;
602 clocks = <&ccu CLK_BUS_UART1>;
603 resets = <&ccu RST_BUS_UART1>;
604 dmas = <&dma 7>, <&dma 7>;
605 dma-names = "rx", "tx";
606 status = "disabled";
607 };
608
a3fd57f5 609 uart2: serial@1c28800 {
0127216f
AP		 610 compatible = "snps,dw-apb-uart";
611 reg = <0x01c28800 0x400>;
612 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
613 reg-shift = <2>;
614 reg-io-width = <4>;
615 clocks = <&ccu CLK_BUS_UART2>;
616 resets = <&ccu RST_BUS_UART2>;
617 dmas = <&dma 8>, <&dma 8>;
618 dma-names = "rx", "tx";
619 status = "disabled";
620 };
621
a3fd57f5 622 uart3: serial@1c28c00 {
0127216f
AP		 623 compatible = "snps,dw-apb-uart";
624 reg = <0x01c28c00 0x400>;
625 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
626 reg-shift = <2>;
627 reg-io-width = <4>;
628 clocks = <&ccu CLK_BUS_UART3>;
629 resets = <&ccu RST_BUS_UART3>;
630 dmas = <&dma 9>, <&dma 9>;
631 dma-names = "rx", "tx";
632 status = "disabled";
633 };
634
a3fd57f5 635 i2c0: i2c@1c2ac00 {
0127216f
AP		 636 compatible = "allwinner,sun6i-a31-i2c";
637 reg = <0x01c2ac00 0x400>;
638 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&ccu CLK_BUS_I2C0>;
640 resets = <&ccu RST_BUS_I2C0>;
641 pinctrl-names = "default";
642 pinctrl-0 = <&i2c0_pins>;
643 status = "disabled";
644 #address-cells = <1>;
645 #size-cells = <0>;
646 };
647
a3fd57f5 648 i2c1: i2c@1c2b000 {
0127216f
AP		 649 compatible = "allwinner,sun6i-a31-i2c";
650 reg = <0x01c2b000 0x400>;
651 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&ccu CLK_BUS_I2C1>;
653 resets = <&ccu RST_BUS_I2C1>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&i2c1_pins>;
656 status = "disabled";
657 #address-cells = <1>;
658 #size-cells = <0>;
659 };
660
a3fd57f5 661 i2c2: i2c@1c2b400 {
0127216f 662 compatible = "allwinner,sun6i-a31-i2c";
4d2ee8d5 663 reg = <0x01c2b400 0x400>;
0127216f
AP		 664 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&ccu CLK_BUS_I2C2>;
666 resets = <&ccu RST_BUS_I2C2>;
667 pinctrl-names = "default";
668 pinctrl-0 = <&i2c2_pins>;
669 status = "disabled";
670 #address-cells = <1>;
671 #size-cells = <0>;
672 };
673
a3fd57f5 674 gic: interrupt-controller@1c81000 {
0127216f
AP		 675 compatible = "arm,gic-400";
676 reg = <0x01c81000 0x1000>,
677 <0x01c82000 0x2000>,
678 <0x01c84000 0x2000>,
679 <0x01c86000 0x2000>;
680 interrupt-controller;
681 #interrupt-cells = <3>;
682 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
683 };
684
a3fd57f5 685 rtc: rtc@1f00000 {
0127216f
AP		 686 compatible = "allwinner,sun6i-a31-rtc";
687 reg = <0x01f00000 0x54>;
688 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
690 };
691
d7bb5b96 692 r_ccu: clock@1f01400 {
a27b49b8 693 compatible = "allwinner,sun8i-h3-r-ccu";
d7bb5b96 694 reg = <0x01f01400 0x100>;
77125a70
CYT		 695 clocks = <&osc24M>, <&osc32k>, <&iosc>,
696 <&ccu 9>;
697 clock-names = "hosc", "losc", "iosc", "pll-periph";
d7bb5b96 698 #clock-cells = <1>;
0127216f
AP		 699 #reset-cells = <1>;
700 };
701
a3fd57f5 702 codec_analog: codec-analog@1f015c0 {
0127216f
AP		 703 compatible = "allwinner,sun8i-h3-codec-analog";
704 reg = <0x01f015c0 0x4>;
705 };
706
a3fd57f5 707 ir: ir@1f02000 {
0127216f 708 compatible = "allwinner,sun5i-a13-ir";
98d87eb5 709 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
0127216f 710 clock-names = "apb", "ir";
98d87eb5 711 resets = <&r_ccu RST_APB0_IR>;
0127216f
AP		 712 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
713 reg = <0x01f02000 0x40>;
714 status = "disabled";
715 };
716
a3fd57f5 717 r_pio: pinctrl@1f02c00 {
0127216f
AP		 718 compatible = "allwinner,sun8i-h3-r-pinctrl";
719 reg = <0x01f02c00 0x400>;
720 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
98d87eb5 721 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
0127216f 722 clock-names = "apb", "hosc", "losc";
0127216f
AP		 723 gpio-controller;
724 #gpio-cells = <3>;
725 interrupt-controller;
726 #interrupt-cells = <3>;
727
31e79286 728 ir_pins_a: ir {
0127216f
AP		 729 pins = "PL11";
730 function = "s_cir_rx";
731 };
732 };
733 };
734};
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