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Merge remote-tracking branches 'asoc/topic/tas2552', 'asoc/topic/tegra', 'asoc/topic...
[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / tegra114.dtsi
CommitLineData
a1c85860 1#include <dt-bindings/clock/tegra114-car.h>
3325f1bc 2#include <dt-bindings/gpio/tegra-gpio.h>
5fc6b0dd 3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6cecf916 4#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 5
1bd0bd49 6#include "skeleton.dtsi"
18a4df70
HD		 7
8/ {
9 compatible = "nvidia,tegra114";
10 interrupt-parent = <&gic>;
11
65344b93
MP		 12 host1x@50000000 {
13 compatible = "nvidia,tegra114-host1x", "simple-bus";
14 reg = <0x50000000 0x00028000>;
15 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
16 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
17 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
18 resets = <&tegra_car 28>;
19 reset-names = "host1x";
20
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 ranges = <0x54000000 0x54000000 0x01000000>;
25
5648b260
TR		 26 gr2d@54140000 {
27 compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
28 reg = <0x54140000 0x00040000>;
29 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
30 clocks = <&tegra_car TEGRA114_CLK_GR2D>;
31 resets = <&tegra_car 21>;
32 reset-names = "2d";
33 };
34
032f11f3
TR		 35 gr3d@54180000 {
36 compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
37 reg = <0x54180000 0x00040000>;
38 clocks = <&tegra_car TEGRA114_CLK_GR3D>;
39 resets = <&tegra_car 24>;
40 reset-names = "3d";
41 };
42
65344b93
MP		 43 dc@54200000 {
44 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
45 reg = <0x54200000 0x00040000>;
46 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
47 clocks = <&tegra_car TEGRA114_CLK_DISP1>,
48 <&tegra_car TEGRA114_CLK_PLL_P>;
49 clock-names = "dc", "parent";
50 resets = <&tegra_car 27>;
51 reset-names = "dc";
52
688b56b4
TR		 53 nvidia,head = <0>;
54
65344b93
MP		 55 rgb {
56 status = "disabled";
57 };
58 };
59
60 dc@54240000 {
61 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
62 reg = <0x54240000 0x00040000>;
63 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
64 clocks = <&tegra_car TEGRA114_CLK_DISP2>,
65 <&tegra_car TEGRA114_CLK_PLL_P>;
66 clock-names = "dc", "parent";
67 resets = <&tegra_car 26>;
68 reset-names = "dc";
69
688b56b4
TR		 70 nvidia,head = <1>;
71
65344b93
MP		 72 rgb {
73 status = "disabled";
74 };
75 };
76
77 hdmi@54280000 {
78 compatible = "nvidia,tegra114-hdmi";
79 reg = <0x54280000 0x00040000>;
80 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
81 clocks = <&tegra_car TEGRA114_CLK_HDMI>,
82 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
83 clock-names = "hdmi", "parent";
84 resets = <&tegra_car 51>;
85 reset-names = "hdmi";
86 status = "disabled";
87 };
7e4ba90f
TR		 88
89 dsi@54300000 {
90 compatible = "nvidia,tegra114-dsi";
91 reg = <0x54300000 0x00040000>;
92 clocks = <&tegra_car TEGRA114_CLK_DSIA>,
93 <&tegra_car TEGRA114_CLK_DSIALP>,
94 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
95 clock-names = "dsi", "lp", "parent";
96 resets = <&tegra_car 48>;
97 reset-names = "dsi";
98 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
99 status = "disabled";
100
101 #address-cells = <1>;
102 #size-cells = <0>;
103 };
104
105 dsi@54400000 {
106 compatible = "nvidia,tegra114-dsi";
107 reg = <0x54400000 0x00040000>;
108 clocks = <&tegra_car TEGRA114_CLK_DSIB>,
109 <&tegra_car TEGRA114_CLK_DSIBLP>,
110 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
111 clock-names = "dsi", "lp", "parent";
112 resets = <&tegra_car 82>;
113 reset-names = "dsi";
114 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
115 status = "disabled";
116
117 #address-cells = <1>;
118 #size-cells = <0>;
119 };
65344b93
MP		 120 };
121
58ecb23f 122 gic: interrupt-controller@50041000 {
18a4df70
HD		 123 compatible = "arm,cortex-a15-gic";
124 #interrupt-cells = <3>;
125 interrupt-controller;
126 reg = <0x50041000 0x1000>,
127 <0x50042000 0x1000>,
128 <0x50044000 0x2000>,
129 <0x50046000 0x2000>;
6cecf916
SW		 130 interrupts = <GIC_PPI 9
131 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
18a4df70
HD		 132 };
133
134 timer@60005000 {
135 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
136 reg = <0x60005000 0x400>;
6cecf916
SW		 137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 143 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
18a4df70
HD		 144 };
145
58ecb23f 146 tegra_car: clock@60006000 {
672d889c 147 compatible = "nvidia,tegra114-car";
18a4df70
HD		 148 reg = <0x60006000 0x1000>;
149 #clock-cells = <1>;
3393d422 150 #reset-cells = <1>;
18a4df70
HD		 151 };
152
b1023134
TR		 153 flow-controller@60007000 {
154 compatible = "nvidia,tegra114-flowctrl";
155 reg = <0x60007000 0x1000>;
156 };
157
58ecb23f 158 apbdma: dma@6000a000 {
c5d9da4a
LD		 159 compatible = "nvidia,tegra114-apbdma";
160 reg = <0x6000a000 0x1400>;
6cecf916
SW		 161 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 193 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
3393d422
SW		 194 resets = <&tegra_car 34>;
195 reset-names = "dma";
034d023f 196 #dma-cells = <1>;
c5d9da4a
LD		 197 };
198
58ecb23f 199 ahb: ahb@6000c004 {
0dfe42ed
HD		 200 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
201 reg = <0x6000c004 0x14c>;
202 };
203
58ecb23f 204 gpio: gpio@6000d000 {
b16f9183
LD		 205 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
206 reg = <0x6000d000 0x1000>;
6cecf916
SW		 207 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
b16f9183
LD		 215 #gpio-cells = <2>;
216 gpio-controller;
217 #interrupt-cells = <2>;
218 interrupt-controller;
219 };
220
155dfc7b
PDS		 221 apbmisc@70000800 {
222 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
223 reg = <0x70000800 0x64 /* Chip revision */
224 0x70000008 0x04>; /* Strapping options */
225 };
226
58ecb23f 227 pinmux: pinmux@70000868 {
031b77af
LD		 228 compatible = "nvidia,tegra114-pinmux";
229 reg = <0x70000868 0x148 /* Pad control registers */
230 0x70003000 0x40c>; /* Mux registers */
231 };
232
0fb22096
LD		 233 /*
234 * There are two serial driver i.e. 8250 based simple serial
235 * driver and APB DMA based serial driver for higher baudrate
236 * and performace. To enable the 8250 based driver, the compatible
237 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
238 * the APB DMA based serial driver, the comptible is
239 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
240 */
241 uarta: serial@70006000 {
18a4df70
HD		 242 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
243 reg = <0x70006000 0x40>;
244 reg-shift = <2>;
6cecf916 245 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 246 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
3393d422
SW		 247 resets = <&tegra_car 6>;
248 reset-names = "serial";
034d023f
SW		 249 dmas = <&apbdma 8>, <&apbdma 8>;
250 dma-names = "rx", "tx";
3393d422 251 status = "disabled";
18a4df70
HD		 252 };
253
0fb22096 254 uartb: serial@70006040 {
18a4df70
HD		 255 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
256 reg = <0x70006040 0x40>;
257 reg-shift = <2>;
6cecf916 258 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 259 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
3393d422
SW		 260 resets = <&tegra_car 7>;
261 reset-names = "serial";
034d023f
SW		 262 dmas = <&apbdma 9>, <&apbdma 9>;
263 dma-names = "rx", "tx";
3393d422 264 status = "disabled";
18a4df70
HD		 265 };
266
0fb22096 267 uartc: serial@70006200 {
18a4df70
HD		 268 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
269 reg = <0x70006200 0x100>;
270 reg-shift = <2>;
6cecf916 271 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 272 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
3393d422
SW		 273 resets = <&tegra_car 55>;
274 reset-names = "serial";
034d023f
SW		 275 dmas = <&apbdma 10>, <&apbdma 10>;
276 dma-names = "rx", "tx";
3393d422 277 status = "disabled";
18a4df70
HD		 278 };
279
0fb22096 280 uartd: serial@70006300 {
18a4df70
HD		 281 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
282 reg = <0x70006300 0x100>;
283 reg-shift = <2>;
6cecf916 284 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 285 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
3393d422
SW		 286 resets = <&tegra_car 65>;
287 reset-names = "serial";
034d023f
SW		 288 dmas = <&apbdma 19>, <&apbdma 19>;
289 dma-names = "rx", "tx";
3393d422 290 status = "disabled";
18a4df70
HD		 291 };
292
58ecb23f 293 pwm: pwm@7000a000 {
6c716db5
AC		 294 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
295 reg = <0x7000a000 0x100>;
296 #pwm-cells = <2>;
a1c85860 297 clocks = <&tegra_car TEGRA114_CLK_PWM>;
3393d422
SW		 298 resets = <&tegra_car 17>;
299 reset-names = "pwm";
6c716db5
AC		 300 status = "disabled";
301 };
302
3fc2f94e
LD		 303 i2c@7000c000 {
304 compatible = "nvidia,tegra114-i2c";
305 reg = <0x7000c000 0x100>;
6cecf916 306 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 307 #address-cells = <1>;
308 #size-cells = <0>;
a1c85860 309 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
3fc2f94e 310 clock-names = "div-clk";
3393d422
SW		 311 resets = <&tegra_car 12>;
312 reset-names = "i2c";
034d023f
SW		 313 dmas = <&apbdma 21>, <&apbdma 21>;
314 dma-names = "rx", "tx";
3fc2f94e
LD		 315 status = "disabled";
316 };
317
318 i2c@7000c400 {
319 compatible = "nvidia,tegra114-i2c";
320 reg = <0x7000c400 0x100>;
6cecf916 321 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 322 #address-cells = <1>;
323 #size-cells = <0>;
a1c85860 324 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
3fc2f94e 325 clock-names = "div-clk";
3393d422
SW		 326 resets = <&tegra_car 54>;
327 reset-names = "i2c";
034d023f
SW		 328 dmas = <&apbdma 22>, <&apbdma 22>;
329 dma-names = "rx", "tx";
3fc2f94e
LD		 330 status = "disabled";
331 };
332
333 i2c@7000c500 {
334 compatible = "nvidia,tegra114-i2c";
335 reg = <0x7000c500 0x100>;
6cecf916 336 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 337 #address-cells = <1>;
338 #size-cells = <0>;
a1c85860 339 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
3fc2f94e 340 clock-names = "div-clk";
3393d422
SW		 341 resets = <&tegra_car 67>;
342 reset-names = "i2c";
034d023f
SW		 343 dmas = <&apbdma 23>, <&apbdma 23>;
344 dma-names = "rx", "tx";
3fc2f94e
LD		 345 status = "disabled";
346 };
347
348 i2c@7000c700 {
349 compatible = "nvidia,tegra114-i2c";
350 reg = <0x7000c700 0x100>;
6cecf916 351 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 352 #address-cells = <1>;
353 #size-cells = <0>;
a1c85860 354 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
3fc2f94e 355 clock-names = "div-clk";
3393d422
SW		 356 resets = <&tegra_car 103>;
357 reset-names = "i2c";
034d023f
SW		 358 dmas = <&apbdma 26>, <&apbdma 26>;
359 dma-names = "rx", "tx";
3fc2f94e
LD		 360 status = "disabled";
361 };
362
363 i2c@7000d000 {
364 compatible = "nvidia,tegra114-i2c";
365 reg = <0x7000d000 0x100>;
6cecf916 366 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 367 #address-cells = <1>;
368 #size-cells = <0>;
a1c85860 369 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
3fc2f94e 370 clock-names = "div-clk";
3393d422
SW		 371 resets = <&tegra_car 47>;
372 reset-names = "i2c";
034d023f
SW		 373 dmas = <&apbdma 24>, <&apbdma 24>;
374 dma-names = "rx", "tx";
3fc2f94e
LD		 375 status = "disabled";
376 };
377
6ea0297e
LD		 378 spi@7000d400 {
379 compatible = "nvidia,tegra114-spi";
380 reg = <0x7000d400 0x200>;
6cecf916 381 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 382 #address-cells = <1>;
383 #size-cells = <0>;
a1c85860 384 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
6ea0297e 385 clock-names = "spi";
3393d422
SW		 386 resets = <&tegra_car 41>;
387 reset-names = "spi";
034d023f
SW		 388 dmas = <&apbdma 15>, <&apbdma 15>;
389 dma-names = "rx", "tx";
6ea0297e
LD		 390 status = "disabled";
391 };
392
393 spi@7000d600 {
394 compatible = "nvidia,tegra114-spi";
395 reg = <0x7000d600 0x200>;
6cecf916 396 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 397 #address-cells = <1>;
398 #size-cells = <0>;
a1c85860 399 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
6ea0297e 400 clock-names = "spi";
3393d422
SW		 401 resets = <&tegra_car 44>;
402 reset-names = "spi";
034d023f
SW		 403 dmas = <&apbdma 16>, <&apbdma 16>;
404 dma-names = "rx", "tx";
6ea0297e
LD		 405 status = "disabled";
406 };
407
408 spi@7000d800 {
409 compatible = "nvidia,tegra114-spi";
410 reg = <0x7000d800 0x200>;
6cecf916 411 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 412 #address-cells = <1>;
413 #size-cells = <0>;
a1c85860 414 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
6ea0297e 415 clock-names = "spi";
3393d422
SW		 416 resets = <&tegra_car 46>;
417 reset-names = "spi";
034d023f
SW		 418 dmas = <&apbdma 17>, <&apbdma 17>;
419 dma-names = "rx", "tx";
6ea0297e
LD		 420 status = "disabled";
421 };
422
423 spi@7000da00 {
424 compatible = "nvidia,tegra114-spi";
425 reg = <0x7000da00 0x200>;
6cecf916 426 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 427 #address-cells = <1>;
428 #size-cells = <0>;
a1c85860 429 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
6ea0297e 430 clock-names = "spi";
3393d422
SW		 431 resets = <&tegra_car 68>;
432 reset-names = "spi";
034d023f
SW		 433 dmas = <&apbdma 18>, <&apbdma 18>;
434 dma-names = "rx", "tx";
6ea0297e
LD		 435 status = "disabled";
436 };
437
438 spi@7000dc00 {
439 compatible = "nvidia,tegra114-spi";
440 reg = <0x7000dc00 0x200>;
6cecf916 441 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 442 #address-cells = <1>;
443 #size-cells = <0>;
a1c85860 444 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
6ea0297e 445 clock-names = "spi";
3393d422
SW		 446 resets = <&tegra_car 104>;
447 reset-names = "spi";
034d023f
SW		 448 dmas = <&apbdma 27>, <&apbdma 27>;
449 dma-names = "rx", "tx";
6ea0297e
LD		 450 status = "disabled";
451 };
452
453 spi@7000de00 {
454 compatible = "nvidia,tegra114-spi";
455 reg = <0x7000de00 0x200>;
6cecf916 456 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 457 #address-cells = <1>;
458 #size-cells = <0>;
a1c85860 459 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
6ea0297e 460 clock-names = "spi";
3393d422
SW		 461 resets = <&tegra_car 105>;
462 reset-names = "spi";
034d023f
SW		 463 dmas = <&apbdma 28>, <&apbdma 28>;
464 dma-names = "rx", "tx";
6ea0297e
LD		 465 status = "disabled";
466 };
467
58ecb23f 468 rtc@7000e000 {
18a4df70
HD		 469 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
470 reg = <0x7000e000 0x100>;
6cecf916 471 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 472 clocks = <&tegra_car TEGRA114_CLK_RTC>;
18a4df70
HD		 473 };
474
58ecb23f 475 kbc@7000e200 {
cd467b7d
LD		 476 compatible = "nvidia,tegra114-kbc";
477 reg = <0x7000e200 0x100>;
6cecf916 478 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 479 clocks = <&tegra_car TEGRA114_CLK_KBC>;
3393d422
SW		 480 resets = <&tegra_car 36>;
481 reset-names = "kbc";
cd467b7d
LD		 482 status = "disabled";
483 };
484
58ecb23f 485 pmc@7000e400 {
2b84e53b 486 compatible = "nvidia,tegra114-pmc";
18a4df70 487 reg = <0x7000e400 0x400>;
a1c85860 488 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
7021d122 489 clock-names = "pclk", "clk32k_in";
18a4df70
HD		 490 };
491
155dfc7b
PDS		 492 fuse@7000f800 {
493 compatible = "nvidia,tegra114-efuse";
494 reg = <0x7000f800 0x400>;
495 clocks = <&tegra_car TEGRA114_CLK_FUSE>;
496 clock-names = "fuse";
497 resets = <&tegra_car 39>;
498 reset-names = "fuse";
499 };
500
58ecb23f 501 iommu@70019010 {
2da13965 502 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
4cca9593
HD		 503 reg = <0x70019010 0x02c
504 0x700191f0 0x010
505 0x70019228 0x074>;
2da13965
HD		 506 nvidia,#asids = <4>;
507 dma-window = <0 0x40000000>;
508 nvidia,swgroups = <0x18659fe>;
509 nvidia,ahb = <&ahb>;
510 };
511
58ecb23f 512 ahub@70080000 {
15e5c647
SW		 513 compatible = "nvidia,tegra114-ahub";
514 reg = <0x70080000 0x200>,
515 <0x70080200 0x100>,
516 <0x70081000 0x200>;
517 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
15e5c647 518 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
2bd541ff
SW		 519 <&tegra_car TEGRA114_CLK_APBIF>;
520 clock-names = "d_audio", "apbif";
3393d422
SW		 521 resets = <&tegra_car 106>, /* d_audio */
522 <&tegra_car 107>, /* apbif */
523 <&tegra_car 30>, /* i2s0 */
524 <&tegra_car 11>, /* i2s1 */
525 <&tegra_car 18>, /* i2s2 */
526 <&tegra_car 101>, /* i2s3 */
527 <&tegra_car 102>, /* i2s4 */
528 <&tegra_car 108>, /* dam0 */
529 <&tegra_car 109>, /* dam1 */
530 <&tegra_car 110>, /* dam2 */
531 <&tegra_car 10>, /* spdif */
532 <&tegra_car 153>, /* amx */
533 <&tegra_car 154>; /* adx */
534 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
535 "i2s3", "i2s4", "dam0", "dam1", "dam2",
536 "spdif", "amx", "adx";
034d023f
SW		 537 dmas = <&apbdma 1>, <&apbdma 1>,
538 <&apbdma 2>, <&apbdma 2>,
539 <&apbdma 3>, <&apbdma 3>,
540 <&apbdma 4>, <&apbdma 4>,
541 <&apbdma 6>, <&apbdma 6>,
542 <&apbdma 7>, <&apbdma 7>,
543 <&apbdma 12>, <&apbdma 12>,
544 <&apbdma 13>, <&apbdma 13>,
545 <&apbdma 14>, <&apbdma 14>,
546 <&apbdma 29>, <&apbdma 29>;
547 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
548 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
549 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
550 "rx9", "tx9";
15e5c647
SW		 551 ranges;
552 #address-cells = <1>;
553 #size-cells = <1>;
554
555 tegra_i2s0: i2s@70080300 {
556 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
557 reg = <0x70080300 0x100>;
558 nvidia,ahub-cif-ids = <4 4>;
559 clocks = <&tegra_car TEGRA114_CLK_I2S0>;
3393d422
SW		 560 resets = <&tegra_car 30>;
561 reset-names = "i2s";
15e5c647
SW		 562 status = "disabled";
563 };
564
565 tegra_i2s1: i2s@70080400 {
566 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
567 reg = <0x70080400 0x100>;
568 nvidia,ahub-cif-ids = <5 5>;
569 clocks = <&tegra_car TEGRA114_CLK_I2S1>;
3393d422
SW		 570 resets = <&tegra_car 11>;
571 reset-names = "i2s";
15e5c647
SW		 572 status = "disabled";
573 };
574
575 tegra_i2s2: i2s@70080500 {
576 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
577 reg = <0x70080500 0x100>;
578 nvidia,ahub-cif-ids = <6 6>;
579 clocks = <&tegra_car TEGRA114_CLK_I2S2>;
3393d422
SW		 580 resets = <&tegra_car 18>;
581 reset-names = "i2s";
15e5c647
SW		 582 status = "disabled";
583 };
584
585 tegra_i2s3: i2s@70080600 {
586 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
587 reg = <0x70080600 0x100>;
588 nvidia,ahub-cif-ids = <7 7>;
589 clocks = <&tegra_car TEGRA114_CLK_I2S3>;
3393d422
SW		 590 resets = <&tegra_car 101>;
591 reset-names = "i2s";
15e5c647
SW		 592 status = "disabled";
593 };
594
595 tegra_i2s4: i2s@70080700 {
596 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
597 reg = <0x70080700 0x100>;
598 nvidia,ahub-cif-ids = <8 8>;
599 clocks = <&tegra_car TEGRA114_CLK_I2S4>;
3393d422
SW		 600 resets = <&tegra_car 102>;
601 reset-names = "i2s";
15e5c647
SW		 602 status = "disabled";
603 };
604 };
605
e3d04d17
TR		 606 mipi: mipi@700e3000 {
607 compatible = "nvidia,tegra114-mipi";
608 reg = <0x700e3000 0x100>;
609 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
610 #nvidia,mipi-calibrate-cells = <1>;
611 };
612
933d87a5
PR		 613 sdhci@78000000 {
614 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
615 reg = <0x78000000 0x200>;
6cecf916 616 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 617 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
3393d422
SW		 618 resets = <&tegra_car 14>;
619 reset-names = "sdhci";
e2b6d77e 620 status = "disabled";
933d87a5
PR		 621 };
622
623 sdhci@78000200 {
624 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
625 reg = <0x78000200 0x200>;
6cecf916 626 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 627 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
3393d422
SW		 628 resets = <&tegra_car 9>;
629 reset-names = "sdhci";
e2b6d77e 630 status = "disabled";
933d87a5
PR		 631 };
632
633 sdhci@78000400 {
634 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
635 reg = <0x78000400 0x200>;
6cecf916 636 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 637 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
3393d422
SW		 638 resets = <&tegra_car 69>;
639 reset-names = "sdhci";
e2b6d77e 640 status = "disabled";
933d87a5
PR		 641 };
642
643 sdhci@78000600 {
644 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
645 reg = <0x78000600 0x200>;
6cecf916 646 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 647 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
3393d422
SW		 648 resets = <&tegra_car 15>;
649 reset-names = "sdhci";
e2b6d77e 650 status = "disabled";
933d87a5
PR		 651 };
652
328dc0ec
MP		 653 usb@7d000000 {
654 compatible = "nvidia,tegra30-ehci", "usb-ehci";
655 reg = <0x7d000000 0x4000>;
656 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
657 phy_type = "utmi";
658 clocks = <&tegra_car TEGRA114_CLK_USBD>;
3393d422
SW		 659 resets = <&tegra_car 22>;
660 reset-names = "usb";
328dc0ec
MP		 661 nvidia,phy = <&phy1>;
662 status = "disabled";
663 };
664
665 phy1: usb-phy@7d000000 {
666 compatible = "nvidia,tegra30-usb-phy";
667 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
668 phy_type = "utmi";
669 clocks = <&tegra_car TEGRA114_CLK_USBD>,
670 <&tegra_car TEGRA114_CLK_PLL_U>,
671 <&tegra_car TEGRA114_CLK_USBD>;
672 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 673 resets = <&tegra_car 22>, <&tegra_car 22>;
674 reset-names = "usb", "utmi-pads";
328dc0ec
MP		 675 nvidia,hssync-start-delay = <0>;
676 nvidia,idle-wait-delay = <17>;
677 nvidia,elastic-limit = <16>;
678 nvidia,term-range-adj = <6>;
679 nvidia,xcvr-setup = <9>;
680 nvidia,xcvr-lsfslew = <0>;
681 nvidia,xcvr-lsrslew = <3>;
682 nvidia,hssquelch-level = <2>;
683 nvidia,hsdiscon-level = <5>;
684 nvidia,xcvr-hsslew = <12>;
308efde2 685 nvidia,has-utmi-pad-registers;
328dc0ec
MP		 686 status = "disabled";
687 };
688
689 usb@7d008000 {
690 compatible = "nvidia,tegra30-ehci", "usb-ehci";
691 reg = <0x7d008000 0x4000>;
692 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
693 phy_type = "utmi";
694 clocks = <&tegra_car TEGRA114_CLK_USB3>;
3393d422
SW		 695 resets = <&tegra_car 59>;
696 reset-names = "usb";
328dc0ec
MP		 697 nvidia,phy = <&phy3>;
698 status = "disabled";
699 };
700
701 phy3: usb-phy@7d008000 {
702 compatible = "nvidia,tegra30-usb-phy";
703 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
704 phy_type = "utmi";
705 clocks = <&tegra_car TEGRA114_CLK_USB3>,
706 <&tegra_car TEGRA114_CLK_PLL_U>,
707 <&tegra_car TEGRA114_CLK_USBD>;
708 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 709 resets = <&tegra_car 59>, <&tegra_car 22>;
710 reset-names = "usb", "utmi-pads";
328dc0ec
MP		 711 nvidia,hssync-start-delay = <0>;
712 nvidia,idle-wait-delay = <17>;
713 nvidia,elastic-limit = <16>;
714 nvidia,term-range-adj = <6>;
715 nvidia,xcvr-setup = <9>;
716 nvidia,xcvr-lsfslew = <0>;
717 nvidia,xcvr-lsrslew = <3>;
718 nvidia,hssquelch-level = <2>;
719 nvidia,hsdiscon-level = <5>;
720 nvidia,xcvr-hsslew = <12>;
721 status = "disabled";
722 };
723
18a4df70
HD		 724 cpus {
725 #address-cells = <1>;
726 #size-cells = <0>;
727
728 cpu@0 {
729 device_type = "cpu";
730 compatible = "arm,cortex-a15";
731 reg = <0>;
732 };
733
734 cpu@1 {
735 device_type = "cpu";
736 compatible = "arm,cortex-a15";
737 reg = <1>;
738 };
739
740 cpu@2 {
741 device_type = "cpu";
742 compatible = "arm,cortex-a15";
743 reg = <2>;
744 };
745
746 cpu@3 {
747 device_type = "cpu";
748 compatible = "arm,cortex-a15";
749 reg = <3>;
750 };
751 };
752
753 timer {
754 compatible = "arm,armv7-timer";
6cecf916
SW		 755 interrupts =
756 <GIC_PPI 13
757 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
758 <GIC_PPI 14
759 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
760 <GIC_PPI 11
761 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
762 <GIC_PPI 10
763 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
18a4df70
HD		 764 };
765};
ubuntu-zesty-kernel mirror