[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / tegra114.dtsi

#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra114";
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uarta;
		serial1 = &uartb;
		serial2 = &uartc;
		serial3 = &uartd;
	};

	gic: interrupt-controller {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x50041000 0x1000>,
		      <0x50042000 0x1000>,
		      <0x50044000 0x2000>,
		      <0x50046000 0x2000>;
		interrupts = <GIC_PPI 9
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
		reg = <0x60005000 0x400>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car 5>;
	};

	tegra_car: clock {
		compatible = "nvidia,tegra114-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
	};

	apbdma: dma {
		compatible = "nvidia,tegra114-apbdma";
		reg = <0x6000a000 0x1400>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car 34>;
	};

	ahb: ahb {
		compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
		reg = <0x6000c004 0x14c>;
	};

	gpio: gpio {
		compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pinmux: pinmux {
		compatible = "nvidia,tegra114-pinmux";
		reg = <0x70000868 0x148		/* Pad control registers */
		       0x70003000 0x40c>;	/* Mux registers */
	};

	/*
	 * There are two serial driver i.e. 8250 based simple serial
	 * driver and APB DMA based serial driver for higher baudrate
	 * and performace. To enable the 8250 based driver, the compatible
	 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
	 * the APB DMA based serial driver, the comptible is
	 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
	 */
	uarta: serial@70006000 {
		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 8>;
		status = "disabled";
		clocks = <&tegra_car 6>;
	};

	uartb: serial@70006040 {
		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 9>;
		status = "disabled";
		clocks = <&tegra_car 192>;
	};

	uartc: serial@70006200 {
		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 10>;
		status = "disabled";
		clocks = <&tegra_car 55>;
	};

	uartd: serial@70006300 {
		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 19>;
		status = "disabled";
		clocks = <&tegra_car 65>;
	};

	pwm: pwm {
		compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
		reg = <0x7000a000 0x100>;
		#pwm-cells = <2>;
		clocks = <&tegra_car 17>;
		status = "disabled";
	};

	i2c@7000c000 {
		compatible = "nvidia,tegra114-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 12>;
		clock-names = "div-clk";
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra114-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 54>;
		clock-names = "div-clk";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra114-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 67>;
		clock-names = "div-clk";
		status = "disabled";
	};

	i2c@7000c700 {
		compatible = "nvidia,tegra114-i2c";
		reg = <0x7000c700 0x100>;
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 103>;
		clock-names = "div-clk";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra114-i2c";
		reg = <0x7000d000 0x100>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 47>;
		clock-names = "div-clk";
		status = "disabled";
	};

	spi@7000d400 {
		compatible = "nvidia,tegra114-spi";
		reg = <0x7000d400 0x200>;
		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 15>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 41>;
		clock-names = "spi";
		status = "disabled";
	};

	spi@7000d600 {
		compatible = "nvidia,tegra114-spi";
		reg = <0x7000d600 0x200>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 16>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 44>;
		clock-names = "spi";
		status = "disabled";
	};

	spi@7000d800 {
		compatible = "nvidia,tegra114-spi";
		reg = <0x7000d800 0x200>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 17>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 46>;
		clock-names = "spi";
		status = "disabled";
	};

	spi@7000da00 {
		compatible = "nvidia,tegra114-spi";
		reg = <0x7000da00 0x200>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 18>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 68>;
		clock-names = "spi";
		status = "disabled";
	};

	spi@7000dc00 {
		compatible = "nvidia,tegra114-spi";
		reg = <0x7000dc00 0x200>;
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 27>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 104>;
		clock-names = "spi";
		status = "disabled";
	};

	spi@7000de00 {
		compatible = "nvidia,tegra114-spi";
		reg = <0x7000de00 0x200>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 28>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 105>;
		clock-names = "spi";
		status = "disabled";
	};

	rtc {
		compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
		reg = <0x7000e000 0x100>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car 4>;
	};

	kbc {
		compatible = "nvidia,tegra114-kbc";
		reg = <0x7000e200 0x100>;
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car 36>;
		status = "disabled";
	};

	pmc {
		compatible = "nvidia,tegra114-pmc";
		reg = <0x7000e400 0x400>;
		clocks = <&tegra_car 261>, <&clk32k_in>;
		clock-names = "pclk", "clk32k_in";
	};

	iommu {
		compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
		reg = <0x7000f010 0x02c
		       0x7000f1f0 0x010
		       0x7000f228 0x074>;
		nvidia,#asids = <4>;
		dma-window = <0 0x40000000>;
		nvidia,swgroups = <0x18659fe>;
		nvidia,ahb = <&ahb>;
	};

	sdhci@78000000 {
		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
		reg = <0x78000000 0x200>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car 14>;
		status = "disable";
	};

	sdhci@78000200 {
		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
		reg = <0x78000200 0x200>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car 9>;
		status = "disable";
	};

	sdhci@78000400 {
		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
		reg = <0x78000400 0x200>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car 69>;
		status = "disable";
	};

	sdhci@78000600 {
		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
		reg = <0x78000600 0x200>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car 15>;
		status = "disable";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <3>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts =
			<GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};
};
Commit	Line	Data
3325f1bc	1	#include <dt-bindings/gpio/tegra-gpio.h>
6cecf916	2	#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc	3
1bd0bd49	4	#include "skeleton.dtsi"
18a4df70 HD	5
	6	/ {
	7	compatible = "nvidia,tegra114";
	8	interrupt-parent = <&gic>;
	9
0fb22096 LD	10	aliases {
	11	serial0 = &uarta;
	12	serial1 = &uartb;
	13	serial2 = &uartc;
	14	serial3 = &uartd;
	15	};
	16
18a4df70 HD	17	gic: interrupt-controller {
	18	compatible = "arm,cortex-a15-gic";
	19	#interrupt-cells = <3>;
	20	interrupt-controller;
	21	reg = <0x50041000 0x1000>,
	22	<0x50042000 0x1000>,
	23	<0x50044000 0x2000>,
	24	<0x50046000 0x2000>;
6cecf916 SW	25	interrupts = <GIC_PPI 9
6cecf916 SW	26	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
18a4df70 HD	27	};
	28
	29	timer@60005000 {
	30	compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
	31	reg = <0x60005000 0x400>;
6cecf916 SW	32	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	33	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	34	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	35	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	36	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	37	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
672d889c	38	clocks = <&tegra_car 5>;
18a4df70 HD	39	};
	40
	41	tegra_car: clock {
672d889c	42	compatible = "nvidia,tegra114-car";
18a4df70 HD	43	reg = <0x60006000 0x1000>;
	44	#clock-cells = <1>;
	45	};
	46
c5d9da4a LD	47	apbdma: dma {
	48	compatible = "nvidia,tegra114-apbdma";
	49	reg = <0x6000a000 0x1400>;
6cecf916 SW	50	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	51	<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	52	<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
	53	<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	54	<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	55	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	56	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	57	<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
	58	<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	59	<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	60	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	61	<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	62	<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	63	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	64	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	65	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
	66	<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
	67	<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
	68	<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
	69	<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	70	<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
	71	<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
	72	<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
	73	<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
	74	<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	75	<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	76	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
	77	<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
	78	<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
	79	<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
	80	<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	81	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
c5d9da4a LD	82	clocks = <&tegra_car 34>;
	83	};
	84
0dfe42ed HD	85	ahb: ahb {
	86	compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
	87	reg = <0x6000c004 0x14c>;
	88	};
	89
b16f9183 LD	90	gpio: gpio {
	91	compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
	92	reg = <0x6000d000 0x1000>;
6cecf916 SW	93	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	94	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	95	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	96	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	97	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	98	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	99	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
	100	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
b16f9183 LD	101	#gpio-cells = <2>;
	102	gpio-controller;
	103	#interrupt-cells = <2>;
	104	interrupt-controller;
	105	};
	106
031b77af LD	107	pinmux: pinmux {
	108	compatible = "nvidia,tegra114-pinmux";
	109	reg = <0x70000868 0x148 /* Pad control registers */
	110	0x70003000 0x40c>; /* Mux registers */
	111	};
	112
0fb22096 LD	113	/*
	114	* There are two serial driver i.e. 8250 based simple serial
	115	* driver and APB DMA based serial driver for higher baudrate
	116	* and performace. To enable the 8250 based driver, the compatible
	117	* is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
	118	* the APB DMA based serial driver, the comptible is
	119	* "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
	120	*/
	121	uarta: serial@70006000 {
18a4df70 HD	122	compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
	123	reg = <0x70006000 0x40>;
	124	reg-shift = <2>;
6cecf916	125	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0fb22096	126	nvidia,dma-request-selector = <&apbdma 8>;
18a4df70	127	status = "disabled";
672d889c	128	clocks = <&tegra_car 6>;
18a4df70 HD	129	};
18a4df70 HD	130
0fb22096	131	uartb: serial@70006040 {
18a4df70 HD	132	compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
	133	reg = <0x70006040 0x40>;
	134	reg-shift = <2>;
6cecf916	135	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0fb22096	136	nvidia,dma-request-selector = <&apbdma 9>;
18a4df70	137	status = "disabled";
672d889c	138	clocks = <&tegra_car 192>;
18a4df70 HD	139	};
18a4df70 HD	140
0fb22096	141	uartc: serial@70006200 {
18a4df70 HD	142	compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
	143	reg = <0x70006200 0x100>;
	144	reg-shift = <2>;
6cecf916	145	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0fb22096	146	nvidia,dma-request-selector = <&apbdma 10>;
18a4df70	147	status = "disabled";
672d889c	148	clocks = <&tegra_car 55>;
18a4df70 HD	149	};
18a4df70 HD	150
0fb22096	151	uartd: serial@70006300 {
18a4df70 HD	152	compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
	153	reg = <0x70006300 0x100>;
	154	reg-shift = <2>;
6cecf916	155	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0fb22096	156	nvidia,dma-request-selector = <&apbdma 19>;
18a4df70	157	status = "disabled";
672d889c	158	clocks = <&tegra_car 65>;
18a4df70 HD	159	};
18a4df70 HD	160
6c716db5 AC	161	pwm: pwm {
	162	compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
	163	reg = <0x7000a000 0x100>;
	164	#pwm-cells = <2>;
	165	clocks = <&tegra_car 17>;
	166	status = "disabled";
	167	};
	168
3fc2f94e LD	169	i2c@7000c000 {
	170	compatible = "nvidia,tegra114-i2c";
	171	reg = <0x7000c000 0x100>;
6cecf916	172	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e LD	173	#address-cells = <1>;
	174	#size-cells = <0>;
	175	clocks = <&tegra_car 12>;
	176	clock-names = "div-clk";
	177	status = "disabled";
	178	};
	179
	180	i2c@7000c400 {
	181	compatible = "nvidia,tegra114-i2c";
	182	reg = <0x7000c400 0x100>;
6cecf916	183	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e LD	184	#address-cells = <1>;
	185	#size-cells = <0>;
	186	clocks = <&tegra_car 54>;
	187	clock-names = "div-clk";
	188	status = "disabled";
	189	};
	190
	191	i2c@7000c500 {
	192	compatible = "nvidia,tegra114-i2c";
	193	reg = <0x7000c500 0x100>;
6cecf916	194	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e LD	195	#address-cells = <1>;
	196	#size-cells = <0>;
	197	clocks = <&tegra_car 67>;
	198	clock-names = "div-clk";
	199	status = "disabled";
	200	};
	201
	202	i2c@7000c700 {
	203	compatible = "nvidia,tegra114-i2c";
	204	reg = <0x7000c700 0x100>;
6cecf916	205	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e LD	206	#address-cells = <1>;
	207	#size-cells = <0>;
	208	clocks = <&tegra_car 103>;
	209	clock-names = "div-clk";
	210	status = "disabled";
	211	};
	212
	213	i2c@7000d000 {
	214	compatible = "nvidia,tegra114-i2c";
	215	reg = <0x7000d000 0x100>;
6cecf916	216	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e LD	217	#address-cells = <1>;
	218	#size-cells = <0>;
	219	clocks = <&tegra_car 47>;
	220	clock-names = "div-clk";
	221	status = "disabled";
	222	};
	223
6ea0297e LD	224	spi@7000d400 {
	225	compatible = "nvidia,tegra114-spi";
	226	reg = <0x7000d400 0x200>;
6cecf916	227	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e LD	228	nvidia,dma-request-selector = <&apbdma 15>;
	229	#address-cells = <1>;
	230	#size-cells = <0>;
	231	clocks = <&tegra_car 41>;
	232	clock-names = "spi";
	233	status = "disabled";
	234	};
	235
	236	spi@7000d600 {
	237	compatible = "nvidia,tegra114-spi";
	238	reg = <0x7000d600 0x200>;
6cecf916	239	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e LD	240	nvidia,dma-request-selector = <&apbdma 16>;
	241	#address-cells = <1>;
	242	#size-cells = <0>;
	243	clocks = <&tegra_car 44>;
	244	clock-names = "spi";
	245	status = "disabled";
	246	};
	247
	248	spi@7000d800 {
	249	compatible = "nvidia,tegra114-spi";
	250	reg = <0x7000d800 0x200>;
6cecf916	251	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e LD	252	nvidia,dma-request-selector = <&apbdma 17>;
	253	#address-cells = <1>;
	254	#size-cells = <0>;
	255	clocks = <&tegra_car 46>;
	256	clock-names = "spi";
	257	status = "disabled";
	258	};
	259
	260	spi@7000da00 {
	261	compatible = "nvidia,tegra114-spi";
	262	reg = <0x7000da00 0x200>;
6cecf916	263	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e LD	264	nvidia,dma-request-selector = <&apbdma 18>;
	265	#address-cells = <1>;
	266	#size-cells = <0>;
	267	clocks = <&tegra_car 68>;
	268	clock-names = "spi";
	269	status = "disabled";
	270	};
	271
	272	spi@7000dc00 {
	273	compatible = "nvidia,tegra114-spi";
	274	reg = <0x7000dc00 0x200>;
6cecf916	275	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e LD	276	nvidia,dma-request-selector = <&apbdma 27>;
	277	#address-cells = <1>;
	278	#size-cells = <0>;
	279	clocks = <&tegra_car 104>;
	280	clock-names = "spi";
	281	status = "disabled";
	282	};
	283
	284	spi@7000de00 {
	285	compatible = "nvidia,tegra114-spi";
	286	reg = <0x7000de00 0x200>;
6cecf916	287	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e LD	288	nvidia,dma-request-selector = <&apbdma 28>;
	289	#address-cells = <1>;
	290	#size-cells = <0>;
	291	clocks = <&tegra_car 105>;
	292	clock-names = "spi";
	293	status = "disabled";
	294	};
	295
18a4df70 HD	296	rtc {
	297	compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
	298	reg = <0x7000e000 0x100>;
6cecf916	299	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
672d889c	300	clocks = <&tegra_car 4>;
18a4df70 HD	301	};
18a4df70 HD	302
cd467b7d LD	303	kbc {
	304	compatible = "nvidia,tegra114-kbc";
	305	reg = <0x7000e200 0x100>;
6cecf916	306	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
cd467b7d LD	307	clocks = <&tegra_car 36>;
	308	status = "disabled";
	309	};
	310
18a4df70	311	pmc {
2b84e53b	312	compatible = "nvidia,tegra114-pmc";
18a4df70	313	reg = <0x7000e400 0x400>;
7021d122 JL	314	clocks = <&tegra_car 261>, <&clk32k_in>;
7021d122 JL	315	clock-names = "pclk", "clk32k_in";
18a4df70 HD	316	};
18a4df70 HD	317
2da13965 HD	318	iommu {
	319	compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
	320	reg = <0x7000f010 0x02c
	321	0x7000f1f0 0x010
	322	0x7000f228 0x074>;
	323	nvidia,#asids = <4>;
	324	dma-window = <0 0x40000000>;
	325	nvidia,swgroups = <0x18659fe>;
	326	nvidia,ahb = <&ahb>;
	327	};
	328
933d87a5 PR	329	sdhci@78000000 {
	330	compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
	331	reg = <0x78000000 0x200>;
6cecf916	332	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
933d87a5 PR	333	clocks = <&tegra_car 14>;
	334	status = "disable";
	335	};
	336
	337	sdhci@78000200 {
	338	compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
	339	reg = <0x78000200 0x200>;
6cecf916	340	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
933d87a5 PR	341	clocks = <&tegra_car 9>;
	342	status = "disable";
	343	};
	344
	345	sdhci@78000400 {
	346	compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
	347	reg = <0x78000400 0x200>;
6cecf916	348	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
933d87a5 PR	349	clocks = <&tegra_car 69>;
	350	status = "disable";
	351	};
	352
	353	sdhci@78000600 {
	354	compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
	355	reg = <0x78000600 0x200>;
6cecf916	356	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
933d87a5 PR	357	clocks = <&tegra_car 15>;
	358	status = "disable";
	359	};
	360
18a4df70 HD	361	cpus {
	362	#address-cells = <1>;
	363	#size-cells = <0>;
	364
	365	cpu@0 {
	366	device_type = "cpu";
	367	compatible = "arm,cortex-a15";
	368	reg = <0>;
	369	};
	370
	371	cpu@1 {
	372	device_type = "cpu";
	373	compatible = "arm,cortex-a15";
	374	reg = <1>;
	375	};
	376
	377	cpu@2 {
	378	device_type = "cpu";
	379	compatible = "arm,cortex-a15";
	380	reg = <2>;
	381	};
	382
	383	cpu@3 {
	384	device_type = "cpu";
	385	compatible = "arm,cortex-a15";
	386	reg = <3>;
	387	};
	388	};
	389
	390	timer {
	391	compatible = "arm,armv7-timer";
6cecf916 SW	392	interrupts =
	393	<GIC_PPI 13
	394	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	395	<GIC_PPI 14
	396	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	397	<GIC_PPI 11
	398	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	399	<GIC_PPI 10
	400	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
18a4df70 HD	401	};
18a4df70 HD	402	};