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Merge tag 'mvebu-fixes-4.17-2' of git://git.infradead.org/linux-mvebu into fixes
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / tegra124-apalis-v1.2.dtsi
CommitLineData
4957a2f1
MZ		 1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2016-2018 Toradex AG
4 */
5
6#include "tegra124.dtsi"
7#include "tegra124-apalis-emc.dtsi"
8
9/*
10 * Toradex Apalis TK1 Module Device Tree
11 * Compatible for Revisions 2GB: V1.2A
12 */
13/ {
14 model = "Toradex Apalis TK1";
15 compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1",
16 "nvidia,tegra124";
17
18 memory {
19 reg = <0x0 0x80000000 0x0 0x80000000>;
20 };
21
22 pcie@1003000 {
23 status = "okay";
24 avddio-pex-supply = <&vdd_1v05>;
25 avdd-pex-pll-supply = <&vdd_1v05>;
26 avdd-pll-erefe-supply = <&avdd_1v05>;
27 dvddio-pex-supply = <&vdd_1v05>;
28 hvdd-pex-pll-e-supply = <&reg_3v3>;
29 hvdd-pex-supply = <&reg_3v3>;
30 vddio-pex-ctl-supply = <&reg_3v3>;
31
32 /* Apalis PCIe (additional lane Apalis type specific) */
33 pci@1,0 {
34 /* PCIE1_RX/TX and TS_DIFF1/2 */
35 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
36 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
37 phy-names = "pcie-0", "pcie-1";
38 };
39
40 /* I210 Gigabit Ethernet Controller (On-module) */
41 pci@2,0 {
42 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
43 phy-names = "pcie-0";
44 status = "okay";
45 };
46 };
47
48 host1x@50000000 {
49 hdmi@54280000 {
50 pll-supply = <&reg_1v05_avdd_hdmi_pll>;
51 vdd-supply = <&reg_3v3_avdd_hdmi>;
52 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
53 nvidia,hpd-gpio =
54 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
55 };
56 };
57
58 gpu@0,57000000 {
59 /*
60 * Node left disabled on purpose - the bootloader will enable
61 * it after having set the VPR up
62 */
63 vdd-supply = <&vdd_gpu>;
64 };
65
66 pinmux: pinmux@70000868 {
67 pinctrl-names = "default";
68 pinctrl-0 = <&state_default>;
69
70 state_default: pinmux {
71 /* Analogue Audio (On-module) */
72 dap3_fs_pp0 {
73 nvidia,pins = "dap3_fs_pp0";
74 nvidia,function = "i2s2";
75 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
76 nvidia,tristate = <TEGRA_PIN_DISABLE>;
77 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
78 };
79 dap3_din_pp1 {
80 nvidia,pins = "dap3_din_pp1";
81 nvidia,function = "i2s2";
82 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
83 nvidia,tristate = <TEGRA_PIN_ENABLE>;
84 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
85 };
86 dap3_dout_pp2 {
87 nvidia,pins = "dap3_dout_pp2";
88 nvidia,function = "i2s2";
89 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
90 nvidia,tristate = <TEGRA_PIN_DISABLE>;
91 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
92 };
93 dap3_sclk_pp3 {
94 nvidia,pins = "dap3_sclk_pp3";
95 nvidia,function = "i2s2";
96 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
97 nvidia,tristate = <TEGRA_PIN_DISABLE>;
98 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
99 };
100 dap_mclk1_pw4 {
101 nvidia,pins = "dap_mclk1_pw4";
102 nvidia,function = "extperiph1";
103 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
104 nvidia,tristate = <TEGRA_PIN_DISABLE>;
105 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
106 };
107
108 /* Apalis BKL1_ON */
109 pbb5 {
110 nvidia,pins = "pbb5";
111 nvidia,function = "vgp5";
112 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
113 nvidia,tristate = <TEGRA_PIN_DISABLE>;
114 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
115 };
116
117 /* Apalis BKL1_PWM */
118 pu6 {
119 nvidia,pins = "pu6";
120 nvidia,function = "pwm3";
121 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
122 nvidia,tristate = <TEGRA_PIN_DISABLE>;
123 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
124 };
125
126 /* Apalis CAM1_MCLK */
127 cam_mclk_pcc0 {
128 nvidia,pins = "cam_mclk_pcc0";
129 nvidia,function = "vi_alt3";
130 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
131 nvidia,tristate = <TEGRA_PIN_DISABLE>;
132 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
133 };
134
135 /* Apalis Digital Audio */
136 dap2_fs_pa2 {
137 nvidia,pins = "dap2_fs_pa2";
138 nvidia,function = "hda";
139 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
140 nvidia,tristate = <TEGRA_PIN_DISABLE>;
141 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
142 };
143 dap2_sclk_pa3 {
144 nvidia,pins = "dap2_sclk_pa3";
145 nvidia,function = "hda";
146 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
147 nvidia,tristate = <TEGRA_PIN_DISABLE>;
148 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
149 };
150 dap2_din_pa4 {
151 nvidia,pins = "dap2_din_pa4";
152 nvidia,function = "hda";
153 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
154 nvidia,tristate = <TEGRA_PIN_ENABLE>;
155 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
156 };
157 dap2_dout_pa5 {
158 nvidia,pins = "dap2_dout_pa5";
159 nvidia,function = "hda";
160 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
161 nvidia,tristate = <TEGRA_PIN_DISABLE>;
162 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
163 };
164 pbb3 { /* DAP1_RESET */
165 nvidia,pins = "pbb3";
166 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167 nvidia,tristate = <TEGRA_PIN_DISABLE>;
168 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
169 };
170 clk3_out_pee0 {
171 nvidia,pins = "clk3_out_pee0";
172 nvidia,function = "extperiph3";
173 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
174 nvidia,tristate = <TEGRA_PIN_DISABLE>;
175 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
176 };
177
178 /* Apalis GPIO */
179 usb_vbus_en0_pn4 {
180 nvidia,pins = "usb_vbus_en0_pn4";
181 nvidia,function = "rsvd2";
182 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
183 nvidia,tristate = <TEGRA_PIN_DISABLE>;
184 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
185 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
186 };
187 usb_vbus_en1_pn5 {
188 nvidia,pins = "usb_vbus_en1_pn5";
189 nvidia,function = "rsvd2";
190 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
191 nvidia,tristate = <TEGRA_PIN_DISABLE>;
192 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
193 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
194 };
195 pex_l0_rst_n_pdd1 {
196 nvidia,pins = "pex_l0_rst_n_pdd1";
197 nvidia,function = "rsvd2";
198 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
199 nvidia,tristate = <TEGRA_PIN_DISABLE>;
200 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
201 };
202 pex_l0_clkreq_n_pdd2 {
203 nvidia,pins = "pex_l0_clkreq_n_pdd2";
204 nvidia,function = "rsvd2";
205 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
206 nvidia,tristate = <TEGRA_PIN_DISABLE>;
207 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
208 };
209 pex_l1_rst_n_pdd5 {
210 nvidia,pins = "pex_l1_rst_n_pdd5";
211 nvidia,function = "rsvd2";
212 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
213 nvidia,tristate = <TEGRA_PIN_DISABLE>;
214 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
215 };
216 pex_l1_clkreq_n_pdd6 {
217 nvidia,pins = "pex_l1_clkreq_n_pdd6";
218 nvidia,function = "rsvd2";
219 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
220 nvidia,tristate = <TEGRA_PIN_DISABLE>;
221 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
222 };
223 dp_hpd_pff0 {
224 nvidia,pins = "dp_hpd_pff0";
225 nvidia,function = "dp";
226 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
227 nvidia,tristate = <TEGRA_PIN_DISABLE>;
228 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
229 };
230 pff2 {
231 nvidia,pins = "pff2";
232 nvidia,function = "rsvd2";
233 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
234 nvidia,tristate = <TEGRA_PIN_DISABLE>;
235 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
236 };
237 owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
238 nvidia,pins = "owr";
239 nvidia,function = "rsvd2";
240 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
241 nvidia,tristate = <TEGRA_PIN_ENABLE>;
242 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
243 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
244 };
245
246 /* Apalis HDMI1_CEC */
247 hdmi_cec_pee3 {
248 nvidia,pins = "hdmi_cec_pee3";
249 nvidia,function = "cec";
250 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
251 nvidia,tristate = <TEGRA_PIN_DISABLE>;
252 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
253 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
254 };
255
256 /* Apalis HDMI1_HPD */
257 hdmi_int_pn7 {
258 nvidia,pins = "hdmi_int_pn7";
259 nvidia,function = "rsvd1";
260 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
261 nvidia,tristate = <TEGRA_PIN_ENABLE>;
262 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
263 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
264 };
265
266 /* Apalis I2C1 */
267 gen1_i2c_scl_pc4 {
268 nvidia,pins = "gen1_i2c_scl_pc4";
269 nvidia,function = "i2c1";
270 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
271 nvidia,tristate = <TEGRA_PIN_DISABLE>;
272 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
273 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
274 };
275 gen1_i2c_sda_pc5 {
276 nvidia,pins = "gen1_i2c_sda_pc5";
277 nvidia,function = "i2c1";
278 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
279 nvidia,tristate = <TEGRA_PIN_DISABLE>;
280 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
281 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
282 };
283
284 /* Apalis I2C3 (CAM) */
285 cam_i2c_scl_pbb1 {
286 nvidia,pins = "cam_i2c_scl_pbb1";
287 nvidia,function = "i2c3";
288 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
289 nvidia,tristate = <TEGRA_PIN_DISABLE>;
290 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
291 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
292 };
293 cam_i2c_sda_pbb2 {
294 nvidia,pins = "cam_i2c_sda_pbb2";
295 nvidia,function = "i2c3";
296 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
297 nvidia,tristate = <TEGRA_PIN_DISABLE>;
298 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
299 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
300 };
301
302 /* Apalis I2C4 (DDC) */
303 ddc_scl_pv4 {
304 nvidia,pins = "ddc_scl_pv4";
305 nvidia,function = "i2c4";
306 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
307 nvidia,tristate = <TEGRA_PIN_DISABLE>;
308 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
309 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
310 };
311 ddc_sda_pv5 {
312 nvidia,pins = "ddc_sda_pv5";
313 nvidia,function = "i2c4";
314 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
315 nvidia,tristate = <TEGRA_PIN_DISABLE>;
316 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
317 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
318 };
319
320 /* Apalis MMC1 */
321 sdmmc1_cd_n_pv3 { /* CD# GPIO */
322 nvidia,pins = "sdmmc1_wp_n_pv3";
323 nvidia,function = "sdmmc1";
324 nvidia,pull = <TEGRA_PIN_PULL_UP>;
325 nvidia,tristate = <TEGRA_PIN_ENABLE>;
326 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
327 };
328 clk2_out_pw5 { /* D5 GPIO */
329 nvidia,pins = "clk2_out_pw5";
330 nvidia,function = "rsvd2";
331 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
332 nvidia,tristate = <TEGRA_PIN_DISABLE>;
333 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
334 };
335 sdmmc1_dat3_py4 {
336 nvidia,pins = "sdmmc1_dat3_py4";
337 nvidia,function = "sdmmc1";
338 nvidia,pull = <TEGRA_PIN_PULL_UP>;
339 nvidia,tristate = <TEGRA_PIN_DISABLE>;
340 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
341 };
342 sdmmc1_dat2_py5 {
343 nvidia,pins = "sdmmc1_dat2_py5";
344 nvidia,function = "sdmmc1";
345 nvidia,pull = <TEGRA_PIN_PULL_UP>;
346 nvidia,tristate = <TEGRA_PIN_DISABLE>;
347 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
348 };
349 sdmmc1_dat1_py6 {
350 nvidia,pins = "sdmmc1_dat1_py6";
351 nvidia,function = "sdmmc1";
352 nvidia,pull = <TEGRA_PIN_PULL_UP>;
353 nvidia,tristate = <TEGRA_PIN_DISABLE>;
354 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
355 };
356 sdmmc1_dat0_py7 {
357 nvidia,pins = "sdmmc1_dat0_py7";
358 nvidia,function = "sdmmc1";
359 nvidia,pull = <TEGRA_PIN_PULL_UP>;
360 nvidia,tristate = <TEGRA_PIN_DISABLE>;
361 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
362 };
363 sdmmc1_clk_pz0 {
364 nvidia,pins = "sdmmc1_clk_pz0";
365 nvidia,function = "sdmmc1";
366 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
367 nvidia,tristate = <TEGRA_PIN_DISABLE>;
368 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
369 };
370 sdmmc1_cmd_pz1 {
371 nvidia,pins = "sdmmc1_cmd_pz1";
372 nvidia,function = "sdmmc1";
373 nvidia,pull = <TEGRA_PIN_PULL_UP>;
374 nvidia,tristate = <TEGRA_PIN_DISABLE>;
375 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
376 };
377 clk2_req_pcc5 { /* D4 GPIO */
378 nvidia,pins = "clk2_req_pcc5";
379 nvidia,function = "rsvd2";
380 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
381 nvidia,tristate = <TEGRA_PIN_DISABLE>;
382 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
383 };
384 sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */
385 nvidia,pins = "sdmmc3_clk_lb_in_pee5";
386 nvidia,function = "rsvd2";
387 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
388 nvidia,tristate = <TEGRA_PIN_DISABLE>;
389 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
390 };
391 usb_vbus_en2_pff1 { /* D7 GPIO */
392 nvidia,pins = "usb_vbus_en2_pff1";
393 nvidia,function = "rsvd2";
394 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
395 nvidia,tristate = <TEGRA_PIN_DISABLE>;
396 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
397 };
398
399 /* Apalis PWM */
400 ph0 {
401 nvidia,pins = "ph0";
402 nvidia,function = "pwm0";
403 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
404 nvidia,tristate = <TEGRA_PIN_DISABLE>;
405 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
406 };
407 ph1 {
408 nvidia,pins = "ph1";
409 nvidia,function = "pwm1";
410 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
411 nvidia,tristate = <TEGRA_PIN_DISABLE>;
412 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
413 };
414 ph2 {
415 nvidia,pins = "ph2";
416 nvidia,function = "pwm2";
417 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
418 nvidia,tristate = <TEGRA_PIN_DISABLE>;
419 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
420 };
421 /* PWM3 active on pu6 being Apalis BKL1_PWM as well */
422 ph3 {
423 nvidia,pins = "ph3";
424 nvidia,function = "pwm3";
425 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
426 nvidia,tristate = <TEGRA_PIN_DISABLE>;
427 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
428 };
429
430 /* Apalis SATA1_ACT# */
431 dap1_dout_pn2 {
432 nvidia,pins = "dap1_dout_pn2";
433 nvidia,function = "gmi";
434 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
435 nvidia,tristate = <TEGRA_PIN_DISABLE>;
436 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
437 };
438
439 /* Apalis SD1 */
440 sdmmc3_clk_pa6 {
441 nvidia,pins = "sdmmc3_clk_pa6";
442 nvidia,function = "sdmmc3";
443 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
444 nvidia,tristate = <TEGRA_PIN_DISABLE>;
445 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
446 };
447 sdmmc3_cmd_pa7 {
448 nvidia,pins = "sdmmc3_cmd_pa7";
449 nvidia,function = "sdmmc3";
450 nvidia,pull = <TEGRA_PIN_PULL_UP>;
451 nvidia,tristate = <TEGRA_PIN_DISABLE>;
452 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
453 };
454 sdmmc3_dat3_pb4 {
455 nvidia,pins = "sdmmc3_dat3_pb4";
456 nvidia,function = "sdmmc3";
457 nvidia,pull = <TEGRA_PIN_PULL_UP>;
458 nvidia,tristate = <TEGRA_PIN_DISABLE>;
459 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
460 };
461 sdmmc3_dat2_pb5 {
462 nvidia,pins = "sdmmc3_dat2_pb5";
463 nvidia,function = "sdmmc3";
464 nvidia,pull = <TEGRA_PIN_PULL_UP>;
465 nvidia,tristate = <TEGRA_PIN_DISABLE>;
466 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
467 };
468 sdmmc3_dat1_pb6 {
469 nvidia,pins = "sdmmc3_dat1_pb6";
470 nvidia,function = "sdmmc3";
471 nvidia,pull = <TEGRA_PIN_PULL_UP>;
472 nvidia,tristate = <TEGRA_PIN_DISABLE>;
473 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
474 };
475 sdmmc3_dat0_pb7 {
476 nvidia,pins = "sdmmc3_dat0_pb7";
477 nvidia,function = "sdmmc3";
478 nvidia,pull = <TEGRA_PIN_PULL_UP>;
479 nvidia,tristate = <TEGRA_PIN_DISABLE>;
480 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
481 };
482 sdmmc3_cd_n_pv2 { /* CD# GPIO */
483 nvidia,pins = "sdmmc3_cd_n_pv2";
484 nvidia,function = "rsvd3";
485 nvidia,pull = <TEGRA_PIN_PULL_UP>;
486 nvidia,tristate = <TEGRA_PIN_ENABLE>;
487 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
488 };
489
490 /* Apalis SPDIF */
491 spdif_out_pk5 {
492 nvidia,pins = "spdif_out_pk5";
493 nvidia,function = "spdif";
494 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
495 nvidia,tristate = <TEGRA_PIN_DISABLE>;
496 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
497 };
498 spdif_in_pk6 {
499 nvidia,pins = "spdif_in_pk6";
500 nvidia,function = "spdif";
501 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
502 nvidia,tristate = <TEGRA_PIN_ENABLE>;
503 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
504 };
505
506 /* Apalis SPI1 */
507 ulpi_clk_py0 {
508 nvidia,pins = "ulpi_clk_py0";
509 nvidia,function = "spi1";
510 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
511 nvidia,tristate = <TEGRA_PIN_DISABLE>;
512 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
513 };
514 ulpi_dir_py1 {
515 nvidia,pins = "ulpi_dir_py1";
516 nvidia,function = "spi1";
517 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
518 nvidia,tristate = <TEGRA_PIN_ENABLE>;
519 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
520 };
521 ulpi_nxt_py2 {
522 nvidia,pins = "ulpi_nxt_py2";
523 nvidia,function = "spi1";
524 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
525 nvidia,tristate = <TEGRA_PIN_DISABLE>;
526 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
527 };
528 ulpi_stp_py3 {
529 nvidia,pins = "ulpi_stp_py3";
530 nvidia,function = "spi1";
531 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
532 nvidia,tristate = <TEGRA_PIN_DISABLE>;
533 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
534 };
535
536 /* Apalis SPI2 */
537 pg5 {
538 nvidia,pins = "pg5";
539 nvidia,function = "spi4";
540 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
541 nvidia,tristate = <TEGRA_PIN_DISABLE>;
542 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
543 };
544 pg6 {
545 nvidia,pins = "pg6";
546 nvidia,function = "spi4";
547 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
548 nvidia,tristate = <TEGRA_PIN_DISABLE>;
549 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
550 };
551 pg7 {
552 nvidia,pins = "pg7";
553 nvidia,function = "spi4";
554 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
555 nvidia,tristate = <TEGRA_PIN_ENABLE>;
556 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
557 };
558 pi3 {
559 nvidia,pins = "pi3";
560 nvidia,function = "spi4";
561 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
562 nvidia,tristate = <TEGRA_PIN_DISABLE>;
563 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
564 };
565
566 /* Apalis UART1 */
567 pb1 { /* DCD GPIO */
568 nvidia,pins = "pb1";
569 nvidia,function = "rsvd2";
570 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
571 nvidia,tristate = <TEGRA_PIN_ENABLE>;
572 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
573 };
574 pk7 { /* RI GPIO */
575 nvidia,pins = "pk7";
576 nvidia,function = "rsvd2";
577 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
578 nvidia,tristate = <TEGRA_PIN_ENABLE>;
579 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
580 };
581 uart1_txd_pu0 {
582 nvidia,pins = "pu0";
583 nvidia,function = "uarta";
584 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
585 nvidia,tristate = <TEGRA_PIN_DISABLE>;
586 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
587 };
588 uart1_rxd_pu1 {
589 nvidia,pins = "pu1";
590 nvidia,function = "uarta";
591 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
592 nvidia,tristate = <TEGRA_PIN_ENABLE>;
593 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
594 };
595 uart1_cts_n_pu2 {
596 nvidia,pins = "pu2";
597 nvidia,function = "uarta";
598 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
599 nvidia,tristate = <TEGRA_PIN_ENABLE>;
600 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
601 };
602 uart1_rts_n_pu3 {
603 nvidia,pins = "pu3";
604 nvidia,function = "uarta";
605 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
606 nvidia,tristate = <TEGRA_PIN_DISABLE>;
607 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
608 };
609 uart3_cts_n_pa1 { /* DSR GPIO */
610 nvidia,pins = "uart3_cts_n_pa1";
611 nvidia,function = "gmi";
612 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
613 nvidia,tristate = <TEGRA_PIN_ENABLE>;
614 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
615 };
616 uart3_rts_n_pc0 { /* DTR GPIO */
617 nvidia,pins = "uart3_rts_n_pc0";
618 nvidia,function = "gmi";
619 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
620 nvidia,tristate = <TEGRA_PIN_DISABLE>;
621 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
622 };
623
624 /* Apalis UART2 */
625 uart2_txd_pc2 {
626 nvidia,pins = "uart2_txd_pc2";
627 nvidia,function = "irda";
628 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
629 nvidia,tristate = <TEGRA_PIN_DISABLE>;
630 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
631 };
632 uart2_rxd_pc3 {
633 nvidia,pins = "uart2_rxd_pc3";
634 nvidia,function = "irda";
635 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
636 nvidia,tristate = <TEGRA_PIN_ENABLE>;
637 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
638 };
639 uart2_cts_n_pj5 {
640 nvidia,pins = "uart2_cts_n_pj5";
641 nvidia,function = "uartb";
642 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
643 nvidia,tristate = <TEGRA_PIN_ENABLE>;
644 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
645 };
646 uart2_rts_n_pj6 {
647 nvidia,pins = "uart2_rts_n_pj6";
648 nvidia,function = "uartb";
649 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
650 nvidia,tristate = <TEGRA_PIN_DISABLE>;
651 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
652 };
653
654 /* Apalis UART3 */
655 uart3_txd_pw6 {
656 nvidia,pins = "uart3_txd_pw6";
657 nvidia,function = "uartc";
658 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
659 nvidia,tristate = <TEGRA_PIN_DISABLE>;
660 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
661 };
662 uart3_rxd_pw7 {
663 nvidia,pins = "uart3_rxd_pw7";
664 nvidia,function = "uartc";
665 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
666 nvidia,tristate = <TEGRA_PIN_ENABLE>;
667 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
668 };
669
670 /* Apalis UART4 */
671 uart4_rxd_pb0 {
672 nvidia,pins = "pb0";
673 nvidia,function = "uartd";
674 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
675 nvidia,tristate = <TEGRA_PIN_ENABLE>;
676 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
677 };
678 uart4_txd_pj7 {
679 nvidia,pins = "pj7";
680 nvidia,function = "uartd";
681 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
682 nvidia,tristate = <TEGRA_PIN_DISABLE>;
683 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
684 };
685
686 /* Apalis USBH_EN */
687 gen2_i2c_sda_pt6 {
688 nvidia,pins = "gen2_i2c_sda_pt6";
689 nvidia,function = "rsvd2";
690 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
691 nvidia,tristate = <TEGRA_PIN_DISABLE>;
692 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
693 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
694 };
695
696 /* Apalis USBH_OC# */
697 pbb0 {
698 nvidia,pins = "pbb0";
699 nvidia,function = "vgp6";
700 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
701 nvidia,tristate = <TEGRA_PIN_ENABLE>;
702 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
703 };
704
705 /* Apalis USBO1_EN */
706 gen2_i2c_scl_pt5 {
707 nvidia,pins = "gen2_i2c_scl_pt5";
708 nvidia,function = "rsvd2";
709 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
710 nvidia,tristate = <TEGRA_PIN_DISABLE>;
711 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
712 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
713 };
714
715 /* Apalis USBO1_OC# */
716 pbb4 {
717 nvidia,pins = "pbb4";
718 nvidia,function = "vgp4";
719 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
720 nvidia,tristate = <TEGRA_PIN_ENABLE>;
721 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
722 };
723
724 /* Apalis WAKE1_MICO */
725 pex_wake_n_pdd3 {
726 nvidia,pins = "pex_wake_n_pdd3";
727 nvidia,function = "rsvd2";
728 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
729 nvidia,tristate = <TEGRA_PIN_ENABLE>;
730 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
731 };
732
733 /* CORE_PWR_REQ */
734 core_pwr_req {
735 nvidia,pins = "core_pwr_req";
736 nvidia,function = "pwron";
737 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
738 nvidia,tristate = <TEGRA_PIN_DISABLE>;
739 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
740 };
741
742 /* CPU_PWR_REQ */
743 cpu_pwr_req {
744 nvidia,pins = "cpu_pwr_req";
745 nvidia,function = "cpu";
746 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
747 nvidia,tristate = <TEGRA_PIN_DISABLE>;
748 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
749 };
750
751 /* DVFS */
752 dvfs_pwm_px0 {
753 nvidia,pins = "dvfs_pwm_px0";
754 nvidia,function = "cldvfs";
755 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
756 nvidia,tristate = <TEGRA_PIN_DISABLE>;
757 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
758 };
759 dvfs_clk_px2 {
760 nvidia,pins = "dvfs_clk_px2";
761 nvidia,function = "cldvfs";
762 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
763 nvidia,tristate = <TEGRA_PIN_DISABLE>;
764 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
765 };
766
767 /* eMMC */
768 sdmmc4_dat0_paa0 {
769 nvidia,pins = "sdmmc4_dat0_paa0";
770 nvidia,function = "sdmmc4";
771 nvidia,pull = <TEGRA_PIN_PULL_UP>;
772 nvidia,tristate = <TEGRA_PIN_DISABLE>;
773 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
774 };
775 sdmmc4_dat1_paa1 {
776 nvidia,pins = "sdmmc4_dat1_paa1";
777 nvidia,function = "sdmmc4";
778 nvidia,pull = <TEGRA_PIN_PULL_UP>;
779 nvidia,tristate = <TEGRA_PIN_DISABLE>;
780 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
781 };
782 sdmmc4_dat2_paa2 {
783 nvidia,pins = "sdmmc4_dat2_paa2";
784 nvidia,function = "sdmmc4";
785 nvidia,pull = <TEGRA_PIN_PULL_UP>;
786 nvidia,tristate = <TEGRA_PIN_DISABLE>;
787 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
788 };
789 sdmmc4_dat3_paa3 {
790 nvidia,pins = "sdmmc4_dat3_paa3";
791 nvidia,function = "sdmmc4";
792 nvidia,pull = <TEGRA_PIN_PULL_UP>;
793 nvidia,tristate = <TEGRA_PIN_DISABLE>;
794 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
795 };
796 sdmmc4_dat4_paa4 {
797 nvidia,pins = "sdmmc4_dat4_paa4";
798 nvidia,function = "sdmmc4";
799 nvidia,pull = <TEGRA_PIN_PULL_UP>;
800 nvidia,tristate = <TEGRA_PIN_DISABLE>;
801 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
802 };
803 sdmmc4_dat5_paa5 {
804 nvidia,pins = "sdmmc4_dat5_paa5";
805 nvidia,function = "sdmmc4";
806 nvidia,pull = <TEGRA_PIN_PULL_UP>;
807 nvidia,tristate = <TEGRA_PIN_DISABLE>;
808 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
809 };
810 sdmmc4_dat6_paa6 {
811 nvidia,pins = "sdmmc4_dat6_paa6";
812 nvidia,function = "sdmmc4";
813 nvidia,pull = <TEGRA_PIN_PULL_UP>;
814 nvidia,tristate = <TEGRA_PIN_DISABLE>;
815 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
816 };
817 sdmmc4_dat7_paa7 {
818 nvidia,pins = "sdmmc4_dat7_paa7";
819 nvidia,function = "sdmmc4";
820 nvidia,pull = <TEGRA_PIN_PULL_UP>;
821 nvidia,tristate = <TEGRA_PIN_DISABLE>;
822 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
823 };
824 sdmmc4_clk_pcc4 {
825 nvidia,pins = "sdmmc4_clk_pcc4";
826 nvidia,function = "sdmmc4";
827 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
828 nvidia,tristate = <TEGRA_PIN_DISABLE>;
829 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
830 };
831 sdmmc4_cmd_pt7 {
832 nvidia,pins = "sdmmc4_cmd_pt7";
833 nvidia,function = "sdmmc4";
834 nvidia,pull = <TEGRA_PIN_PULL_UP>;
835 nvidia,tristate = <TEGRA_PIN_DISABLE>;
836 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
837 };
838
839 /* JTAG_RTCK */
840 jtag_rtck {
841 nvidia,pins = "jtag_rtck";
842 nvidia,function = "rtck";
843 nvidia,pull = <TEGRA_PIN_PULL_UP>;
844 nvidia,tristate = <TEGRA_PIN_DISABLE>;
845 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
846 };
847
848 /* LAN_DEV_OFF# */
849 ulpi_data5_po6 {
850 nvidia,pins = "ulpi_data5_po6";
851 nvidia,function = "ulpi";
852 nvidia,pull = <TEGRA_PIN_PULL_UP>;
853 nvidia,tristate = <TEGRA_PIN_DISABLE>;
854 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
855 };
856
857 /* LAN_RESET# */
858 kb_row10_ps2 {
859 nvidia,pins = "kb_row10_ps2";
860 nvidia,function = "rsvd2";
861 nvidia,pull = <TEGRA_PIN_PULL_UP>;
862 nvidia,tristate = <TEGRA_PIN_DISABLE>;
863 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
864 };
865
866 /* LAN_WAKE# */
867 ulpi_data4_po5 {
868 nvidia,pins = "ulpi_data4_po5";
869 nvidia,function = "ulpi";
870 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
871 nvidia,tristate = <TEGRA_PIN_ENABLE>;
872 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
873 };
874
875 /* MCU_INT1# */
876 pk2 {
877 nvidia,pins = "pk2";
878 nvidia,function = "rsvd1";
879 nvidia,pull = <TEGRA_PIN_PULL_UP>;
880 nvidia,tristate = <TEGRA_PIN_ENABLE>;
881 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
882 };
883
884 /* MCU_INT2# */
885 pj2 {
886 nvidia,pins = "pj2";
887 nvidia,function = "rsvd1";
888 nvidia,pull = <TEGRA_PIN_PULL_UP>;
889 nvidia,tristate = <TEGRA_PIN_ENABLE>;
890 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
891 };
892
893 /* MCU_INT3# */
894 pi5 {
895 nvidia,pins = "pi5";
896 nvidia,function = "rsvd2";
897 nvidia,pull = <TEGRA_PIN_PULL_UP>;
898 nvidia,tristate = <TEGRA_PIN_ENABLE>;
899 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
900 };
901
902 /* MCU_INT4# */
903 pj0 {
904 nvidia,pins = "pj0";
905 nvidia,function = "rsvd1";
906 nvidia,pull = <TEGRA_PIN_PULL_UP>;
907 nvidia,tristate = <TEGRA_PIN_ENABLE>;
908 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
909 };
910
911 /* MCU_RESET */
912 pbb6 {
913 nvidia,pins = "pbb6";
914 nvidia,function = "rsvd2";
915 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
916 nvidia,tristate = <TEGRA_PIN_DISABLE>;
917 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
918 };
919
920 /* MCU SPI */
921 gpio_x4_aud_px4 {
922 nvidia,pins = "gpio_x4_aud_px4";
923 nvidia,function = "spi2";
924 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
925 nvidia,tristate = <TEGRA_PIN_DISABLE>;
926 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
927 };
928 gpio_x5_aud_px5 {
929 nvidia,pins = "gpio_x5_aud_px5";
930 nvidia,function = "spi2";
931 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
932 nvidia,tristate = <TEGRA_PIN_DISABLE>;
933 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
934 };
935 gpio_x6_aud_px6 { /* MCU_CS */
936 nvidia,pins = "gpio_x6_aud_px6";
937 nvidia,function = "spi2";
938 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
939 nvidia,tristate = <TEGRA_PIN_DISABLE>;
940 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
941 };
942 gpio_x7_aud_px7 {
943 nvidia,pins = "gpio_x7_aud_px7";
944 nvidia,function = "spi2";
945 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
946 nvidia,tristate = <TEGRA_PIN_ENABLE>;
947 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
948 };
949 gpio_w2_aud_pw2 { /* MCU_CSEZP */
950 nvidia,pins = "gpio_w2_aud_pw2";
951 nvidia,function = "spi2";
952 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
953 nvidia,tristate = <TEGRA_PIN_DISABLE>;
954 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
955 };
956
957 /* PMIC_CLK_32K */
958 clk_32k_in {
959 nvidia,pins = "clk_32k_in";
960 nvidia,function = "clk";
961 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
962 nvidia,tristate = <TEGRA_PIN_ENABLE>;
963 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
964 };
965
966 /* PMIC_CPU_OC_INT */
967 clk_32k_out_pa0 {
968 nvidia,pins = "clk_32k_out_pa0";
969 nvidia,function = "soc";
970 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
971 nvidia,tristate = <TEGRA_PIN_ENABLE>;
972 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
973 };
974
975 /* PWR_I2C */
976 pwr_i2c_scl_pz6 {
977 nvidia,pins = "pwr_i2c_scl_pz6";
978 nvidia,function = "i2cpwr";
979 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
980 nvidia,tristate = <TEGRA_PIN_DISABLE>;
981 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
982 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
983 };
984 pwr_i2c_sda_pz7 {
985 nvidia,pins = "pwr_i2c_sda_pz7";
986 nvidia,function = "i2cpwr";
987 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
988 nvidia,tristate = <TEGRA_PIN_DISABLE>;
989 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
990 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
991 };
992
993 /* PWR_INT_N */
994 pwr_int_n {
995 nvidia,pins = "pwr_int_n";
996 nvidia,function = "pmi";
997 nvidia,pull = <TEGRA_PIN_PULL_UP>;
998 nvidia,tristate = <TEGRA_PIN_ENABLE>;
999 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1000 };
1001
1002 /* RESET_MOCI_CTRL */
1003 pu4 {
1004 nvidia,pins = "pu4";
1005 nvidia,function = "gmi";
1006 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1007 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1008 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1009 };
1010
1011 /* RESET_OUT_N */
1012 reset_out_n {
1013 nvidia,pins = "reset_out_n";
1014 nvidia,function = "reset_out_n";
1015 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1016 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1017 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1018 };
1019
1020 /* SHIFT_CTRL_DIR_IN */
1021 kb_row0_pr0 {
1022 nvidia,pins = "kb_row0_pr0";
1023 nvidia,function = "rsvd2";
1024 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1025 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1026 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1027 };
1028 kb_row1_pr1 {
1029 nvidia,pins = "kb_row1_pr1";
1030 nvidia,function = "rsvd2";
1031 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1032 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1033 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1034 };
1035
1036 /* Configure level-shifter as output for HDA */
1037 kb_row11_ps3 {
1038 nvidia,pins = "kb_row11_ps3";
1039 nvidia,function = "rsvd2";
1040 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1041 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1042 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1043 };
1044
1045 /* SHIFT_CTRL_DIR_OUT */
1046 kb_col5_pq5 {
1047 nvidia,pins = "kb_col5_pq5";
1048 nvidia,function = "rsvd2";
1049 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1050 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1051 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1052 };
1053 kb_col6_pq6 {
1054 nvidia,pins = "kb_col6_pq6";
1055 nvidia,function = "rsvd2";
1056 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1057 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1058 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1059 };
1060 kb_col7_pq7 {
1061 nvidia,pins = "kb_col7_pq7";
1062 nvidia,function = "rsvd2";
1063 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1064 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1065 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1066 };
1067
1068 /* SHIFT_CTRL_OE */
1069 kb_col0_pq0 {
1070 nvidia,pins = "kb_col0_pq0";
1071 nvidia,function = "rsvd2";
1072 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1073 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1074 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1075 };
1076 kb_col1_pq1 {
1077 nvidia,pins = "kb_col1_pq1";
1078 nvidia,function = "rsvd2";
1079 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1080 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1081 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1082 };
1083 kb_col2_pq2 {
1084 nvidia,pins = "kb_col2_pq2";
1085 nvidia,function = "rsvd2";
1086 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1087 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1088 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1089 };
1090 kb_col4_pq4 {
1091 nvidia,pins = "kb_col4_pq4";
1092 nvidia,function = "kbc";
1093 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1094 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1095 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1096 };
1097 kb_row2_pr2 {
1098 nvidia,pins = "kb_row2_pr2";
1099 nvidia,function = "rsvd2";
1100 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1101 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1102 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1103 };
1104
1105 /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */
1106 pi6 {
1107 nvidia,pins = "pi6";
1108 nvidia,function = "rsvd1";
1109 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1110 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1111 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1112 };
1113
1114 /* TOUCH_INT */
1115 gpio_w3_aud_pw3 {
1116 nvidia,pins = "gpio_w3_aud_pw3";
1117 nvidia,function = "spi6";
1118 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1119 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1120 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1121 };
1122
1123 pc7 { /* NC */
1124 nvidia,pins = "pc7";
1125 nvidia,function = "rsvd1";
1126 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1127 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1128 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1129 };
1130 pg0 { /* NC */
1131 nvidia,pins = "pg0";
1132 nvidia,function = "rsvd1";
1133 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1134 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1135 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1136 };
1137 pg1 { /* NC */
1138 nvidia,pins = "pg1";
1139 nvidia,function = "rsvd1";
1140 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1141 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1142 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1143 };
1144 pg2 { /* NC */
1145 nvidia,pins = "pg2";
1146 nvidia,function = "rsvd1";
1147 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1148 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1149 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1150 };
1151 pg3 { /* NC */
1152 nvidia,pins = "pg3";
1153 nvidia,function = "rsvd1";
1154 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1155 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1156 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1157 };
1158 pg4 { /* NC */
1159 nvidia,pins = "pg4";
1160 nvidia,function = "rsvd1";
1161 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1162 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1163 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1164 };
1165 ph4 { /* NC */
1166 nvidia,pins = "ph4";
1167 nvidia,function = "rsvd2";
1168 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1169 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1170 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1171 };
1172 ph5 { /* NC */
1173 nvidia,pins = "ph5";
1174 nvidia,function = "rsvd2";
1175 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1176 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1177 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1178 };
1179 ph6 { /* NC */
1180 nvidia,pins = "ph6";
1181 nvidia,function = "gmi";
1182 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1183 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1184 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1185 };
1186 ph7 { /* NC */
1187 nvidia,pins = "ph7";
1188 nvidia,function = "gmi";
1189 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1190 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1191 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1192 };
1193 pi0 { /* NC */
1194 nvidia,pins = "pi0";
1195 nvidia,function = "rsvd1";
1196 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1197 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1198 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1199 };
1200 pi1 { /* NC */
1201 nvidia,pins = "pi1";
1202 nvidia,function = "rsvd1";
1203 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1204 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1205 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1206 };
1207 pi2 { /* NC */
1208 nvidia,pins = "pi2";
1209 nvidia,function = "rsvd4";
1210 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1211 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1212 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1213 };
1214 pi4 { /* NC */
1215 nvidia,pins = "pi4";
1216 nvidia,function = "gmi";
1217 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1218 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1219 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1220 };
1221 pi7 { /* NC */
1222 nvidia,pins = "pi7";
1223 nvidia,function = "rsvd1";
1224 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1225 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1226 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1227 };
1228 pk0 { /* NC */
1229 nvidia,pins = "pk0";
1230 nvidia,function = "rsvd1";
1231 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1232 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1233 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1234 };
1235 pk1 { /* NC */
1236 nvidia,pins = "pk1";
1237 nvidia,function = "rsvd4";
1238 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1239 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1240 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1241 };
1242 pk3 { /* NC */
1243 nvidia,pins = "pk3";
1244 nvidia,function = "gmi";
1245 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1246 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1247 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1248 };
1249 pk4 { /* NC */
1250 nvidia,pins = "pk4";
1251 nvidia,function = "rsvd2";
1252 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1253 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1254 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1255 };
1256 dap1_fs_pn0 { /* NC */
1257 nvidia,pins = "dap1_fs_pn0";
1258 nvidia,function = "rsvd4";
1259 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1260 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1261 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1262 };
1263 dap1_din_pn1 { /* NC */
1264 nvidia,pins = "dap1_din_pn1";
1265 nvidia,function = "rsvd4";
1266 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1267 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1268 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1269 };
1270 dap1_sclk_pn3 { /* NC */
1271 nvidia,pins = "dap1_sclk_pn3";
1272 nvidia,function = "rsvd4";
1273 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1274 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1275 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1276 };
1277 ulpi_data7_po0 { /* NC */
1278 nvidia,pins = "ulpi_data7_po0";
1279 nvidia,function = "ulpi";
1280 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1281 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1282 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1283 };
1284 ulpi_data0_po1 { /* NC */
1285 nvidia,pins = "ulpi_data0_po1";
1286 nvidia,function = "ulpi";
1287 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1288 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1289 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1290 };
1291 ulpi_data1_po2 { /* NC */
1292 nvidia,pins = "ulpi_data1_po2";
1293 nvidia,function = "ulpi";
1294 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1295 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1296 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1297 };
1298 ulpi_data2_po3 { /* NC */
1299 nvidia,pins = "ulpi_data2_po3";
1300 nvidia,function = "ulpi";
1301 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1302 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1303 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1304 };
1305 ulpi_data3_po4 { /* NC */
1306 nvidia,pins = "ulpi_data3_po4";
1307 nvidia,function = "ulpi";
1308 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1309 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1310 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1311 };
1312 ulpi_data6_po7 { /* NC */
1313 nvidia,pins = "ulpi_data6_po7";
1314 nvidia,function = "ulpi";
1315 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1316 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1317 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1318 };
1319 dap4_fs_pp4 { /* NC */
1320 nvidia,pins = "dap4_fs_pp4";
1321 nvidia,function = "rsvd4";
1322 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1323 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1324 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1325 };
1326 dap4_din_pp5 { /* NC */
1327 nvidia,pins = "dap4_din_pp5";
1328 nvidia,function = "rsvd3";
1329 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1330 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1331 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1332 };
1333 dap4_dout_pp6 { /* NC */
1334 nvidia,pins = "dap4_dout_pp6";
1335 nvidia,function = "rsvd4";
1336 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1337 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1338 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1339 };
1340 dap4_sclk_pp7 { /* NC */
1341 nvidia,pins = "dap4_sclk_pp7";
1342 nvidia,function = "rsvd3";
1343 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1344 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1345 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1346 };
1347 kb_col3_pq3 { /* NC */
1348 nvidia,pins = "kb_col3_pq3";
1349 nvidia,function = "kbc";
1350 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1351 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1352 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1353 };
1354 kb_row3_pr3 { /* NC */
1355 nvidia,pins = "kb_row3_pr3";
1356 nvidia,function = "kbc";
1357 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1358 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1359 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1360 };
1361 kb_row4_pr4 { /* NC */
1362 nvidia,pins = "kb_row4_pr4";
1363 nvidia,function = "rsvd3";
1364 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1365 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1366 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1367 };
1368 kb_row5_pr5 { /* NC */
1369 nvidia,pins = "kb_row5_pr5";
1370 nvidia,function = "rsvd3";
1371 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1372 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1373 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1374 };
1375 kb_row6_pr6 { /* NC */
1376 nvidia,pins = "kb_row6_pr6";
1377 nvidia,function = "kbc";
1378 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1379 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1380 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1381 };
1382 kb_row7_pr7 { /* NC */
1383 nvidia,pins = "kb_row7_pr7";
1384 nvidia,function = "rsvd2";
1385 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1386 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1387 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1388 };
1389 kb_row8_ps0 { /* NC */
1390 nvidia,pins = "kb_row8_ps0";
1391 nvidia,function = "rsvd2";
1392 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1393 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1394 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1395 };
1396 kb_row9_ps1 { /* NC */
1397 nvidia,pins = "kb_row9_ps1";
1398 nvidia,function = "rsvd2";
1399 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1400 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1401 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1402 };
1403 kb_row12_ps4 { /* NC */
1404 nvidia,pins = "kb_row12_ps4";
1405 nvidia,function = "rsvd2";
1406 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1407 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1408 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1409 };
1410 kb_row13_ps5 { /* NC */
1411 nvidia,pins = "kb_row13_ps5";
1412 nvidia,function = "rsvd2";
1413 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1414 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1415 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1416 };
1417 kb_row14_ps6 { /* NC */
1418 nvidia,pins = "kb_row14_ps6";
1419 nvidia,function = "rsvd2";
1420 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1421 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1422 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1423 };
1424 kb_row15_ps7 { /* NC */
1425 nvidia,pins = "kb_row15_ps7";
1426 nvidia,function = "rsvd3";
1427 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1428 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1429 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1430 };
1431 kb_row16_pt0 { /* NC */
1432 nvidia,pins = "kb_row16_pt0";
1433 nvidia,function = "rsvd2";
1434 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1435 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1436 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1437 };
1438 kb_row17_pt1 { /* NC */
1439 nvidia,pins = "kb_row17_pt1";
1440 nvidia,function = "rsvd2";
1441 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1442 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1443 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1444 };
1445 pu5 { /* NC */
1446 nvidia,pins = "pu5";
1447 nvidia,function = "gmi";
1448 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1449 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1450 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1451 };
1452 /*
1453 * PCB Version Indication: V1.2 and later have GPIO_PV0
1454 * wired to GND, was NC before
1455 */
1456 pv0 {
1457 nvidia,pins = "pv0";
1458 nvidia,function = "rsvd1";
1459 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1460 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1461 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1462 };
1463 pv1 { /* NC */
1464 nvidia,pins = "pv1";
1465 nvidia,function = "rsvd1";
1466 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1467 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1468 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1469 };
1470 gpio_x1_aud_px1 { /* NC */
1471 nvidia,pins = "gpio_x1_aud_px1";
1472 nvidia,function = "rsvd2";
1473 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1474 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1475 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1476 };
1477 gpio_x3_aud_px3 { /* NC */
1478 nvidia,pins = "gpio_x3_aud_px3";
1479 nvidia,function = "rsvd4";
1480 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1481 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1482 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1483 };
1484 pbb7 { /* NC */
1485 nvidia,pins = "pbb7";
1486 nvidia,function = "rsvd2";
1487 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1488 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1489 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1490 };
1491 pcc1 { /* NC */
1492 nvidia,pins = "pcc1";
1493 nvidia,function = "rsvd2";
1494 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1495 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1496 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1497 };
1498 pcc2 { /* NC */
1499 nvidia,pins = "pcc2";
1500 nvidia,function = "rsvd2";
1501 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1502 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1503 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1504 };
1505 clk3_req_pee1 { /* NC */
1506 nvidia,pins = "clk3_req_pee1";
1507 nvidia,function = "rsvd2";
1508 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1509 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1510 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1511 };
1512 dap_mclk1_req_pee2 { /* NC */
1513 nvidia,pins = "dap_mclk1_req_pee2";
1514 nvidia,function = "rsvd4";
1515 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1516 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1517 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1518 };
1519 /*
1520 * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
1521 * driver enabled aka not tristated and input driver
1522 * enabled as well as it features some magic properties
1523 * even though the external loopback is disabled and the
1524 * internal loopback used as per
1525 * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
1526 * bits being set to 0xfffd according to the TRM!
1527 */
1528 sdmmc3_clk_lb_out_pee4 { /* NC */
1529 nvidia,pins = "sdmmc3_clk_lb_out_pee4";
1530 nvidia,function = "sdmmc3";
1531 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1532 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1533 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1534 };
1535 };
1536 };
1537
1538 serial@70006040 {
b036a75a 1539 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
4957a2f1
MZ		 1540 };
1541
1542 serial@70006200 {
b036a75a 1543 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
4957a2f1
MZ		 1544 };
1545
1546 serial@70006300 {
b036a75a 1547 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
4957a2f1
MZ		 1548 };
1549
1550 hdmi_ddc: i2c@7000c700 {
1551 clock-frequency = <10000>;
1552 };
1553
1554 /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
1555 i2c@7000d000 {
1556 status = "okay";
1557 clock-frequency = <400000>;
1558
1559 /* SGTL5000 audio codec */
1560 sgtl5000: codec@a {
1561 compatible = "fsl,sgtl5000";
1562 reg = <0x0a>;
1563 VDDA-supply = <&reg_3v3>;
1564 VDDIO-supply = <&vddio_1v8>;
1565 clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
1566 };
1567
1568 pmic: pmic@40 {
1569 compatible = "ams,as3722";
1570 reg = <0x40>;
1571 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
1572 ams,system-power-controller;
1573 #interrupt-cells = <2>;
1574 interrupt-controller;
1575 gpio-controller;
1576 #gpio-cells = <2>;
1577 pinctrl-names = "default";
1578 pinctrl-0 = <&as3722_default>;
1579
1580 as3722_default: pinmux {
1581 gpio2_7 {
1582 pins = "gpio2", /* PWR_EN_+V3.3 */
1583 "gpio7"; /* +V1.6_LPO */
1584 function = "gpio";
1585 bias-pull-up;
1586 };
1587
1588 gpio0_1_3_4_5_6 {
1589 pins = "gpio0", "gpio1", "gpio3",
1590 "gpio4", "gpio5", "gpio6";
1591 bias-high-impedance;
1592 };
1593 };
1594
1595 regulators {
1596 vsup-sd2-supply = <&reg_3v3>;
1597 vsup-sd3-supply = <&reg_3v3>;
1598 vsup-sd4-supply = <&reg_3v3>;
1599 vsup-sd5-supply = <&reg_3v3>;
1600 vin-ldo0-supply = <&vddio_ddr_1v35>;
1601 vin-ldo1-6-supply = <&reg_3v3>;
1602 vin-ldo2-5-7-supply = <&vddio_1v8>;
1603 vin-ldo3-4-supply = <&reg_3v3>;
1604 vin-ldo9-10-supply = <&reg_3v3>;
1605 vin-ldo11-supply = <&reg_3v3>;
1606
1607 vdd_cpu: sd0 {
1608 regulator-name = "+VDD_CPU_AP";
1609 regulator-min-microvolt = <700000>;
1610 regulator-max-microvolt = <1400000>;
1611 regulator-min-microamp = <3500000>;
1612 regulator-max-microamp = <3500000>;
1613 regulator-always-on;
1614 regulator-boot-on;
1615 ams,ext-control = <2>;
1616 };
1617
1618 sd1 {
1619 regulator-name = "+VDD_CORE";
1620 regulator-min-microvolt = <700000>;
1621 regulator-max-microvolt = <1350000>;
1622 regulator-min-microamp = <2500000>;
1623 regulator-max-microamp = <4000000>;
1624 regulator-always-on;
1625 regulator-boot-on;
1626 ams,ext-control = <1>;
1627 };
1628
1629 vddio_ddr_1v35: sd2 {
1630 regulator-name =
1631 "+V1.35_VDDIO_DDR(sd2)";
1632 regulator-min-microvolt = <1350000>;
1633 regulator-max-microvolt = <1350000>;
1634 regulator-always-on;
1635 regulator-boot-on;
1636 };
1637
1638 sd3 {
1639 regulator-name =
1640 "+V1.35_VDDIO_DDR(sd3)";
1641 regulator-min-microvolt = <1350000>;
1642 regulator-max-microvolt = <1350000>;
1643 regulator-always-on;
1644 regulator-boot-on;
1645 };
1646
1647 vdd_1v05: sd4 {
1648 regulator-name = "+V1.05";
1649 regulator-min-microvolt = <1050000>;
1650 regulator-max-microvolt = <1050000>;
1651 };
1652
1653 vddio_1v8: sd5 {
1654 regulator-name = "+V1.8";
1655 regulator-min-microvolt = <1800000>;
1656 regulator-max-microvolt = <1800000>;
1657 regulator-boot-on;
1658 regulator-always-on;
1659 };
1660
1661 vdd_gpu: sd6 {
1662 regulator-name = "+VDD_GPU_AP";
1663 regulator-min-microvolt = <650000>;
1664 regulator-max-microvolt = <1200000>;
1665 regulator-min-microamp = <3500000>;
1666 regulator-max-microamp = <3500000>;
1667 regulator-boot-on;
1668 regulator-always-on;
1669 };
1670
1671 avdd_1v05: ldo0 {
1672 regulator-name = "+V1.05_AVDD";
1673 regulator-min-microvolt = <1050000>;
1674 regulator-max-microvolt = <1050000>;
1675 regulator-boot-on;
1676 regulator-always-on;
1677 ams,ext-control = <1>;
1678 };
1679
1680 vddio_sdmmc1: ldo1 {
1681 regulator-name = "VDDIO_SDMMC1";
1682 regulator-min-microvolt = <1800000>;
1683 regulator-max-microvolt = <3300000>;
1684 };
1685
1686 ldo2 {
1687 regulator-name = "+V1.2";
1688 regulator-min-microvolt = <1200000>;
1689 regulator-max-microvolt = <1200000>;
1690 regulator-boot-on;
1691 regulator-always-on;
1692 };
1693
1694 ldo3 {
1695 regulator-name = "+V1.05_RTC";
1696 regulator-min-microvolt = <1000000>;
1697 regulator-max-microvolt = <1000000>;
1698 regulator-boot-on;
1699 regulator-always-on;
1700 ams,enable-tracking;
1701 };
1702
1703 /* 1.8V for LVDS, 3.3V for eDP */
1704 ldo4 {
1705 regulator-name = "AVDD_LVDS0_PLL";
1706 regulator-min-microvolt = <1800000>;
1707 regulator-max-microvolt = <1800000>;
1708 };
1709
1710 /* LDO5 not used */
1711
1712 vddio_sdmmc3: ldo6 {
1713 regulator-name = "VDDIO_SDMMC3";
1714 regulator-min-microvolt = <1800000>;
1715 regulator-max-microvolt = <3300000>;
1716 };
1717
1718 /* LDO7 not used */
1719
1720 ldo9 {
1721 regulator-name = "+V3.3_ETH(ldo9)";
1722 regulator-min-microvolt = <3300000>;
1723 regulator-max-microvolt = <3300000>;
1724 regulator-always-on;
1725 };
1726
1727 ldo10 {
1728 regulator-name = "+V3.3_ETH(ldo10)";
1729 regulator-min-microvolt = <3300000>;
1730 regulator-max-microvolt = <3300000>;
1731 regulator-always-on;
1732 };
1733
1734 ldo11 {
1735 regulator-name = "+V1.8_VPP_FUSE";
1736 regulator-min-microvolt = <1800000>;
1737 regulator-max-microvolt = <1800000>;
1738 };
1739 };
1740 };
1741
1742 /*
1743 * TMP451 temperature sensor
1744 * Note: THERM_N directly connected to AS3722 PMIC THERM
1745 */
1746 temperature-sensor@4c {
1747 compatible = "ti,tmp451";
1748 reg = <0x4c>;
1749 interrupt-parent = <&gpio>;
1750 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
1751 #thermal-sensor-cells = <1>;
1752 };
1753 };
1754
1755 /* SPI2: MCU SPI */
1756 spi@7000d600 {
1757 status = "okay";
1758 spi-max-frequency = <25000000>;
1759 };
1760
1761 pmc@7000e400 {
1762 nvidia,invert-interrupt;
1763 nvidia,suspend-mode = <1>;
1764 nvidia,cpu-pwr-good-time = <500>;
1765 nvidia,cpu-pwr-off-time = <300>;
1766 nvidia,core-pwr-good-time = <641 3845>;
1767 nvidia,core-pwr-off-time = <61036>;
1768 nvidia,core-power-req-active-high;
1769 nvidia,sys-clock-req-active-high;
1770
1771 /* Set power_off bit in ResetControl register of AS3722 PMIC */
1772 i2c-thermtrip {
1773 nvidia,i2c-controller-id = <4>;
1774 nvidia,bus-addr = <0x40>;
1775 nvidia,reg-addr = <0x36>;
1776 nvidia,reg-data = <0x2>;
1777 };
1778 };
1779
1780 sata@70020000 {
1781 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
1782 phy-names = "sata-0";
1783 avdd-supply = <&vdd_1v05>;
1784 hvdd-supply = <&reg_3v3>;
1785 vddio-supply = <&vdd_1v05>;
1786 };
1787
1788 usb@70090000 {
1789 /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
1790 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
1791 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
1792 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
1793 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
1794 <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
1795 phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
1796 avddio-pex-supply = <&vdd_1v05>;
1797 avdd-pll-erefe-supply = <&avdd_1v05>;
1798 avdd-pll-utmip-supply = <&vddio_1v8>;
1799 avdd-usb-ss-pll-supply = <&vdd_1v05>;
1800 avdd-usb-supply = <&reg_3v3>;
1801 dvddio-pex-supply = <&vdd_1v05>;
1802 hvdd-usb-ss-pll-e-supply = <&reg_3v3>;
1803 hvdd-usb-ss-supply = <&reg_3v3>;
1804 };
1805
1806 padctl@7009f000 {
1807 pads {
1808 usb2 {
1809 status = "okay";
1810
1811 lanes {
1812 usb2-0 {
1813 nvidia,function = "xusb";
1814 status = "okay";
1815 };
1816
1817 usb2-1 {
1818 nvidia,function = "xusb";
1819 status = "okay";
1820 };
1821
1822 usb2-2 {
1823 nvidia,function = "xusb";
1824 status = "okay";
1825 };
1826 };
1827 };
1828
1829 pcie {
1830 status = "okay";
1831
1832 lanes {
1833 pcie-0 {
1834 nvidia,function = "usb3-ss";
1835 status = "okay";
1836 };
1837
1838 pcie-1 {
1839 nvidia,function = "usb3-ss";
1840 status = "okay";
1841 };
1842
1843 pcie-2 {
1844 nvidia,function = "pcie";
1845 status = "okay";
1846 };
1847
1848 pcie-3 {
1849 nvidia,function = "pcie";
1850 status = "okay";
1851 };
1852
1853 pcie-4 {
1854 nvidia,function = "pcie";
1855 status = "okay";
1856 };
1857 };
1858 };
1859
1860 sata {
1861 status = "okay";
1862
1863 lanes {
1864 sata-0 {
1865 nvidia,function = "sata";
1866 status = "okay";
1867 };
1868 };
1869 };
1870 };
1871
1872 ports {
1873 /* USBO1 */
1874 usb2-0 {
1875 status = "okay";
1876 mode = "otg";
1877
1878 vbus-supply = <&reg_usbo1_vbus>;
1879 };
1880
1881 /* USBH2 */
1882 usb2-1 {
1883 status = "okay";
1884 mode = "host";
1885
1886 vbus-supply = <&reg_usbh_vbus>;
1887 };
1888
1889 /* USBH4 */
1890 usb2-2 {
1891 status = "okay";
1892 mode = "host";
1893
1894 vbus-supply = <&reg_usbh_vbus>;
1895 };
1896
1897 usb3-0 {
1898 nvidia,usb2-companion = <2>;
1899 status = "okay";
1900 };
1901
1902 usb3-1 {
1903 nvidia,usb2-companion = <0>;
1904 status = "okay";
1905 };
1906 };
1907 };
1908
1909 /* eMMC */
1910 sdhci@700b0600 {
1911 status = "okay";
1912 bus-width = <8>;
1913 non-removable;
1914 };
1915
1916 /* CPU DFLL clock */
1917 clock@70110000 {
1918 status = "okay";
1919 vdd-cpu-supply = <&vdd_cpu>;
1920 nvidia,i2c-fs-rate = <400000>;
1921 };
1922
1923 ahub@70300000 {
1924 i2s@70301200 {
1925 status = "okay";
1926 };
1927 };
1928
1929 clocks {
1930 compatible = "simple-bus";
1931 #address-cells = <1>;
1932 #size-cells = <0>;
1933
1934 clk32k_in: clock@0 {
1935 compatible = "fixed-clock";
1936 reg = <0>;
1937 #clock-cells = <0>;
1938 clock-frequency = <32768>;
1939 };
1940 };
1941
1942 cpus {
1943 cpu@0 {
1944 vdd-cpu-supply = <&vdd_cpu>;
1945 };
1946 };
1947
1948 reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
1949 compatible = "regulator-fixed";
1950 regulator-name = "+V1.05_AVDD_HDMI_PLL";
1951 regulator-min-microvolt = <1050000>;
1952 regulator-max-microvolt = <1050000>;
1953 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1954 vin-supply = <&vdd_1v05>;
1955 };
1956
1957 reg_3v3_mxm: regulator-3v3-mxm {
1958 compatible = "regulator-fixed";
1959 regulator-name = "+V3.3_MXM";
1960 regulator-min-microvolt = <3300000>;
1961 regulator-max-microvolt = <3300000>;
1962 regulator-always-on;
1963 regulator-boot-on;
1964 };
1965
1966 reg_3v3: regulator-3v3 {
1967 compatible = "regulator-fixed";
1968 regulator-name = "+V3.3";
1969 regulator-min-microvolt = <3300000>;
1970 regulator-max-microvolt = <3300000>;
1971 regulator-always-on;
1972 regulator-boot-on;
1973 /* PWR_EN_+V3.3 */
1974 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
1975 enable-active-high;
1976 vin-supply = <&reg_3v3_mxm>;
1977 };
1978
1979 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
1980 compatible = "regulator-fixed";
1981 regulator-name = "+V3.3_AVDD_HDMI";
1982 regulator-min-microvolt = <3300000>;
1983 regulator-max-microvolt = <3300000>;
1984 vin-supply = <&vdd_1v05>;
1985 };
1986
1987 sound {
1988 compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
1989 "nvidia,tegra-audio-sgtl5000";
1990 nvidia,model = "Toradex Apalis TK1";
1991 nvidia,audio-routing =
1992 "Headphone Jack", "HP_OUT",
1993 "LINE_IN", "Line In Jack",
1994 "MIC_IN", "Mic Jack";
1995 nvidia,i2s-controller = <&tegra_i2s2>;
1996 nvidia,audio-codec = <&sgtl5000>;
1997 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
1998 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
1999 <&tegra_car TEGRA124_CLK_EXTERN1>;
2000 clock-names = "pll_a", "pll_a_out0", "mclk";
2001 };
2002
2003 thermal-zones {
2004 cpu {
2005 trips {
2006 cpu-shutdown-trip {
2007 temperature = <101000>;
2008 hysteresis = <0>;
2009 type = "critical";
2010 };
2011 };
2012 };
2013
2014 mem {
2015 trips {
2016 mem-shutdown-trip {
2017 temperature = <101000>;
2018 hysteresis = <0>;
2019 type = "critical";
2020 };
2021 };
2022 };
2023
2024 gpu {
2025 trips {
2026 gpu-shutdown-trip {
2027 temperature = <101000>;
2028 hysteresis = <0>;
2029 type = "critical";
2030 };
2031 };
2032 };
2033 };
2034};
2035
2036&gpio {
2037 /* I210 Gigabit Ethernet Controller Reset */
2038 lan_reset_n {
2039 gpio-hog;
2040 gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
2041 output-high;
2042 line-name = "LAN_RESET_N";
2043 };
2044
2045 /* Control MXM3 pin 26 Reset Module Output Carrier Input */
2046 reset_moci_ctrl {
2047 gpio-hog;
2048 gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
2049 output-high;
2050 line-name = "RESET_MOCI_CTRL";
2051 };
2052};
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