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85afd20e | 1 | /* |
0d900bbb | 2 | * Copyright 2016-2018 Toradex AG |
85afd20e MZ |
3 | * |
4 | * This file is dual-licensed: you can use it either under the terms | |
5 | * of the GPL or the X11 license, at your option. Note that this dual | |
6 | * licensing only applies to this file, and not this project as a | |
7 | * whole. | |
8 | * | |
9 | * a) This file is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This file is distributed in the hope that it will be useful | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * Or, alternatively | |
19 | * | |
20 | * b) Permission is hereby granted, free of charge, to any person | |
21 | * obtaining a copy of this software and associated documentation | |
22 | * files (the "Software"), to deal in the Software without | |
23 | * restriction, including without limitation the rights to use | |
24 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
25 | * sell copies of the Software, and to permit persons to whom the | |
26 | * Software is furnished to do so, subject to the following | |
27 | * conditions: | |
28 | * | |
29 | * The above copyright notice and this permission notice shall be | |
30 | * included in all copies or substantial portions of the Software. | |
31 | * | |
32 | * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND | |
33 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
34 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
35 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
36 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY | |
37 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
38 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
39 | * OTHER DEALINGS IN THE SOFTWARE. | |
40 | */ | |
41 | ||
42 | #include "tegra124.dtsi" | |
43 | #include "tegra124-apalis-emc.dtsi" | |
44 | ||
45 | /* | |
46 | * Toradex Apalis TK1 Module Device Tree | |
6270bd3d | 47 | * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A |
85afd20e MZ |
48 | */ |
49 | / { | |
48299769 | 50 | memory@80000000 { |
85afd20e MZ |
51 | reg = <0x0 0x80000000 0x0 0x80000000>; |
52 | }; | |
53 | ||
508d690e | 54 | pcie@1003000 { |
85afd20e | 55 | status = "okay"; |
1bef3a57 MZ |
56 | avddio-pex-supply = <®_1v05_vdd>; |
57 | avdd-pex-pll-supply = <®_1v05_vdd>; | |
58 | avdd-pll-erefe-supply = <®_1v05_avdd>; | |
59 | dvddio-pex-supply = <®_1v05_vdd>; | |
60 | hvdd-pex-pll-e-supply = <®_module_3v3>; | |
61 | hvdd-pex-supply = <®_module_3v3>; | |
62 | vddio-pex-ctl-supply = <®_module_3v3>; | |
85afd20e MZ |
63 | |
64 | /* Apalis PCIe (additional lane Apalis type specific) */ | |
65 | pci@1,0 { | |
66 | /* PCIE1_RX/TX and TS_DIFF1/2 */ | |
67 | phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>, | |
68 | <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; | |
69 | phy-names = "pcie-0", "pcie-1"; | |
70 | }; | |
71 | ||
72 | /* I210 Gigabit Ethernet Controller (On-module) */ | |
73 | pci@2,0 { | |
74 | phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; | |
75 | phy-names = "pcie-0"; | |
76 | status = "okay"; | |
864495be MZ |
77 | |
78 | pcie@0 { | |
79 | reg = <0 0 0 0 0>; | |
80 | local-mac-address = [00 00 00 00 00 00]; | |
81 | }; | |
85afd20e MZ |
82 | }; |
83 | }; | |
84 | ||
85 | host1x@50000000 { | |
86 | hdmi@54280000 { | |
85afd20e MZ |
87 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
88 | nvidia,hpd-gpio = | |
89 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | |
f2f7bf06 MZ |
90 | pll-supply = <®_1v05_avdd_hdmi_pll>; |
91 | vdd-supply = <®_3v3_avdd_hdmi>; | |
85afd20e MZ |
92 | }; |
93 | }; | |
94 | ||
95 | gpu@0,57000000 { | |
96 | /* | |
97 | * Node left disabled on purpose - the bootloader will enable | |
98 | * it after having set the VPR up | |
99 | */ | |
1bef3a57 | 100 | vdd-supply = <®_vdd_gpu>; |
85afd20e MZ |
101 | }; |
102 | ||
35a2473f | 103 | pinmux@70000868 { |
85afd20e MZ |
104 | pinctrl-names = "default"; |
105 | pinctrl-0 = <&state_default>; | |
106 | ||
107 | state_default: pinmux { | |
108 | /* Analogue Audio (On-module) */ | |
26e19cdf | 109 | dap3-fs-pp0 { |
85afd20e MZ |
110 | nvidia,pins = "dap3_fs_pp0"; |
111 | nvidia,function = "i2s2"; | |
112 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
113 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
114 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
115 | }; | |
26e19cdf | 116 | dap3-din-pp1 { |
85afd20e MZ |
117 | nvidia,pins = "dap3_din_pp1"; |
118 | nvidia,function = "i2s2"; | |
119 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
120 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
121 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
122 | }; | |
26e19cdf | 123 | dap3-dout-pp2 { |
85afd20e MZ |
124 | nvidia,pins = "dap3_dout_pp2"; |
125 | nvidia,function = "i2s2"; | |
126 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
127 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
128 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
129 | }; | |
26e19cdf | 130 | dap3-sclk-pp3 { |
85afd20e MZ |
131 | nvidia,pins = "dap3_sclk_pp3"; |
132 | nvidia,function = "i2s2"; | |
133 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
134 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
135 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
136 | }; | |
26e19cdf | 137 | dap-mclk1-pw4 { |
85afd20e MZ |
138 | nvidia,pins = "dap_mclk1_pw4"; |
139 | nvidia,function = "extperiph1"; | |
140 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
141 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
142 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
143 | }; | |
144 | ||
145 | /* Apalis BKL1_ON */ | |
146 | pbb5 { | |
147 | nvidia,pins = "pbb5"; | |
148 | nvidia,function = "vgp5"; | |
149 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
150 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
151 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
152 | }; | |
153 | ||
154 | /* Apalis BKL1_PWM */ | |
155 | pu6 { | |
156 | nvidia,pins = "pu6"; | |
157 | nvidia,function = "pwm3"; | |
158 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
159 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
160 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
161 | }; | |
162 | ||
163 | /* Apalis CAM1_MCLK */ | |
26e19cdf | 164 | cam-mclk-pcc0 { |
85afd20e MZ |
165 | nvidia,pins = "cam_mclk_pcc0"; |
166 | nvidia,function = "vi_alt3"; | |
167 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
168 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
169 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
170 | }; | |
171 | ||
172 | /* Apalis Digital Audio */ | |
26e19cdf | 173 | dap2-fs-pa2 { |
85afd20e MZ |
174 | nvidia,pins = "dap2_fs_pa2"; |
175 | nvidia,function = "hda"; | |
176 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
177 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
178 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
179 | }; | |
26e19cdf | 180 | dap2-sclk-pa3 { |
85afd20e MZ |
181 | nvidia,pins = "dap2_sclk_pa3"; |
182 | nvidia,function = "hda"; | |
183 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
184 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
185 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
186 | }; | |
26e19cdf | 187 | dap2-din-pa4 { |
85afd20e MZ |
188 | nvidia,pins = "dap2_din_pa4"; |
189 | nvidia,function = "hda"; | |
190 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
191 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
192 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
193 | }; | |
26e19cdf | 194 | dap2-dout-pa5 { |
85afd20e MZ |
195 | nvidia,pins = "dap2_dout_pa5"; |
196 | nvidia,function = "hda"; | |
197 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
198 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
199 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
200 | }; | |
201 | pbb3 { /* DAP1_RESET */ | |
202 | nvidia,pins = "pbb3"; | |
203 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
204 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
205 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
206 | }; | |
26e19cdf | 207 | clk3-out-pee0 { |
85afd20e MZ |
208 | nvidia,pins = "clk3_out_pee0"; |
209 | nvidia,function = "extperiph3"; | |
210 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
211 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
212 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
213 | }; | |
214 | ||
215 | /* Apalis GPIO */ | |
26e19cdf | 216 | ddc-scl-pv4 { |
85afd20e MZ |
217 | nvidia,pins = "ddc_scl_pv4"; |
218 | nvidia,function = "rsvd2"; | |
219 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
220 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
221 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
222 | }; | |
26e19cdf | 223 | ddc-sda-pv5 { |
85afd20e MZ |
224 | nvidia,pins = "ddc_sda_pv5"; |
225 | nvidia,function = "rsvd2"; | |
226 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
227 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
228 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
229 | }; | |
26e19cdf | 230 | pex-l0-rst-n-pdd1 { |
85afd20e MZ |
231 | nvidia,pins = "pex_l0_rst_n_pdd1"; |
232 | nvidia,function = "rsvd2"; | |
233 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
234 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
235 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
236 | }; | |
26e19cdf | 237 | pex-l0-clkreq-n-pdd2 { |
85afd20e MZ |
238 | nvidia,pins = "pex_l0_clkreq_n_pdd2"; |
239 | nvidia,function = "rsvd2"; | |
240 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
241 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
242 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
243 | }; | |
26e19cdf | 244 | pex-l1-rst-n-pdd5 { |
85afd20e MZ |
245 | nvidia,pins = "pex_l1_rst_n_pdd5"; |
246 | nvidia,function = "rsvd2"; | |
247 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
248 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
249 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
250 | }; | |
26e19cdf | 251 | pex-l1-clkreq-n-pdd6 { |
85afd20e MZ |
252 | nvidia,pins = "pex_l1_clkreq_n_pdd6"; |
253 | nvidia,function = "rsvd2"; | |
254 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
255 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
256 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
257 | }; | |
26e19cdf | 258 | dp-hpd-pff0 { |
85afd20e | 259 | nvidia,pins = "dp_hpd_pff0"; |
a7f9d4fe | 260 | nvidia,function = "dp"; |
85afd20e MZ |
261 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
262 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
263 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
264 | }; | |
265 | pff2 { | |
266 | nvidia,pins = "pff2"; | |
267 | nvidia,function = "rsvd2"; | |
268 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
269 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
270 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
271 | }; | |
272 | owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */ | |
273 | nvidia,pins = "owr"; | |
274 | nvidia,function = "rsvd2"; | |
275 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
276 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
277 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
278 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
279 | }; | |
280 | ||
281 | /* Apalis HDMI1_CEC */ | |
26e19cdf | 282 | hdmi-cec-pee3 { |
85afd20e MZ |
283 | nvidia,pins = "hdmi_cec_pee3"; |
284 | nvidia,function = "cec"; | |
285 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
286 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
287 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
288 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
289 | }; | |
290 | ||
291 | /* Apalis HDMI1_HPD */ | |
26e19cdf | 292 | hdmi-int-pn7 { |
85afd20e MZ |
293 | nvidia,pins = "hdmi_int_pn7"; |
294 | nvidia,function = "rsvd1"; | |
295 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
296 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
297 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
298 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
299 | }; | |
300 | ||
301 | /* Apalis I2C1 */ | |
26e19cdf | 302 | gen1-i2c-scl-pc4 { |
85afd20e MZ |
303 | nvidia,pins = "gen1_i2c_scl_pc4"; |
304 | nvidia,function = "i2c1"; | |
305 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
306 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
307 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
308 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
309 | }; | |
26e19cdf | 310 | gen1-i2c-sda-pc5 { |
85afd20e MZ |
311 | nvidia,pins = "gen1_i2c_sda_pc5"; |
312 | nvidia,function = "i2c1"; | |
313 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
314 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
315 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
316 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
317 | }; | |
318 | ||
319 | /* Apalis I2C2 (DDC) */ | |
26e19cdf | 320 | gen2-i2c-scl-pt5 { |
85afd20e MZ |
321 | nvidia,pins = "gen2_i2c_scl_pt5"; |
322 | nvidia,function = "i2c2"; | |
323 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
324 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
325 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
326 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
327 | }; | |
26e19cdf | 328 | gen2-i2c-sda-pt6 { |
85afd20e MZ |
329 | nvidia,pins = "gen2_i2c_sda_pt6"; |
330 | nvidia,function = "i2c2"; | |
331 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
332 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
333 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
334 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
335 | }; | |
336 | ||
337 | /* Apalis I2C3 (CAM) */ | |
26e19cdf | 338 | cam-i2c-scl-pbb1 { |
85afd20e MZ |
339 | nvidia,pins = "cam_i2c_scl_pbb1"; |
340 | nvidia,function = "i2c3"; | |
341 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
342 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
343 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
344 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
345 | }; | |
26e19cdf | 346 | cam-i2c-sda-pbb2 { |
85afd20e MZ |
347 | nvidia,pins = "cam_i2c_sda_pbb2"; |
348 | nvidia,function = "i2c3"; | |
349 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
350 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
351 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
352 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
353 | }; | |
354 | ||
355 | /* Apalis MMC1 */ | |
26e19cdf | 356 | sdmmc1-cd-n-pv3 { /* CD# GPIO */ |
85afd20e MZ |
357 | nvidia,pins = "sdmmc1_wp_n_pv3"; |
358 | nvidia,function = "sdmmc1"; | |
359 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
360 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
361 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
362 | }; | |
26e19cdf | 363 | clk2-out-pw5 { /* D5 GPIO */ |
85afd20e MZ |
364 | nvidia,pins = "clk2_out_pw5"; |
365 | nvidia,function = "rsvd2"; | |
366 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
367 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
368 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
369 | }; | |
26e19cdf | 370 | sdmmc1-dat3-py4 { |
85afd20e MZ |
371 | nvidia,pins = "sdmmc1_dat3_py4"; |
372 | nvidia,function = "sdmmc1"; | |
373 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
374 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
375 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
376 | }; | |
26e19cdf | 377 | sdmmc1-dat2-py5 { |
85afd20e MZ |
378 | nvidia,pins = "sdmmc1_dat2_py5"; |
379 | nvidia,function = "sdmmc1"; | |
380 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
381 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
382 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
383 | }; | |
26e19cdf | 384 | sdmmc1-dat1-py6 { |
85afd20e MZ |
385 | nvidia,pins = "sdmmc1_dat1_py6"; |
386 | nvidia,function = "sdmmc1"; | |
387 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
388 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
389 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
390 | }; | |
26e19cdf | 391 | sdmmc1-dat0-py7 { |
85afd20e MZ |
392 | nvidia,pins = "sdmmc1_dat0_py7"; |
393 | nvidia,function = "sdmmc1"; | |
394 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
395 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
396 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
397 | }; | |
26e19cdf | 398 | sdmmc1-clk-pz0 { |
85afd20e MZ |
399 | nvidia,pins = "sdmmc1_clk_pz0"; |
400 | nvidia,function = "sdmmc1"; | |
401 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
402 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
403 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
404 | }; | |
26e19cdf | 405 | sdmmc1-cmd-pz1 { |
85afd20e MZ |
406 | nvidia,pins = "sdmmc1_cmd_pz1"; |
407 | nvidia,function = "sdmmc1"; | |
408 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
409 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
410 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
411 | }; | |
26e19cdf | 412 | clk2-req-pcc5 { /* D4 GPIO */ |
85afd20e MZ |
413 | nvidia,pins = "clk2_req_pcc5"; |
414 | nvidia,function = "rsvd2"; | |
415 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
416 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
417 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
418 | }; | |
26e19cdf | 419 | sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */ |
85afd20e | 420 | nvidia,pins = "sdmmc3_clk_lb_in_pee5"; |
5142bd65 MZ |
421 | nvidia,function = "rsvd2"; |
422 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
85afd20e MZ |
423 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
424 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
425 | }; | |
26e19cdf | 426 | usb-vbus-en2-pff1 { /* D7 GPIO */ |
85afd20e MZ |
427 | nvidia,pins = "usb_vbus_en2_pff1"; |
428 | nvidia,function = "rsvd2"; | |
429 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
430 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
431 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
432 | }; | |
433 | ||
434 | /* Apalis PWM */ | |
435 | ph0 { | |
436 | nvidia,pins = "ph0"; | |
437 | nvidia,function = "pwm0"; | |
438 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
439 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
440 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
441 | }; | |
442 | ph1 { | |
443 | nvidia,pins = "ph1"; | |
444 | nvidia,function = "pwm1"; | |
445 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
446 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
447 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
448 | }; | |
449 | ph2 { | |
450 | nvidia,pins = "ph2"; | |
451 | nvidia,function = "pwm2"; | |
452 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
453 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
454 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
455 | }; | |
e18dc296 | 456 | /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ |
85afd20e MZ |
457 | ph3 { |
458 | nvidia,pins = "ph3"; | |
e18dc296 MZ |
459 | nvidia,function = "pwm3"; |
460 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
461 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
85afd20e MZ |
462 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
463 | }; | |
464 | ||
465 | /* Apalis SATA1_ACT# */ | |
26e19cdf | 466 | dap1-dout-pn2 { |
85afd20e MZ |
467 | nvidia,pins = "dap1_dout_pn2"; |
468 | nvidia,function = "gmi"; | |
469 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
470 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
471 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
472 | }; | |
473 | ||
474 | /* Apalis SD1 */ | |
26e19cdf | 475 | sdmmc3-clk-pa6 { |
85afd20e MZ |
476 | nvidia,pins = "sdmmc3_clk_pa6"; |
477 | nvidia,function = "sdmmc3"; | |
478 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
479 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
480 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
481 | }; | |
26e19cdf | 482 | sdmmc3-cmd-pa7 { |
85afd20e MZ |
483 | nvidia,pins = "sdmmc3_cmd_pa7"; |
484 | nvidia,function = "sdmmc3"; | |
485 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
486 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
487 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
488 | }; | |
26e19cdf | 489 | sdmmc3-dat3-pb4 { |
85afd20e MZ |
490 | nvidia,pins = "sdmmc3_dat3_pb4"; |
491 | nvidia,function = "sdmmc3"; | |
492 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
493 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
494 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
495 | }; | |
26e19cdf | 496 | sdmmc3-dat2-pb5 { |
85afd20e MZ |
497 | nvidia,pins = "sdmmc3_dat2_pb5"; |
498 | nvidia,function = "sdmmc3"; | |
499 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
500 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
501 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
502 | }; | |
26e19cdf | 503 | sdmmc3-dat1-pb6 { |
85afd20e MZ |
504 | nvidia,pins = "sdmmc3_dat1_pb6"; |
505 | nvidia,function = "sdmmc3"; | |
506 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
507 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
508 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
509 | }; | |
26e19cdf | 510 | sdmmc3-dat0-pb7 { |
85afd20e MZ |
511 | nvidia,pins = "sdmmc3_dat0_pb7"; |
512 | nvidia,function = "sdmmc3"; | |
513 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
514 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
515 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
516 | }; | |
26e19cdf | 517 | sdmmc3-cd-n-pv2 { /* CD# GPIO */ |
5142bd65 MZ |
518 | nvidia,pins = "sdmmc3_cd_n_pv2"; |
519 | nvidia,function = "rsvd3"; | |
520 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
85afd20e | 521 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
5142bd65 | 522 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
85afd20e MZ |
523 | }; |
524 | ||
525 | /* Apalis SPDIF */ | |
26e19cdf | 526 | spdif-out-pk5 { |
85afd20e MZ |
527 | nvidia,pins = "spdif_out_pk5"; |
528 | nvidia,function = "spdif"; | |
529 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
530 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
531 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
532 | }; | |
26e19cdf | 533 | spdif-in-pk6 { |
85afd20e MZ |
534 | nvidia,pins = "spdif_in_pk6"; |
535 | nvidia,function = "spdif"; | |
536 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
537 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
538 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
539 | }; | |
540 | ||
541 | /* Apalis SPI1 */ | |
26e19cdf | 542 | ulpi-clk-py0 { |
85afd20e MZ |
543 | nvidia,pins = "ulpi_clk_py0"; |
544 | nvidia,function = "spi1"; | |
545 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
546 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
547 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
548 | }; | |
26e19cdf | 549 | ulpi-dir-py1 { |
85afd20e MZ |
550 | nvidia,pins = "ulpi_dir_py1"; |
551 | nvidia,function = "spi1"; | |
552 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
553 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
554 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
555 | }; | |
26e19cdf | 556 | ulpi-nxt-py2 { |
85afd20e MZ |
557 | nvidia,pins = "ulpi_nxt_py2"; |
558 | nvidia,function = "spi1"; | |
559 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
560 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
561 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
562 | }; | |
26e19cdf | 563 | ulpi-stp-py3 { |
85afd20e MZ |
564 | nvidia,pins = "ulpi_stp_py3"; |
565 | nvidia,function = "spi1"; | |
566 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
567 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
568 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
569 | }; | |
570 | ||
571 | /* Apalis SPI2 */ | |
572 | pg5 { | |
573 | nvidia,pins = "pg5"; | |
574 | nvidia,function = "spi4"; | |
575 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
576 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
577 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
578 | }; | |
579 | pg6 { | |
580 | nvidia,pins = "pg6"; | |
581 | nvidia,function = "spi4"; | |
582 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
583 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
584 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
585 | }; | |
586 | pg7 { | |
587 | nvidia,pins = "pg7"; | |
588 | nvidia,function = "spi4"; | |
589 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
590 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
591 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
592 | }; | |
593 | pi3 { | |
594 | nvidia,pins = "pi3"; | |
595 | nvidia,function = "spi4"; | |
596 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
597 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
598 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
599 | }; | |
600 | ||
601 | /* Apalis UART1 */ | |
602 | pb1 { /* DCD GPIO */ | |
603 | nvidia,pins = "pb1"; | |
604 | nvidia,function = "rsvd2"; | |
605 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
606 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
607 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
608 | }; | |
609 | pk7 { /* RI GPIO */ | |
610 | nvidia,pins = "pk7"; | |
611 | nvidia,function = "rsvd2"; | |
612 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
613 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
614 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
615 | }; | |
26e19cdf | 616 | uart1-txd-pu0 { |
85afd20e MZ |
617 | nvidia,pins = "pu0"; |
618 | nvidia,function = "uarta"; | |
619 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
620 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
621 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
622 | }; | |
26e19cdf | 623 | uart1-rxd-pu1 { |
85afd20e MZ |
624 | nvidia,pins = "pu1"; |
625 | nvidia,function = "uarta"; | |
626 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
627 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
628 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
629 | }; | |
26e19cdf | 630 | uart1-cts-n-pu2 { |
85afd20e MZ |
631 | nvidia,pins = "pu2"; |
632 | nvidia,function = "uarta"; | |
633 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
634 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
635 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
636 | }; | |
26e19cdf | 637 | uart1-rts-n-pu3 { |
85afd20e MZ |
638 | nvidia,pins = "pu3"; |
639 | nvidia,function = "uarta"; | |
640 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
641 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
642 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
643 | }; | |
26e19cdf | 644 | uart3-cts-n-pa1 { /* DSR GPIO */ |
85afd20e MZ |
645 | nvidia,pins = "uart3_cts_n_pa1"; |
646 | nvidia,function = "gmi"; | |
647 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
648 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
649 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
650 | }; | |
26e19cdf | 651 | uart3-rts-n-pc0 { /* DTR GPIO */ |
85afd20e MZ |
652 | nvidia,pins = "uart3_rts_n_pc0"; |
653 | nvidia,function = "gmi"; | |
654 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
655 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
656 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
657 | }; | |
658 | ||
659 | /* Apalis UART2 */ | |
26e19cdf | 660 | uart2-txd-pc2 { |
85afd20e MZ |
661 | nvidia,pins = "uart2_txd_pc2"; |
662 | nvidia,function = "irda"; | |
663 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
664 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
665 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
666 | }; | |
26e19cdf | 667 | uart2-rxd-pc3 { |
85afd20e MZ |
668 | nvidia,pins = "uart2_rxd_pc3"; |
669 | nvidia,function = "irda"; | |
670 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
671 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
672 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
673 | }; | |
26e19cdf | 674 | uart2-cts-n-pj5 { |
85afd20e MZ |
675 | nvidia,pins = "uart2_cts_n_pj5"; |
676 | nvidia,function = "uartb"; | |
677 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
678 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
679 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
680 | }; | |
26e19cdf | 681 | uart2-rts-n-pj6 { |
85afd20e MZ |
682 | nvidia,pins = "uart2_rts_n_pj6"; |
683 | nvidia,function = "uartb"; | |
684 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
685 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
686 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
687 | }; | |
688 | ||
689 | /* Apalis UART3 */ | |
26e19cdf | 690 | uart3-txd-pw6 { |
85afd20e MZ |
691 | nvidia,pins = "uart3_txd_pw6"; |
692 | nvidia,function = "uartc"; | |
693 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
694 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
695 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
696 | }; | |
26e19cdf | 697 | uart3-rxd-pw7 { |
85afd20e MZ |
698 | nvidia,pins = "uart3_rxd_pw7"; |
699 | nvidia,function = "uartc"; | |
700 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
701 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
702 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
703 | }; | |
704 | ||
705 | /* Apalis UART4 */ | |
26e19cdf | 706 | uart4-rxd-pb0 { |
85afd20e MZ |
707 | nvidia,pins = "pb0"; |
708 | nvidia,function = "uartd"; | |
709 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
710 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
711 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
712 | }; | |
26e19cdf | 713 | uart4-txd-pj7 { |
85afd20e MZ |
714 | nvidia,pins = "pj7"; |
715 | nvidia,function = "uartd"; | |
716 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
717 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
718 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
719 | }; | |
720 | ||
721 | /* Apalis USBH_EN */ | |
26e19cdf | 722 | usb-vbus-en1-pn5 { |
85afd20e MZ |
723 | nvidia,pins = "usb_vbus_en1_pn5"; |
724 | nvidia,function = "rsvd2"; | |
725 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
726 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
727 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
728 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
729 | }; | |
730 | ||
731 | /* Apalis USBH_OC# */ | |
732 | pbb0 { | |
733 | nvidia,pins = "pbb0"; | |
734 | nvidia,function = "vgp6"; | |
735 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
736 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
737 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
738 | }; | |
739 | ||
740 | /* Apalis USBO1_EN */ | |
26e19cdf | 741 | usb-vbus-en0-pn4 { |
85afd20e MZ |
742 | nvidia,pins = "usb_vbus_en0_pn4"; |
743 | nvidia,function = "rsvd2"; | |
744 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
745 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
746 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
747 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
748 | }; | |
749 | ||
750 | /* Apalis USBO1_OC# */ | |
751 | pbb4 { | |
752 | nvidia,pins = "pbb4"; | |
753 | nvidia,function = "vgp4"; | |
754 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
755 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
756 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
757 | }; | |
758 | ||
759 | /* Apalis WAKE1_MICO */ | |
26e19cdf | 760 | pex-wake-n-pdd3 { |
85afd20e MZ |
761 | nvidia,pins = "pex_wake_n_pdd3"; |
762 | nvidia,function = "rsvd2"; | |
763 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
764 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
765 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
766 | }; | |
767 | ||
768 | /* CORE_PWR_REQ */ | |
26e19cdf | 769 | core-pwr-req { |
85afd20e MZ |
770 | nvidia,pins = "core_pwr_req"; |
771 | nvidia,function = "pwron"; | |
772 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
773 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
774 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
775 | }; | |
776 | ||
777 | /* CPU_PWR_REQ */ | |
26e19cdf | 778 | cpu-pwr-req { |
85afd20e MZ |
779 | nvidia,pins = "cpu_pwr_req"; |
780 | nvidia,function = "cpu"; | |
781 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
782 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
783 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
784 | }; | |
785 | ||
786 | /* DVFS */ | |
26e19cdf | 787 | dvfs-pwm-px0 { |
85afd20e MZ |
788 | nvidia,pins = "dvfs_pwm_px0"; |
789 | nvidia,function = "cldvfs"; | |
790 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
791 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
792 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
793 | }; | |
26e19cdf | 794 | dvfs-clk-px2 { |
85afd20e MZ |
795 | nvidia,pins = "dvfs_clk_px2"; |
796 | nvidia,function = "cldvfs"; | |
797 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
798 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
799 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
800 | }; | |
801 | ||
802 | /* eMMC */ | |
26e19cdf | 803 | sdmmc4-dat0-paa0 { |
85afd20e MZ |
804 | nvidia,pins = "sdmmc4_dat0_paa0"; |
805 | nvidia,function = "sdmmc4"; | |
806 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
807 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
808 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
809 | }; | |
26e19cdf | 810 | sdmmc4-dat1-paa1 { |
85afd20e MZ |
811 | nvidia,pins = "sdmmc4_dat1_paa1"; |
812 | nvidia,function = "sdmmc4"; | |
813 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
814 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
815 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
816 | }; | |
26e19cdf | 817 | sdmmc4-dat2-paa2 { |
85afd20e MZ |
818 | nvidia,pins = "sdmmc4_dat2_paa2"; |
819 | nvidia,function = "sdmmc4"; | |
820 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
821 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
822 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
823 | }; | |
26e19cdf | 824 | sdmmc4-dat3-paa3 { |
85afd20e MZ |
825 | nvidia,pins = "sdmmc4_dat3_paa3"; |
826 | nvidia,function = "sdmmc4"; | |
827 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
828 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
829 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
830 | }; | |
26e19cdf | 831 | sdmmc4-dat4-paa4 { |
85afd20e MZ |
832 | nvidia,pins = "sdmmc4_dat4_paa4"; |
833 | nvidia,function = "sdmmc4"; | |
834 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
835 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
836 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
837 | }; | |
26e19cdf | 838 | sdmmc4-dat5-paa5 { |
85afd20e MZ |
839 | nvidia,pins = "sdmmc4_dat5_paa5"; |
840 | nvidia,function = "sdmmc4"; | |
841 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
842 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
843 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
844 | }; | |
26e19cdf | 845 | sdmmc4-dat6-paa6 { |
85afd20e MZ |
846 | nvidia,pins = "sdmmc4_dat6_paa6"; |
847 | nvidia,function = "sdmmc4"; | |
848 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
849 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
850 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
851 | }; | |
26e19cdf | 852 | sdmmc4-dat7-paa7 { |
85afd20e MZ |
853 | nvidia,pins = "sdmmc4_dat7_paa7"; |
854 | nvidia,function = "sdmmc4"; | |
855 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
856 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
857 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
858 | }; | |
26e19cdf | 859 | sdmmc4-clk-pcc4 { |
85afd20e MZ |
860 | nvidia,pins = "sdmmc4_clk_pcc4"; |
861 | nvidia,function = "sdmmc4"; | |
862 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
863 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
864 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
865 | }; | |
26e19cdf | 866 | sdmmc4-cmd-pt7 { |
85afd20e MZ |
867 | nvidia,pins = "sdmmc4_cmd_pt7"; |
868 | nvidia,function = "sdmmc4"; | |
869 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
870 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
871 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
872 | }; | |
873 | ||
874 | /* JTAG_RTCK */ | |
26e19cdf | 875 | jtag-rtck { |
85afd20e MZ |
876 | nvidia,pins = "jtag_rtck"; |
877 | nvidia,function = "rtck"; | |
878 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
879 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
880 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
881 | }; | |
882 | ||
883 | /* LAN_DEV_OFF# */ | |
26e19cdf | 884 | ulpi-data5-po6 { |
85afd20e MZ |
885 | nvidia,pins = "ulpi_data5_po6"; |
886 | nvidia,function = "ulpi"; | |
887 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
888 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
889 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
890 | }; | |
891 | ||
892 | /* LAN_RESET# */ | |
26e19cdf | 893 | kb-row10-ps2 { |
85afd20e MZ |
894 | nvidia,pins = "kb_row10_ps2"; |
895 | nvidia,function = "rsvd2"; | |
896 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
897 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
898 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
899 | }; | |
900 | ||
901 | /* LAN_WAKE# */ | |
26e19cdf | 902 | ulpi-data4-po5 { |
85afd20e MZ |
903 | nvidia,pins = "ulpi_data4_po5"; |
904 | nvidia,function = "ulpi"; | |
905 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
906 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
907 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
908 | }; | |
909 | ||
910 | /* MCU_INT1# */ | |
911 | pk2 { | |
912 | nvidia,pins = "pk2"; | |
913 | nvidia,function = "rsvd1"; | |
914 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
915 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
916 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
917 | }; | |
918 | ||
919 | /* MCU_INT2# */ | |
920 | pj2 { | |
921 | nvidia,pins = "pj2"; | |
922 | nvidia,function = "rsvd1"; | |
923 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
924 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
925 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
926 | }; | |
927 | ||
928 | /* MCU_INT3# */ | |
929 | pi5 { | |
930 | nvidia,pins = "pi5"; | |
931 | nvidia,function = "rsvd2"; | |
932 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
933 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
934 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
935 | }; | |
936 | ||
937 | /* MCU_INT4# */ | |
938 | pj0 { | |
939 | nvidia,pins = "pj0"; | |
940 | nvidia,function = "rsvd1"; | |
941 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
942 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
943 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
944 | }; | |
945 | ||
946 | /* MCU_RESET */ | |
947 | pbb6 { | |
948 | nvidia,pins = "pbb6"; | |
949 | nvidia,function = "rsvd2"; | |
950 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
951 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
952 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
953 | }; | |
954 | ||
955 | /* MCU SPI */ | |
26e19cdf | 956 | gpio-x4-aud-px4 { |
85afd20e MZ |
957 | nvidia,pins = "gpio_x4_aud_px4"; |
958 | nvidia,function = "spi2"; | |
959 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
960 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
961 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
962 | }; | |
26e19cdf | 963 | gpio-x5-aud-px5 { |
85afd20e MZ |
964 | nvidia,pins = "gpio_x5_aud_px5"; |
965 | nvidia,function = "spi2"; | |
966 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
967 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
968 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
969 | }; | |
26e19cdf | 970 | gpio-x6-aud-px6 { /* MCU_CS */ |
85afd20e MZ |
971 | nvidia,pins = "gpio_x6_aud_px6"; |
972 | nvidia,function = "spi2"; | |
973 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
974 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
975 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
976 | }; | |
26e19cdf | 977 | gpio-x7-aud-px7 { |
85afd20e MZ |
978 | nvidia,pins = "gpio_x7_aud_px7"; |
979 | nvidia,function = "spi2"; | |
980 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
981 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
982 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
983 | }; | |
26e19cdf | 984 | gpio-w2-aud-pw2 { /* MCU_CSEZP */ |
85afd20e MZ |
985 | nvidia,pins = "gpio_w2_aud_pw2"; |
986 | nvidia,function = "spi2"; | |
987 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
988 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
989 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
990 | }; | |
991 | ||
992 | /* PMIC_CLK_32K */ | |
26e19cdf | 993 | clk-32k-in { |
85afd20e MZ |
994 | nvidia,pins = "clk_32k_in"; |
995 | nvidia,function = "clk"; | |
996 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
997 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
998 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
999 | }; | |
1000 | ||
1001 | /* PMIC_CPU_OC_INT */ | |
26e19cdf | 1002 | clk-32k-out-pa0 { |
85afd20e MZ |
1003 | nvidia,pins = "clk_32k_out_pa0"; |
1004 | nvidia,function = "soc"; | |
1005 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1006 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1007 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1008 | }; | |
1009 | ||
1010 | /* PWR_I2C */ | |
26e19cdf | 1011 | pwr-i2c-scl-pz6 { |
85afd20e MZ |
1012 | nvidia,pins = "pwr_i2c_scl_pz6"; |
1013 | nvidia,function = "i2cpwr"; | |
1014 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1015 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1016 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1017 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1018 | }; | |
26e19cdf | 1019 | pwr-i2c-sda-pz7 { |
85afd20e MZ |
1020 | nvidia,pins = "pwr_i2c_sda_pz7"; |
1021 | nvidia,function = "i2cpwr"; | |
1022 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1023 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1024 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1025 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1026 | }; | |
1027 | ||
1028 | /* PWR_INT_N */ | |
26e19cdf | 1029 | pwr-int-n { |
85afd20e MZ |
1030 | nvidia,pins = "pwr_int_n"; |
1031 | nvidia,function = "pmi"; | |
1032 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1033 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1034 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1035 | }; | |
1036 | ||
1037 | /* RESET_MOCI_CTRL */ | |
1038 | pu4 { | |
1039 | nvidia,pins = "pu4"; | |
1040 | nvidia,function = "gmi"; | |
1041 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1042 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1043 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1044 | }; | |
1045 | ||
1046 | /* RESET_OUT_N */ | |
26e19cdf | 1047 | reset-out-n { |
85afd20e MZ |
1048 | nvidia,pins = "reset_out_n"; |
1049 | nvidia,function = "reset_out_n"; | |
1050 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1051 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1052 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1053 | }; | |
1054 | ||
1055 | /* SHIFT_CTRL_DIR_IN */ | |
26e19cdf | 1056 | kb-row0-pr0 { |
85afd20e MZ |
1057 | nvidia,pins = "kb_row0_pr0"; |
1058 | nvidia,function = "rsvd2"; | |
1059 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1060 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1061 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1062 | }; | |
26e19cdf | 1063 | kb-row1-pr1 { |
85afd20e MZ |
1064 | nvidia,pins = "kb_row1_pr1"; |
1065 | nvidia,function = "rsvd2"; | |
1066 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1067 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1068 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1069 | }; | |
1070 | ||
1071 | /* Configure level-shifter as output for HDA */ | |
26e19cdf | 1072 | kb-row11-ps3 { |
85afd20e MZ |
1073 | nvidia,pins = "kb_row11_ps3"; |
1074 | nvidia,function = "rsvd2"; | |
1075 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1076 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1077 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1078 | }; | |
1079 | ||
1080 | /* SHIFT_CTRL_DIR_OUT */ | |
26e19cdf | 1081 | kb-col5-pq5 { |
85afd20e MZ |
1082 | nvidia,pins = "kb_col5_pq5"; |
1083 | nvidia,function = "rsvd2"; | |
1084 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1085 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1086 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1087 | }; | |
26e19cdf | 1088 | kb-col6-pq6 { |
85afd20e MZ |
1089 | nvidia,pins = "kb_col6_pq6"; |
1090 | nvidia,function = "rsvd2"; | |
1091 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1092 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1093 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1094 | }; | |
26e19cdf | 1095 | kb-col7-pq7 { |
85afd20e MZ |
1096 | nvidia,pins = "kb_col7_pq7"; |
1097 | nvidia,function = "rsvd2"; | |
1098 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1099 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1100 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1101 | }; | |
1102 | ||
1103 | /* SHIFT_CTRL_OE */ | |
26e19cdf | 1104 | kb-col0-pq0 { |
85afd20e MZ |
1105 | nvidia,pins = "kb_col0_pq0"; |
1106 | nvidia,function = "rsvd2"; | |
1107 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1108 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1109 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1110 | }; | |
26e19cdf | 1111 | kb-col1-pq1 { |
85afd20e MZ |
1112 | nvidia,pins = "kb_col1_pq1"; |
1113 | nvidia,function = "rsvd2"; | |
1114 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1115 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1116 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1117 | }; | |
26e19cdf | 1118 | kb-col2-pq2 { |
85afd20e MZ |
1119 | nvidia,pins = "kb_col2_pq2"; |
1120 | nvidia,function = "rsvd2"; | |
1121 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1122 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1123 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1124 | }; | |
26e19cdf | 1125 | kb-col4-pq4 { |
85afd20e MZ |
1126 | nvidia,pins = "kb_col4_pq4"; |
1127 | nvidia,function = "kbc"; | |
1128 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1129 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1130 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1131 | }; | |
26e19cdf | 1132 | kb-row2-pr2 { |
85afd20e MZ |
1133 | nvidia,pins = "kb_row2_pr2"; |
1134 | nvidia,function = "rsvd2"; | |
1135 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1136 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1137 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1138 | }; | |
1139 | ||
02888f8b | 1140 | /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */ |
85afd20e MZ |
1141 | pi6 { |
1142 | nvidia,pins = "pi6"; | |
1143 | nvidia,function = "rsvd1"; | |
02888f8b | 1144 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
85afd20e MZ |
1145 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
1146 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1147 | }; | |
1148 | ||
1149 | /* TOUCH_INT */ | |
26e19cdf | 1150 | gpio-w3-aud-pw3 { |
85afd20e MZ |
1151 | nvidia,pins = "gpio_w3_aud_pw3"; |
1152 | nvidia,function = "spi6"; | |
1153 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1154 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1155 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1156 | }; | |
1157 | ||
1158 | pc7 { /* NC */ | |
1159 | nvidia,pins = "pc7"; | |
1160 | nvidia,function = "rsvd1"; | |
1161 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1162 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1163 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1164 | }; | |
1165 | pg0 { /* NC */ | |
1166 | nvidia,pins = "pg0"; | |
1167 | nvidia,function = "rsvd1"; | |
1168 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1169 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1170 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1171 | }; | |
1172 | pg1 { /* NC */ | |
1173 | nvidia,pins = "pg1"; | |
1174 | nvidia,function = "rsvd1"; | |
1175 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1176 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1177 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1178 | }; | |
1179 | pg2 { /* NC */ | |
1180 | nvidia,pins = "pg2"; | |
1181 | nvidia,function = "rsvd1"; | |
1182 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1183 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1184 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1185 | }; | |
1186 | pg3 { /* NC */ | |
1187 | nvidia,pins = "pg3"; | |
1188 | nvidia,function = "rsvd1"; | |
1189 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1190 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1191 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1192 | }; | |
1193 | pg4 { /* NC */ | |
1194 | nvidia,pins = "pg4"; | |
1195 | nvidia,function = "rsvd1"; | |
1196 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1197 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1198 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1199 | }; | |
1200 | ph4 { /* NC */ | |
1201 | nvidia,pins = "ph4"; | |
1202 | nvidia,function = "rsvd2"; | |
1203 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1204 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1205 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1206 | }; | |
1207 | ph5 { /* NC */ | |
1208 | nvidia,pins = "ph5"; | |
1209 | nvidia,function = "rsvd2"; | |
1210 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1211 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1212 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1213 | }; | |
1214 | ph6 { /* NC */ | |
1215 | nvidia,pins = "ph6"; | |
1216 | nvidia,function = "gmi"; | |
1217 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1218 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1219 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1220 | }; | |
1221 | ph7 { /* NC */ | |
1222 | nvidia,pins = "ph7"; | |
1223 | nvidia,function = "gmi"; | |
1224 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1225 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1226 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1227 | }; | |
1228 | pi0 { /* NC */ | |
1229 | nvidia,pins = "pi0"; | |
1230 | nvidia,function = "rsvd1"; | |
1231 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1232 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1233 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1234 | }; | |
1235 | pi1 { /* NC */ | |
1236 | nvidia,pins = "pi1"; | |
1237 | nvidia,function = "rsvd1"; | |
1238 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1239 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1240 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1241 | }; | |
1242 | pi2 { /* NC */ | |
1243 | nvidia,pins = "pi2"; | |
1244 | nvidia,function = "rsvd4"; | |
1245 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1246 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1247 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1248 | }; | |
1249 | pi4 { /* NC */ | |
1250 | nvidia,pins = "pi4"; | |
1251 | nvidia,function = "gmi"; | |
1252 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1253 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1254 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1255 | }; | |
1256 | pi7 { /* NC */ | |
1257 | nvidia,pins = "pi7"; | |
1258 | nvidia,function = "rsvd1"; | |
1259 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1260 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1261 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1262 | }; | |
1263 | pk0 { /* NC */ | |
1264 | nvidia,pins = "pk0"; | |
1265 | nvidia,function = "rsvd1"; | |
1266 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1267 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1268 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1269 | }; | |
1270 | pk1 { /* NC */ | |
1271 | nvidia,pins = "pk1"; | |
1272 | nvidia,function = "rsvd4"; | |
1273 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1274 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1275 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1276 | }; | |
1277 | pk3 { /* NC */ | |
1278 | nvidia,pins = "pk3"; | |
1279 | nvidia,function = "gmi"; | |
1280 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1281 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1282 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1283 | }; | |
1284 | pk4 { /* NC */ | |
1285 | nvidia,pins = "pk4"; | |
1286 | nvidia,function = "rsvd2"; | |
1287 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1288 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1289 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1290 | }; | |
26e19cdf | 1291 | dap1-fs-pn0 { /* NC */ |
85afd20e MZ |
1292 | nvidia,pins = "dap1_fs_pn0"; |
1293 | nvidia,function = "rsvd4"; | |
1294 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1295 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1296 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1297 | }; | |
26e19cdf | 1298 | dap1-din-pn1 { /* NC */ |
85afd20e MZ |
1299 | nvidia,pins = "dap1_din_pn1"; |
1300 | nvidia,function = "rsvd4"; | |
1301 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1302 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1303 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1304 | }; | |
26e19cdf | 1305 | dap1-sclk-pn3 { /* NC */ |
85afd20e MZ |
1306 | nvidia,pins = "dap1_sclk_pn3"; |
1307 | nvidia,function = "rsvd4"; | |
1308 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1309 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1310 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1311 | }; | |
26e19cdf | 1312 | ulpi-data7-po0 { /* NC */ |
85afd20e MZ |
1313 | nvidia,pins = "ulpi_data7_po0"; |
1314 | nvidia,function = "ulpi"; | |
1315 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1316 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1317 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1318 | }; | |
26e19cdf | 1319 | ulpi-data0-po1 { /* NC */ |
85afd20e MZ |
1320 | nvidia,pins = "ulpi_data0_po1"; |
1321 | nvidia,function = "ulpi"; | |
1322 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1323 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1324 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1325 | }; | |
26e19cdf | 1326 | ulpi-data1-po2 { /* NC */ |
85afd20e MZ |
1327 | nvidia,pins = "ulpi_data1_po2"; |
1328 | nvidia,function = "ulpi"; | |
1329 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1330 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1331 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1332 | }; | |
26e19cdf | 1333 | ulpi-data2-po3 { /* NC */ |
85afd20e MZ |
1334 | nvidia,pins = "ulpi_data2_po3"; |
1335 | nvidia,function = "ulpi"; | |
1336 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1337 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1338 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1339 | }; | |
26e19cdf | 1340 | ulpi-data3-po4 { /* NC */ |
85afd20e MZ |
1341 | nvidia,pins = "ulpi_data3_po4"; |
1342 | nvidia,function = "ulpi"; | |
1343 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1344 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1345 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1346 | }; | |
26e19cdf | 1347 | ulpi-data6-po7 { /* NC */ |
85afd20e MZ |
1348 | nvidia,pins = "ulpi_data6_po7"; |
1349 | nvidia,function = "ulpi"; | |
1350 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1351 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1352 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1353 | }; | |
26e19cdf | 1354 | dap4-fs-pp4 { /* NC */ |
85afd20e MZ |
1355 | nvidia,pins = "dap4_fs_pp4"; |
1356 | nvidia,function = "rsvd4"; | |
1357 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1358 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1359 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1360 | }; | |
26e19cdf | 1361 | dap4-din-pp5 { /* NC */ |
85afd20e MZ |
1362 | nvidia,pins = "dap4_din_pp5"; |
1363 | nvidia,function = "rsvd3"; | |
1364 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1365 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1366 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1367 | }; | |
26e19cdf | 1368 | dap4-dout-pp6 { /* NC */ |
85afd20e MZ |
1369 | nvidia,pins = "dap4_dout_pp6"; |
1370 | nvidia,function = "rsvd4"; | |
1371 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1372 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1373 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1374 | }; | |
26e19cdf | 1375 | dap4-sclk-pp7 { /* NC */ |
85afd20e MZ |
1376 | nvidia,pins = "dap4_sclk_pp7"; |
1377 | nvidia,function = "rsvd3"; | |
1378 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1379 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1380 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1381 | }; | |
26e19cdf | 1382 | kb-col3-pq3 { /* NC */ |
85afd20e MZ |
1383 | nvidia,pins = "kb_col3_pq3"; |
1384 | nvidia,function = "kbc"; | |
1385 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1386 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1387 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1388 | }; | |
26e19cdf | 1389 | kb-row3-pr3 { /* NC */ |
85afd20e MZ |
1390 | nvidia,pins = "kb_row3_pr3"; |
1391 | nvidia,function = "kbc"; | |
1392 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1393 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1394 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1395 | }; | |
26e19cdf | 1396 | kb-row4-pr4 { /* NC */ |
85afd20e MZ |
1397 | nvidia,pins = "kb_row4_pr4"; |
1398 | nvidia,function = "rsvd3"; | |
1399 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1400 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1401 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1402 | }; | |
26e19cdf | 1403 | kb-row5-pr5 { /* NC */ |
85afd20e MZ |
1404 | nvidia,pins = "kb_row5_pr5"; |
1405 | nvidia,function = "rsvd3"; | |
1406 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1407 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1408 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1409 | }; | |
26e19cdf | 1410 | kb-row6-pr6 { /* NC */ |
85afd20e MZ |
1411 | nvidia,pins = "kb_row6_pr6"; |
1412 | nvidia,function = "kbc"; | |
1413 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1414 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1415 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1416 | }; | |
26e19cdf | 1417 | kb-row7-pr7 { /* NC */ |
85afd20e MZ |
1418 | nvidia,pins = "kb_row7_pr7"; |
1419 | nvidia,function = "rsvd2"; | |
1420 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1421 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1422 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1423 | }; | |
26e19cdf | 1424 | kb-row8-ps0 { /* NC */ |
85afd20e MZ |
1425 | nvidia,pins = "kb_row8_ps0"; |
1426 | nvidia,function = "rsvd2"; | |
1427 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1428 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1429 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1430 | }; | |
26e19cdf | 1431 | kb-row9-ps1 { /* NC */ |
85afd20e MZ |
1432 | nvidia,pins = "kb_row9_ps1"; |
1433 | nvidia,function = "rsvd2"; | |
1434 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1435 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1436 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1437 | }; | |
26e19cdf | 1438 | kb-row12-ps4 { /* NC */ |
85afd20e MZ |
1439 | nvidia,pins = "kb_row12_ps4"; |
1440 | nvidia,function = "rsvd2"; | |
1441 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1442 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1443 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1444 | }; | |
26e19cdf | 1445 | kb-row13-ps5 { /* NC */ |
85afd20e MZ |
1446 | nvidia,pins = "kb_row13_ps5"; |
1447 | nvidia,function = "rsvd2"; | |
1448 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1449 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1450 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1451 | }; | |
26e19cdf | 1452 | kb-row14-ps6 { /* NC */ |
85afd20e MZ |
1453 | nvidia,pins = "kb_row14_ps6"; |
1454 | nvidia,function = "rsvd2"; | |
1455 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1456 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1457 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1458 | }; | |
26e19cdf | 1459 | kb-row15-ps7 { /* NC */ |
85afd20e MZ |
1460 | nvidia,pins = "kb_row15_ps7"; |
1461 | nvidia,function = "rsvd3"; | |
1462 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1463 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1464 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1465 | }; | |
26e19cdf | 1466 | kb-row16-pt0 { /* NC */ |
85afd20e MZ |
1467 | nvidia,pins = "kb_row16_pt0"; |
1468 | nvidia,function = "rsvd2"; | |
1469 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1470 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1471 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1472 | }; | |
26e19cdf | 1473 | kb-row17-pt1 { /* NC */ |
85afd20e MZ |
1474 | nvidia,pins = "kb_row17_pt1"; |
1475 | nvidia,function = "rsvd2"; | |
1476 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1477 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1478 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1479 | }; | |
1480 | pu5 { /* NC */ | |
1481 | nvidia,pins = "pu5"; | |
1482 | nvidia,function = "gmi"; | |
1483 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1484 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1485 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1486 | }; | |
1487 | pv0 { /* NC */ | |
1488 | nvidia,pins = "pv0"; | |
1489 | nvidia,function = "rsvd1"; | |
1490 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1491 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1492 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1493 | }; | |
1494 | pv1 { /* NC */ | |
1495 | nvidia,pins = "pv1"; | |
1496 | nvidia,function = "rsvd1"; | |
1497 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1498 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1499 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1500 | }; | |
26e19cdf | 1501 | gpio-x1-aud-px1 { /* NC */ |
85afd20e MZ |
1502 | nvidia,pins = "gpio_x1_aud_px1"; |
1503 | nvidia,function = "rsvd2"; | |
1504 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1505 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1506 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1507 | }; | |
26e19cdf | 1508 | gpio-x3-aud-px3 { /* NC */ |
85afd20e MZ |
1509 | nvidia,pins = "gpio_x3_aud_px3"; |
1510 | nvidia,function = "rsvd4"; | |
1511 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1512 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1513 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1514 | }; | |
1515 | pbb7 { /* NC */ | |
1516 | nvidia,pins = "pbb7"; | |
1517 | nvidia,function = "rsvd2"; | |
1518 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1519 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1520 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1521 | }; | |
1522 | pcc1 { /* NC */ | |
1523 | nvidia,pins = "pcc1"; | |
1524 | nvidia,function = "rsvd2"; | |
1525 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1526 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1527 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1528 | }; | |
1529 | pcc2 { /* NC */ | |
1530 | nvidia,pins = "pcc2"; | |
1531 | nvidia,function = "rsvd2"; | |
1532 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1533 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1534 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1535 | }; | |
26e19cdf | 1536 | clk3-req-pee1 { /* NC */ |
85afd20e MZ |
1537 | nvidia,pins = "clk3_req_pee1"; |
1538 | nvidia,function = "rsvd2"; | |
1539 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1540 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1541 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1542 | }; | |
26e19cdf | 1543 | dap-mclk1-req-pee2 { /* NC */ |
85afd20e MZ |
1544 | nvidia,pins = "dap_mclk1_req_pee2"; |
1545 | nvidia,function = "rsvd4"; | |
1546 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1547 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1548 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1549 | }; | |
5142bd65 MZ |
1550 | /* |
1551 | * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output | |
1552 | * driver enabled aka not tristated and input driver | |
1553 | * enabled as well as it features some magic properties | |
1554 | * even though the external loopback is disabled and the | |
1555 | * internal loopback used as per | |
1556 | * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 | |
1557 | * bits being set to 0xfffd according to the TRM! | |
1558 | */ | |
26e19cdf | 1559 | sdmmc3-clk-lb-out-pee4 { /* NC */ |
5142bd65 MZ |
1560 | nvidia,pins = "sdmmc3_clk_lb_out_pee4"; |
1561 | nvidia,function = "sdmmc3"; | |
1562 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1563 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1564 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1565 | }; | |
85afd20e MZ |
1566 | }; |
1567 | }; | |
1568 | ||
1569 | serial@70006040 { | |
b036a75a | 1570 | compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; |
85afd20e MZ |
1571 | }; |
1572 | ||
1573 | serial@70006200 { | |
b036a75a | 1574 | compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; |
85afd20e MZ |
1575 | }; |
1576 | ||
1577 | serial@70006300 { | |
b036a75a | 1578 | compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; |
85afd20e MZ |
1579 | }; |
1580 | ||
1581 | hdmi_ddc: i2c@7000c400 { | |
1c3389e6 | 1582 | clock-frequency = <10000>; |
85afd20e MZ |
1583 | }; |
1584 | ||
1585 | /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ | |
1586 | i2c@7000d000 { | |
1587 | status = "okay"; | |
1588 | clock-frequency = <400000>; | |
1589 | ||
1590 | /* SGTL5000 audio codec */ | |
5e8a724d | 1591 | sgtl5000: codec@a { |
85afd20e MZ |
1592 | compatible = "fsl,sgtl5000"; |
1593 | reg = <0x0a>; | |
8c3a9d21 MZ |
1594 | VDDA-supply = <®_module_3v3_audio>; |
1595 | VDDD-supply = <®_1v8_vddio>; | |
1bef3a57 | 1596 | VDDIO-supply = <®_1v8_vddio>; |
85afd20e MZ |
1597 | clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; |
1598 | }; | |
1599 | ||
1600 | pmic: pmic@40 { | |
1601 | compatible = "ams,as3722"; | |
1602 | reg = <0x40>; | |
1603 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; | |
85afd20e | 1604 | ams,system-power-controller; |
85afd20e MZ |
1605 | #interrupt-cells = <2>; |
1606 | interrupt-controller; | |
85afd20e MZ |
1607 | gpio-controller; |
1608 | #gpio-cells = <2>; | |
85afd20e MZ |
1609 | pinctrl-names = "default"; |
1610 | pinctrl-0 = <&as3722_default>; | |
1611 | ||
1612 | as3722_default: pinmux { | |
26e19cdf | 1613 | gpio2-7 { |
85afd20e MZ |
1614 | pins = "gpio2", /* PWR_EN_+V3.3 */ |
1615 | "gpio7"; /* +V1.6_LPO */ | |
1616 | function = "gpio"; | |
1617 | bias-pull-up; | |
1618 | }; | |
1619 | ||
26e19cdf | 1620 | gpio0-1-3-4-5-6 { |
405698f0 MZ |
1621 | pins = "gpio0", "gpio1", "gpio3", |
1622 | "gpio4", "gpio5", "gpio6"; | |
85afd20e MZ |
1623 | bias-high-impedance; |
1624 | }; | |
1625 | }; | |
1626 | ||
1627 | regulators { | |
1bef3a57 MZ |
1628 | vsup-sd2-supply = <®_module_3v3>; |
1629 | vsup-sd3-supply = <®_module_3v3>; | |
1630 | vsup-sd4-supply = <®_module_3v3>; | |
1631 | vsup-sd5-supply = <®_module_3v3>; | |
1632 | vin-ldo0-supply = <®_1v35_vddio_ddr>; | |
1633 | vin-ldo1-6-supply = <®_module_3v3>; | |
1634 | vin-ldo2-5-7-supply = <®_1v8_vddio>; | |
1635 | vin-ldo3-4-supply = <®_module_3v3>; | |
1636 | vin-ldo9-10-supply = <®_module_3v3>; | |
1637 | vin-ldo11-supply = <®_module_3v3>; | |
1638 | ||
1639 | reg_vdd_cpu: sd0 { | |
85afd20e MZ |
1640 | regulator-name = "+VDD_CPU_AP"; |
1641 | regulator-min-microvolt = <700000>; | |
1642 | regulator-max-microvolt = <1400000>; | |
1643 | regulator-min-microamp = <3500000>; | |
1644 | regulator-max-microamp = <3500000>; | |
1645 | regulator-always-on; | |
1646 | regulator-boot-on; | |
1647 | ams,ext-control = <2>; | |
1648 | }; | |
1649 | ||
1650 | sd1 { | |
1651 | regulator-name = "+VDD_CORE"; | |
1652 | regulator-min-microvolt = <700000>; | |
1653 | regulator-max-microvolt = <1350000>; | |
1654 | regulator-min-microamp = <2500000>; | |
1655 | regulator-max-microamp = <4000000>; | |
1656 | regulator-always-on; | |
1657 | regulator-boot-on; | |
1658 | ams,ext-control = <1>; | |
1659 | }; | |
1660 | ||
1bef3a57 | 1661 | reg_1v35_vddio_ddr: sd2 { |
85afd20e MZ |
1662 | regulator-name = |
1663 | "+V1.35_VDDIO_DDR(sd2)"; | |
1664 | regulator-min-microvolt = <1350000>; | |
1665 | regulator-max-microvolt = <1350000>; | |
1666 | regulator-always-on; | |
1667 | regulator-boot-on; | |
1668 | }; | |
1669 | ||
1670 | sd3 { | |
1671 | regulator-name = | |
1672 | "+V1.35_VDDIO_DDR(sd3)"; | |
1673 | regulator-min-microvolt = <1350000>; | |
1674 | regulator-max-microvolt = <1350000>; | |
1675 | regulator-always-on; | |
1676 | regulator-boot-on; | |
1677 | }; | |
1678 | ||
1bef3a57 | 1679 | reg_1v05_vdd: sd4 { |
85afd20e MZ |
1680 | regulator-name = "+V1.05"; |
1681 | regulator-min-microvolt = <1050000>; | |
1682 | regulator-max-microvolt = <1050000>; | |
1683 | }; | |
1684 | ||
1bef3a57 | 1685 | reg_1v8_vddio: sd5 { |
85afd20e MZ |
1686 | regulator-name = "+V1.8"; |
1687 | regulator-min-microvolt = <1800000>; | |
1688 | regulator-max-microvolt = <1800000>; | |
1689 | regulator-boot-on; | |
1690 | regulator-always-on; | |
1691 | }; | |
1692 | ||
1bef3a57 | 1693 | reg_vdd_gpu: sd6 { |
85afd20e MZ |
1694 | regulator-name = "+VDD_GPU_AP"; |
1695 | regulator-min-microvolt = <650000>; | |
1696 | regulator-max-microvolt = <1200000>; | |
1697 | regulator-min-microamp = <3500000>; | |
1698 | regulator-max-microamp = <3500000>; | |
1699 | regulator-boot-on; | |
1700 | regulator-always-on; | |
1701 | }; | |
1702 | ||
1bef3a57 | 1703 | reg_1v05_avdd: ldo0 { |
85afd20e MZ |
1704 | regulator-name = "+V1.05_AVDD"; |
1705 | regulator-min-microvolt = <1050000>; | |
1706 | regulator-max-microvolt = <1050000>; | |
1707 | regulator-boot-on; | |
1708 | regulator-always-on; | |
1709 | ams,ext-control = <1>; | |
1710 | }; | |
1711 | ||
1712 | vddio_sdmmc1: ldo1 { | |
1713 | regulator-name = "VDDIO_SDMMC1"; | |
1714 | regulator-min-microvolt = <1800000>; | |
1715 | regulator-max-microvolt = <3300000>; | |
1716 | }; | |
1717 | ||
1718 | ldo2 { | |
1719 | regulator-name = "+V1.2"; | |
1720 | regulator-min-microvolt = <1200000>; | |
1721 | regulator-max-microvolt = <1200000>; | |
1722 | regulator-boot-on; | |
1723 | regulator-always-on; | |
1724 | }; | |
1725 | ||
1726 | ldo3 { | |
1727 | regulator-name = "+V1.05_RTC"; | |
1728 | regulator-min-microvolt = <1000000>; | |
1729 | regulator-max-microvolt = <1000000>; | |
1730 | regulator-boot-on; | |
1731 | regulator-always-on; | |
1732 | ams,enable-tracking; | |
1733 | }; | |
1734 | ||
1735 | /* 1.8V for LVDS, 3.3V for eDP */ | |
1736 | ldo4 { | |
1737 | regulator-name = "AVDD_LVDS0_PLL"; | |
1738 | regulator-min-microvolt = <1800000>; | |
1739 | regulator-max-microvolt = <1800000>; | |
1740 | }; | |
1741 | ||
1742 | /* LDO5 not used */ | |
1743 | ||
1744 | vddio_sdmmc3: ldo6 { | |
1745 | regulator-name = "VDDIO_SDMMC3"; | |
1746 | regulator-min-microvolt = <1800000>; | |
1747 | regulator-max-microvolt = <3300000>; | |
1748 | }; | |
1749 | ||
1750 | /* LDO7 not used */ | |
1751 | ||
1752 | ldo9 { | |
1753 | regulator-name = "+V3.3_ETH(ldo9)"; | |
1754 | regulator-min-microvolt = <3300000>; | |
1755 | regulator-max-microvolt = <3300000>; | |
1756 | regulator-always-on; | |
1757 | }; | |
1758 | ||
1759 | ldo10 { | |
1760 | regulator-name = "+V3.3_ETH(ldo10)"; | |
1761 | regulator-min-microvolt = <3300000>; | |
1762 | regulator-max-microvolt = <3300000>; | |
1763 | regulator-always-on; | |
1764 | }; | |
1765 | ||
1766 | ldo11 { | |
1767 | regulator-name = "+V1.8_VPP_FUSE"; | |
1768 | regulator-min-microvolt = <1800000>; | |
1769 | regulator-max-microvolt = <1800000>; | |
1770 | }; | |
1771 | }; | |
1772 | }; | |
1773 | ||
1774 | /* | |
1775 | * TMP451 temperature sensor | |
1776 | * Note: THERM_N directly connected to AS3722 PMIC THERM | |
1777 | */ | |
6253f885 | 1778 | temp-sensor@4c { |
85afd20e MZ |
1779 | compatible = "ti,tmp451"; |
1780 | reg = <0x4c>; | |
1781 | interrupt-parent = <&gpio>; | |
1782 | interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; | |
85afd20e | 1783 | #thermal-sensor-cells = <1>; |
8c3a9d21 | 1784 | vcc-supply = <®_module_3v3>; |
85afd20e MZ |
1785 | }; |
1786 | }; | |
1787 | ||
1788 | /* SPI2: MCU SPI */ | |
1789 | spi@7000d600 { | |
1790 | status = "okay"; | |
1791 | spi-max-frequency = <25000000>; | |
1792 | }; | |
1793 | ||
1794 | pmc@7000e400 { | |
1795 | nvidia,invert-interrupt; | |
1796 | nvidia,suspend-mode = <1>; | |
1797 | nvidia,cpu-pwr-good-time = <500>; | |
1798 | nvidia,cpu-pwr-off-time = <300>; | |
1799 | nvidia,core-pwr-good-time = <641 3845>; | |
1800 | nvidia,core-pwr-off-time = <61036>; | |
1801 | nvidia,core-power-req-active-high; | |
1802 | nvidia,sys-clock-req-active-high; | |
1803 | ||
1804 | /* Set power_off bit in ResetControl register of AS3722 PMIC */ | |
1805 | i2c-thermtrip { | |
1806 | nvidia,i2c-controller-id = <4>; | |
1807 | nvidia,bus-addr = <0x40>; | |
1808 | nvidia,reg-addr = <0x36>; | |
1809 | nvidia,reg-data = <0x2>; | |
1810 | }; | |
1811 | }; | |
1812 | ||
1813 | sata@70020000 { | |
1814 | phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; | |
1815 | phy-names = "sata-0"; | |
1bef3a57 MZ |
1816 | avdd-supply = <®_1v05_vdd>; |
1817 | hvdd-supply = <®_module_3v3>; | |
1818 | vddio-supply = <®_1v05_vdd>; | |
85afd20e MZ |
1819 | }; |
1820 | ||
1821 | usb@70090000 { | |
1822 | /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */ | |
1823 | phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, | |
1824 | <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, | |
1825 | <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, | |
1826 | <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, | |
1827 | <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; | |
1828 | phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; | |
1bef3a57 MZ |
1829 | avddio-pex-supply = <®_1v05_vdd>; |
1830 | avdd-pll-erefe-supply = <®_1v05_avdd>; | |
1831 | avdd-pll-utmip-supply = <®_1v8_vddio>; | |
1832 | avdd-usb-ss-pll-supply = <®_1v05_vdd>; | |
1833 | avdd-usb-supply = <®_module_3v3>; | |
1834 | dvddio-pex-supply = <®_1v05_vdd>; | |
1835 | hvdd-usb-ss-pll-e-supply = <®_module_3v3>; | |
1836 | hvdd-usb-ss-supply = <®_module_3v3>; | |
85afd20e MZ |
1837 | }; |
1838 | ||
1839 | padctl@7009f000 { | |
1840 | pads { | |
1841 | usb2 { | |
1842 | status = "okay"; | |
1843 | ||
1844 | lanes { | |
1845 | usb2-0 { | |
85afd20e | 1846 | status = "okay"; |
a945eae0 | 1847 | nvidia,function = "xusb"; |
85afd20e MZ |
1848 | }; |
1849 | ||
1850 | usb2-1 { | |
85afd20e | 1851 | status = "okay"; |
a945eae0 | 1852 | nvidia,function = "xusb"; |
85afd20e MZ |
1853 | }; |
1854 | ||
1855 | usb2-2 { | |
85afd20e | 1856 | status = "okay"; |
a945eae0 | 1857 | nvidia,function = "xusb"; |
85afd20e MZ |
1858 | }; |
1859 | }; | |
1860 | }; | |
1861 | ||
1862 | pcie { | |
1863 | status = "okay"; | |
1864 | ||
1865 | lanes { | |
1866 | pcie-0 { | |
85afd20e | 1867 | status = "okay"; |
a945eae0 | 1868 | nvidia,function = "usb3-ss"; |
85afd20e MZ |
1869 | }; |
1870 | ||
1871 | pcie-1 { | |
85afd20e | 1872 | status = "okay"; |
a945eae0 | 1873 | nvidia,function = "usb3-ss"; |
85afd20e MZ |
1874 | }; |
1875 | ||
1876 | pcie-2 { | |
85afd20e | 1877 | status = "okay"; |
a945eae0 | 1878 | nvidia,function = "pcie"; |
85afd20e MZ |
1879 | }; |
1880 | ||
1881 | pcie-3 { | |
85afd20e | 1882 | status = "okay"; |
a945eae0 | 1883 | nvidia,function = "pcie"; |
85afd20e MZ |
1884 | }; |
1885 | ||
1886 | pcie-4 { | |
85afd20e | 1887 | status = "okay"; |
a945eae0 | 1888 | nvidia,function = "pcie"; |
85afd20e MZ |
1889 | }; |
1890 | }; | |
1891 | }; | |
1892 | ||
1893 | sata { | |
1894 | status = "okay"; | |
1895 | ||
1896 | lanes { | |
1897 | sata-0 { | |
85afd20e | 1898 | status = "okay"; |
a945eae0 | 1899 | nvidia,function = "sata"; |
85afd20e MZ |
1900 | }; |
1901 | }; | |
1902 | }; | |
1903 | }; | |
1904 | ||
1905 | ports { | |
1906 | /* USBO1 */ | |
1907 | usb2-0 { | |
1908 | status = "okay"; | |
1909 | mode = "otg"; | |
85afd20e MZ |
1910 | vbus-supply = <®_usbo1_vbus>; |
1911 | }; | |
1912 | ||
1913 | /* USBH2 */ | |
1914 | usb2-1 { | |
1915 | status = "okay"; | |
1916 | mode = "host"; | |
85afd20e MZ |
1917 | vbus-supply = <®_usbh_vbus>; |
1918 | }; | |
1919 | ||
1920 | /* USBH4 */ | |
1921 | usb2-2 { | |
1922 | status = "okay"; | |
1923 | mode = "host"; | |
85afd20e MZ |
1924 | vbus-supply = <®_usbh_vbus>; |
1925 | }; | |
1926 | ||
1927 | usb3-0 { | |
85afd20e | 1928 | status = "okay"; |
a945eae0 | 1929 | nvidia,usb2-companion = <2>; |
8c3a9d21 | 1930 | vbus-supply = <®_usbh_vbus>; |
85afd20e MZ |
1931 | }; |
1932 | ||
1933 | usb3-1 { | |
85afd20e | 1934 | status = "okay"; |
a945eae0 | 1935 | nvidia,usb2-companion = <0>; |
8c3a9d21 | 1936 | vbus-supply = <®_usbo1_vbus>; |
85afd20e MZ |
1937 | }; |
1938 | }; | |
1939 | }; | |
1940 | ||
1941 | /* eMMC */ | |
1942 | sdhci@700b0600 { | |
1943 | status = "okay"; | |
1944 | bus-width = <8>; | |
1945 | non-removable; | |
fca051b0 MZ |
1946 | vmmc-supply = <®_module_3v3>; /* VCC */ |
1947 | vqmmc-supply = <®_1v8_vddio>; /* VCCQ */ | |
8be6e49a | 1948 | mmc-ddr-1_8v; |
85afd20e MZ |
1949 | }; |
1950 | ||
1951 | /* CPU DFLL clock */ | |
1952 | clock@70110000 { | |
1953 | status = "okay"; | |
85afd20e | 1954 | nvidia,i2c-fs-rate = <400000>; |
e0cffa9a | 1955 | vdd-cpu-supply = <®_vdd_cpu>; |
85afd20e MZ |
1956 | }; |
1957 | ||
1958 | ahub@70300000 { | |
1959 | i2s@70301200 { | |
1960 | status = "okay"; | |
1961 | }; | |
1962 | }; | |
1963 | ||
94c3847d MZ |
1964 | clk32k_in: osc3 { |
1965 | compatible = "fixed-clock"; | |
1966 | #clock-cells = <0>; | |
1967 | clock-frequency = <32768>; | |
85afd20e MZ |
1968 | }; |
1969 | ||
1970 | cpus { | |
1971 | cpu@0 { | |
1bef3a57 | 1972 | vdd-cpu-supply = <®_vdd_cpu>; |
85afd20e MZ |
1973 | }; |
1974 | }; | |
1975 | ||
1976 | reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { | |
1977 | compatible = "regulator-fixed"; | |
1978 | regulator-name = "+V1.05_AVDD_HDMI_PLL"; | |
1979 | regulator-min-microvolt = <1050000>; | |
1980 | regulator-max-microvolt = <1050000>; | |
1981 | gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; | |
1bef3a57 | 1982 | vin-supply = <®_1v05_vdd>; |
85afd20e MZ |
1983 | }; |
1984 | ||
1985 | reg_3v3_mxm: regulator-3v3-mxm { | |
1986 | compatible = "regulator-fixed"; | |
1987 | regulator-name = "+V3.3_MXM"; | |
1988 | regulator-min-microvolt = <3300000>; | |
1989 | regulator-max-microvolt = <3300000>; | |
1990 | regulator-always-on; | |
1991 | regulator-boot-on; | |
1992 | }; | |
1993 | ||
1bef3a57 MZ |
1994 | reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { |
1995 | compatible = "regulator-fixed"; | |
1996 | regulator-name = "+V3.3_AVDD_HDMI"; | |
1997 | regulator-min-microvolt = <3300000>; | |
1998 | regulator-max-microvolt = <3300000>; | |
1999 | vin-supply = <®_1v05_vdd>; | |
2000 | }; | |
2001 | ||
2002 | reg_module_3v3: regulator-module-3v3 { | |
85afd20e MZ |
2003 | compatible = "regulator-fixed"; |
2004 | regulator-name = "+V3.3"; | |
2005 | regulator-min-microvolt = <3300000>; | |
2006 | regulator-max-microvolt = <3300000>; | |
2007 | regulator-always-on; | |
2008 | regulator-boot-on; | |
2009 | /* PWR_EN_+V3.3 */ | |
2010 | gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; | |
2011 | enable-active-high; | |
2012 | vin-supply = <®_3v3_mxm>; | |
2013 | }; | |
2014 | ||
8c3a9d21 MZ |
2015 | reg_module_3v3_audio: regulator-module-3v3-audio { |
2016 | compatible = "regulator-fixed"; | |
2017 | regulator-name = "+V3.3_AUDIO_AVDD_S"; | |
2018 | regulator-min-microvolt = <3300000>; | |
2019 | regulator-max-microvolt = <3300000>; | |
2020 | regulator-always-on; | |
2021 | }; | |
2022 | ||
85afd20e MZ |
2023 | sound { |
2024 | compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", | |
2025 | "nvidia,tegra-audio-sgtl5000"; | |
2026 | nvidia,model = "Toradex Apalis TK1"; | |
2027 | nvidia,audio-routing = | |
2028 | "Headphone Jack", "HP_OUT", | |
2029 | "LINE_IN", "Line In Jack", | |
2030 | "MIC_IN", "Mic Jack"; | |
2031 | nvidia,i2s-controller = <&tegra_i2s2>; | |
2032 | nvidia,audio-codec = <&sgtl5000>; | |
2033 | clocks = <&tegra_car TEGRA124_CLK_PLL_A>, | |
2034 | <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, | |
2035 | <&tegra_car TEGRA124_CLK_EXTERN1>; | |
2036 | clock-names = "pll_a", "pll_a_out0", "mclk"; | |
2037 | }; | |
2038 | ||
2039 | thermal-zones { | |
2040 | cpu { | |
2041 | trips { | |
d174e946 | 2042 | cpu-shutdown-trip { |
85afd20e MZ |
2043 | temperature = <101000>; |
2044 | hysteresis = <0>; | |
2045 | type = "critical"; | |
2046 | }; | |
2047 | }; | |
85afd20e MZ |
2048 | }; |
2049 | ||
2050 | mem { | |
2051 | trips { | |
d174e946 | 2052 | mem-shutdown-trip { |
85afd20e MZ |
2053 | temperature = <101000>; |
2054 | hysteresis = <0>; | |
2055 | type = "critical"; | |
2056 | }; | |
2057 | }; | |
85afd20e MZ |
2058 | }; |
2059 | ||
2060 | gpu { | |
2061 | trips { | |
d174e946 | 2062 | gpu-shutdown-trip { |
85afd20e MZ |
2063 | temperature = <101000>; |
2064 | hysteresis = <0>; | |
2065 | type = "critical"; | |
2066 | }; | |
2067 | }; | |
85afd20e MZ |
2068 | }; |
2069 | }; | |
2070 | }; | |
818e8729 MZ |
2071 | |
2072 | &gpio { | |
2073 | /* I210 Gigabit Ethernet Controller Reset */ | |
26e19cdf | 2074 | lan-reset-n { |
818e8729 MZ |
2075 | gpio-hog; |
2076 | gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>; | |
2077 | output-high; | |
2078 | line-name = "LAN_RESET_N"; | |
2079 | }; | |
2080 | ||
2081 | /* Control MXM3 pin 26 Reset Module Output Carrier Input */ | |
26e19cdf | 2082 | reset-moci-ctrl { |
818e8729 MZ |
2083 | gpio-hog; |
2084 | gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; | |
2085 | output-high; | |
2086 | line-name = "RESET_MOCI_CTRL"; | |
2087 | }; | |
2088 | }; |