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Merge tag 'powerpc-5.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / tegra124-apalis.dtsi
CommitLineData
8cb35d34 1// SPDX-License-Identifier: GPL-2.0 OR X11
85afd20e 2/*
8cb35d34 3 * Copyright 2016-2019 Toradex AG
85afd20e
MZ		 4 */
5
6#include "tegra124.dtsi"
7#include "tegra124-apalis-emc.dtsi"
8
9/*
10 * Toradex Apalis TK1 Module Device Tree
6270bd3d 11 * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A
85afd20e
MZ		 12 */
13/ {
48299769 14 memory@80000000 {
85afd20e
MZ		 15 reg = <0x0 0x80000000 0x0 0x80000000>;
16 };
17
508d690e 18 pcie@1003000 {
85afd20e 19 status = "okay";
1bef3a57
MZ		 20 avddio-pex-supply = <&reg_1v05_vdd>;
21 avdd-pex-pll-supply = <&reg_1v05_vdd>;
22 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
23 dvddio-pex-supply = <&reg_1v05_vdd>;
24 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
25 hvdd-pex-supply = <&reg_module_3v3>;
26 vddio-pex-ctl-supply = <&reg_module_3v3>;
85afd20e
MZ		 27
28 /* Apalis PCIe (additional lane Apalis type specific) */
29 pci@1,0 {
30 /* PCIE1_RX/TX and TS_DIFF1/2 */
31 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
32 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
33 phy-names = "pcie-0", "pcie-1";
34 };
35
36 /* I210 Gigabit Ethernet Controller (On-module) */
37 pci@2,0 {
38 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
39 phy-names = "pcie-0";
40 status = "okay";
864495be
MZ		 41
42 pcie@0 {
43 reg = <0 0 0 0 0>;
44 local-mac-address = [00 00 00 00 00 00];
45 };
85afd20e
MZ		 46 };
47 };
48
49 host1x@50000000 {
50 hdmi@54280000 {
85afd20e
MZ		 51 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
52 nvidia,hpd-gpio =
53 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
f2f7bf06
MZ		 54 pll-supply = <&reg_1v05_avdd_hdmi_pll>;
55 vdd-supply = <&reg_3v3_avdd_hdmi>;
85afd20e
MZ		 56 };
57 };
58
59 gpu@0,57000000 {
60 /*
61 * Node left disabled on purpose - the bootloader will enable
62 * it after having set the VPR up
63 */
1bef3a57 64 vdd-supply = <&reg_vdd_gpu>;
85afd20e
MZ		 65 };
66
35a2473f 67 pinmux@70000868 {
85afd20e
MZ		 68 pinctrl-names = "default";
69 pinctrl-0 = <&state_default>;
70
71 state_default: pinmux {
72 /* Analogue Audio (On-module) */
26e19cdf 73 dap3-fs-pp0 {
85afd20e
MZ		 74 nvidia,pins = "dap3_fs_pp0";
75 nvidia,function = "i2s2";
76 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
77 nvidia,tristate = <TEGRA_PIN_DISABLE>;
78 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
79 };
26e19cdf 80 dap3-din-pp1 {
85afd20e
MZ		 81 nvidia,pins = "dap3_din_pp1";
82 nvidia,function = "i2s2";
83 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
84 nvidia,tristate = <TEGRA_PIN_ENABLE>;
85 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
86 };
26e19cdf 87 dap3-dout-pp2 {
85afd20e
MZ		 88 nvidia,pins = "dap3_dout_pp2";
89 nvidia,function = "i2s2";
90 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
91 nvidia,tristate = <TEGRA_PIN_DISABLE>;
92 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
93 };
26e19cdf 94 dap3-sclk-pp3 {
85afd20e
MZ		 95 nvidia,pins = "dap3_sclk_pp3";
96 nvidia,function = "i2s2";
97 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
98 nvidia,tristate = <TEGRA_PIN_DISABLE>;
99 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
100 };
26e19cdf 101 dap-mclk1-pw4 {
85afd20e
MZ		 102 nvidia,pins = "dap_mclk1_pw4";
103 nvidia,function = "extperiph1";
104 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
105 nvidia,tristate = <TEGRA_PIN_DISABLE>;
106 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
107 };
108
109 /* Apalis BKL1_ON */
110 pbb5 {
111 nvidia,pins = "pbb5";
112 nvidia,function = "vgp5";
113 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
114 nvidia,tristate = <TEGRA_PIN_DISABLE>;
115 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
116 };
117
118 /* Apalis BKL1_PWM */
119 pu6 {
120 nvidia,pins = "pu6";
121 nvidia,function = "pwm3";
122 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
123 nvidia,tristate = <TEGRA_PIN_DISABLE>;
124 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
125 };
126
127 /* Apalis CAM1_MCLK */
26e19cdf 128 cam-mclk-pcc0 {
85afd20e
MZ		 129 nvidia,pins = "cam_mclk_pcc0";
130 nvidia,function = "vi_alt3";
131 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
132 nvidia,tristate = <TEGRA_PIN_DISABLE>;
133 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
134 };
135
136 /* Apalis Digital Audio */
26e19cdf 137 dap2-fs-pa2 {
85afd20e
MZ		 138 nvidia,pins = "dap2_fs_pa2";
139 nvidia,function = "hda";
140 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141 nvidia,tristate = <TEGRA_PIN_DISABLE>;
142 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
143 };
26e19cdf 144 dap2-sclk-pa3 {
85afd20e
MZ		 145 nvidia,pins = "dap2_sclk_pa3";
146 nvidia,function = "hda";
147 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
148 nvidia,tristate = <TEGRA_PIN_DISABLE>;
149 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
150 };
26e19cdf 151 dap2-din-pa4 {
85afd20e
MZ		 152 nvidia,pins = "dap2_din_pa4";
153 nvidia,function = "hda";
154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155 nvidia,tristate = <TEGRA_PIN_ENABLE>;
156 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
157 };
26e19cdf 158 dap2-dout-pa5 {
85afd20e
MZ		 159 nvidia,pins = "dap2_dout_pa5";
160 nvidia,function = "hda";
161 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
162 nvidia,tristate = <TEGRA_PIN_DISABLE>;
163 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
164 };
165 pbb3 { /* DAP1_RESET */
166 nvidia,pins = "pbb3";
167 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
168 nvidia,tristate = <TEGRA_PIN_DISABLE>;
169 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
170 };
26e19cdf 171 clk3-out-pee0 {
85afd20e
MZ		 172 nvidia,pins = "clk3_out_pee0";
173 nvidia,function = "extperiph3";
174 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
175 nvidia,tristate = <TEGRA_PIN_DISABLE>;
176 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
177 };
178
179 /* Apalis GPIO */
26e19cdf 180 ddc-scl-pv4 {
85afd20e
MZ		 181 nvidia,pins = "ddc_scl_pv4";
182 nvidia,function = "rsvd2";
183 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
184 nvidia,tristate = <TEGRA_PIN_DISABLE>;
185 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
186 };
26e19cdf 187 ddc-sda-pv5 {
85afd20e
MZ		 188 nvidia,pins = "ddc_sda_pv5";
189 nvidia,function = "rsvd2";
190 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
191 nvidia,tristate = <TEGRA_PIN_DISABLE>;
192 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
193 };
26e19cdf 194 pex-l0-rst-n-pdd1 {
85afd20e
MZ		 195 nvidia,pins = "pex_l0_rst_n_pdd1";
196 nvidia,function = "rsvd2";
197 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
198 nvidia,tristate = <TEGRA_PIN_DISABLE>;
199 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
200 };
26e19cdf 201 pex-l0-clkreq-n-pdd2 {
85afd20e
MZ		 202 nvidia,pins = "pex_l0_clkreq_n_pdd2";
203 nvidia,function = "rsvd2";
204 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
205 nvidia,tristate = <TEGRA_PIN_DISABLE>;
206 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
207 };
26e19cdf 208 pex-l1-rst-n-pdd5 {
85afd20e
MZ		 209 nvidia,pins = "pex_l1_rst_n_pdd5";
210 nvidia,function = "rsvd2";
211 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
212 nvidia,tristate = <TEGRA_PIN_DISABLE>;
213 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
214 };
26e19cdf 215 pex-l1-clkreq-n-pdd6 {
85afd20e
MZ		 216 nvidia,pins = "pex_l1_clkreq_n_pdd6";
217 nvidia,function = "rsvd2";
218 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
219 nvidia,tristate = <TEGRA_PIN_DISABLE>;
220 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
221 };
26e19cdf 222 dp-hpd-pff0 {
85afd20e 223 nvidia,pins = "dp_hpd_pff0";
a7f9d4fe 224 nvidia,function = "dp";
85afd20e
MZ		 225 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
226 nvidia,tristate = <TEGRA_PIN_DISABLE>;
227 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
228 };
229 pff2 {
230 nvidia,pins = "pff2";
231 nvidia,function = "rsvd2";
232 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
233 nvidia,tristate = <TEGRA_PIN_DISABLE>;
234 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
235 };
236 owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
237 nvidia,pins = "owr";
238 nvidia,function = "rsvd2";
239 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
240 nvidia,tristate = <TEGRA_PIN_ENABLE>;
241 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
242 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
243 };
244
245 /* Apalis HDMI1_CEC */
26e19cdf 246 hdmi-cec-pee3 {
85afd20e
MZ		 247 nvidia,pins = "hdmi_cec_pee3";
248 nvidia,function = "cec";
249 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
250 nvidia,tristate = <TEGRA_PIN_DISABLE>;
251 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
252 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
253 };
254
255 /* Apalis HDMI1_HPD */
26e19cdf 256 hdmi-int-pn7 {
85afd20e
MZ		 257 nvidia,pins = "hdmi_int_pn7";
258 nvidia,function = "rsvd1";
259 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
260 nvidia,tristate = <TEGRA_PIN_ENABLE>;
261 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
262 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
263 };
264
265 /* Apalis I2C1 */
26e19cdf 266 gen1-i2c-scl-pc4 {
85afd20e
MZ		 267 nvidia,pins = "gen1_i2c_scl_pc4";
268 nvidia,function = "i2c1";
269 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
270 nvidia,tristate = <TEGRA_PIN_DISABLE>;
271 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
272 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
273 };
26e19cdf 274 gen1-i2c-sda-pc5 {
85afd20e
MZ		 275 nvidia,pins = "gen1_i2c_sda_pc5";
276 nvidia,function = "i2c1";
277 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
278 nvidia,tristate = <TEGRA_PIN_DISABLE>;
279 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
280 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
281 };
282
283 /* Apalis I2C2 (DDC) */
26e19cdf 284 gen2-i2c-scl-pt5 {
85afd20e
MZ		 285 nvidia,pins = "gen2_i2c_scl_pt5";
286 nvidia,function = "i2c2";
287 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
288 nvidia,tristate = <TEGRA_PIN_DISABLE>;
289 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
290 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
291 };
26e19cdf 292 gen2-i2c-sda-pt6 {
85afd20e
MZ		 293 nvidia,pins = "gen2_i2c_sda_pt6";
294 nvidia,function = "i2c2";
295 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
296 nvidia,tristate = <TEGRA_PIN_DISABLE>;
297 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
298 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
299 };
300
301 /* Apalis I2C3 (CAM) */
26e19cdf 302 cam-i2c-scl-pbb1 {
85afd20e
MZ		 303 nvidia,pins = "cam_i2c_scl_pbb1";
304 nvidia,function = "i2c3";
305 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
306 nvidia,tristate = <TEGRA_PIN_DISABLE>;
307 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
308 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
309 };
26e19cdf 310 cam-i2c-sda-pbb2 {
85afd20e
MZ		 311 nvidia,pins = "cam_i2c_sda_pbb2";
312 nvidia,function = "i2c3";
313 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
314 nvidia,tristate = <TEGRA_PIN_DISABLE>;
315 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
316 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
317 };
318
319 /* Apalis MMC1 */
26e19cdf 320 sdmmc1-cd-n-pv3 { /* CD# GPIO */
85afd20e
MZ		 321 nvidia,pins = "sdmmc1_wp_n_pv3";
322 nvidia,function = "sdmmc1";
323 nvidia,pull = <TEGRA_PIN_PULL_UP>;
324 nvidia,tristate = <TEGRA_PIN_ENABLE>;
325 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
326 };
26e19cdf 327 clk2-out-pw5 { /* D5 GPIO */
85afd20e
MZ		 328 nvidia,pins = "clk2_out_pw5";
329 nvidia,function = "rsvd2";
330 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
331 nvidia,tristate = <TEGRA_PIN_DISABLE>;
332 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
333 };
26e19cdf 334 sdmmc1-dat3-py4 {
85afd20e
MZ		 335 nvidia,pins = "sdmmc1_dat3_py4";
336 nvidia,function = "sdmmc1";
337 nvidia,pull = <TEGRA_PIN_PULL_UP>;
338 nvidia,tristate = <TEGRA_PIN_DISABLE>;
339 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
340 };
26e19cdf 341 sdmmc1-dat2-py5 {
85afd20e
MZ		 342 nvidia,pins = "sdmmc1_dat2_py5";
343 nvidia,function = "sdmmc1";
344 nvidia,pull = <TEGRA_PIN_PULL_UP>;
345 nvidia,tristate = <TEGRA_PIN_DISABLE>;
346 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
347 };
26e19cdf 348 sdmmc1-dat1-py6 {
85afd20e
MZ		 349 nvidia,pins = "sdmmc1_dat1_py6";
350 nvidia,function = "sdmmc1";
351 nvidia,pull = <TEGRA_PIN_PULL_UP>;
352 nvidia,tristate = <TEGRA_PIN_DISABLE>;
353 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
354 };
26e19cdf 355 sdmmc1-dat0-py7 {
85afd20e
MZ		 356 nvidia,pins = "sdmmc1_dat0_py7";
357 nvidia,function = "sdmmc1";
358 nvidia,pull = <TEGRA_PIN_PULL_UP>;
359 nvidia,tristate = <TEGRA_PIN_DISABLE>;
360 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
361 };
26e19cdf 362 sdmmc1-clk-pz0 {
85afd20e
MZ		 363 nvidia,pins = "sdmmc1_clk_pz0";
364 nvidia,function = "sdmmc1";
365 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
366 nvidia,tristate = <TEGRA_PIN_DISABLE>;
367 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
368 };
26e19cdf 369 sdmmc1-cmd-pz1 {
85afd20e
MZ		 370 nvidia,pins = "sdmmc1_cmd_pz1";
371 nvidia,function = "sdmmc1";
372 nvidia,pull = <TEGRA_PIN_PULL_UP>;
373 nvidia,tristate = <TEGRA_PIN_DISABLE>;
374 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
375 };
26e19cdf 376 clk2-req-pcc5 { /* D4 GPIO */
85afd20e
MZ		 377 nvidia,pins = "clk2_req_pcc5";
378 nvidia,function = "rsvd2";
379 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
380 nvidia,tristate = <TEGRA_PIN_DISABLE>;
381 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
382 };
26e19cdf 383 sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */
85afd20e 384 nvidia,pins = "sdmmc3_clk_lb_in_pee5";
5142bd65
MZ		 385 nvidia,function = "rsvd2";
386 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
85afd20e
MZ		 387 nvidia,tristate = <TEGRA_PIN_DISABLE>;
388 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
389 };
26e19cdf 390 usb-vbus-en2-pff1 { /* D7 GPIO */
85afd20e
MZ		 391 nvidia,pins = "usb_vbus_en2_pff1";
392 nvidia,function = "rsvd2";
393 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
394 nvidia,tristate = <TEGRA_PIN_DISABLE>;
395 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
396 };
397
398 /* Apalis PWM */
399 ph0 {
400 nvidia,pins = "ph0";
401 nvidia,function = "pwm0";
402 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
403 nvidia,tristate = <TEGRA_PIN_DISABLE>;
404 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
405 };
406 ph1 {
407 nvidia,pins = "ph1";
408 nvidia,function = "pwm1";
409 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
410 nvidia,tristate = <TEGRA_PIN_DISABLE>;
411 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
412 };
413 ph2 {
414 nvidia,pins = "ph2";
415 nvidia,function = "pwm2";
416 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
417 nvidia,tristate = <TEGRA_PIN_DISABLE>;
418 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
419 };
e18dc296 420 /* PWM3 active on pu6 being Apalis BKL1_PWM as well */
85afd20e
MZ		 421 ph3 {
422 nvidia,pins = "ph3";
e18dc296
MZ		 423 nvidia,function = "pwm3";
424 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
425 nvidia,tristate = <TEGRA_PIN_DISABLE>;
85afd20e
MZ		 426 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
427 };
428
429 /* Apalis SATA1_ACT# */
26e19cdf 430 dap1-dout-pn2 {
85afd20e
MZ		 431 nvidia,pins = "dap1_dout_pn2";
432 nvidia,function = "gmi";
433 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
434 nvidia,tristate = <TEGRA_PIN_DISABLE>;
435 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
436 };
437
438 /* Apalis SD1 */
26e19cdf 439 sdmmc3-clk-pa6 {
85afd20e
MZ		 440 nvidia,pins = "sdmmc3_clk_pa6";
441 nvidia,function = "sdmmc3";
442 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
443 nvidia,tristate = <TEGRA_PIN_DISABLE>;
444 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
445 };
26e19cdf 446 sdmmc3-cmd-pa7 {
85afd20e
MZ		 447 nvidia,pins = "sdmmc3_cmd_pa7";
448 nvidia,function = "sdmmc3";
449 nvidia,pull = <TEGRA_PIN_PULL_UP>;
450 nvidia,tristate = <TEGRA_PIN_DISABLE>;
451 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
452 };
26e19cdf 453 sdmmc3-dat3-pb4 {
85afd20e
MZ		 454 nvidia,pins = "sdmmc3_dat3_pb4";
455 nvidia,function = "sdmmc3";
456 nvidia,pull = <TEGRA_PIN_PULL_UP>;
457 nvidia,tristate = <TEGRA_PIN_DISABLE>;
458 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
459 };
26e19cdf 460 sdmmc3-dat2-pb5 {
85afd20e
MZ		 461 nvidia,pins = "sdmmc3_dat2_pb5";
462 nvidia,function = "sdmmc3";
463 nvidia,pull = <TEGRA_PIN_PULL_UP>;
464 nvidia,tristate = <TEGRA_PIN_DISABLE>;
465 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
466 };
26e19cdf 467 sdmmc3-dat1-pb6 {
85afd20e
MZ		 468 nvidia,pins = "sdmmc3_dat1_pb6";
469 nvidia,function = "sdmmc3";
470 nvidia,pull = <TEGRA_PIN_PULL_UP>;
471 nvidia,tristate = <TEGRA_PIN_DISABLE>;
472 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
473 };
26e19cdf 474 sdmmc3-dat0-pb7 {
85afd20e
MZ		 475 nvidia,pins = "sdmmc3_dat0_pb7";
476 nvidia,function = "sdmmc3";
477 nvidia,pull = <TEGRA_PIN_PULL_UP>;
478 nvidia,tristate = <TEGRA_PIN_DISABLE>;
479 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
480 };
26e19cdf 481 sdmmc3-cd-n-pv2 { /* CD# GPIO */
5142bd65
MZ		 482 nvidia,pins = "sdmmc3_cd_n_pv2";
483 nvidia,function = "rsvd3";
484 nvidia,pull = <TEGRA_PIN_PULL_UP>;
85afd20e 485 nvidia,tristate = <TEGRA_PIN_ENABLE>;
5142bd65 486 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
85afd20e
MZ		 487 };
488
489 /* Apalis SPDIF */
26e19cdf 490 spdif-out-pk5 {
85afd20e
MZ		 491 nvidia,pins = "spdif_out_pk5";
492 nvidia,function = "spdif";
493 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
494 nvidia,tristate = <TEGRA_PIN_DISABLE>;
495 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
496 };
26e19cdf 497 spdif-in-pk6 {
85afd20e
MZ		 498 nvidia,pins = "spdif_in_pk6";
499 nvidia,function = "spdif";
500 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
501 nvidia,tristate = <TEGRA_PIN_ENABLE>;
502 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
503 };
504
505 /* Apalis SPI1 */
26e19cdf 506 ulpi-clk-py0 {
85afd20e
MZ		 507 nvidia,pins = "ulpi_clk_py0";
508 nvidia,function = "spi1";
509 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
510 nvidia,tristate = <TEGRA_PIN_DISABLE>;
511 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
512 };
26e19cdf 513 ulpi-dir-py1 {
85afd20e
MZ		 514 nvidia,pins = "ulpi_dir_py1";
515 nvidia,function = "spi1";
516 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
517 nvidia,tristate = <TEGRA_PIN_ENABLE>;
518 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
519 };
26e19cdf 520 ulpi-nxt-py2 {
85afd20e
MZ		 521 nvidia,pins = "ulpi_nxt_py2";
522 nvidia,function = "spi1";
523 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
524 nvidia,tristate = <TEGRA_PIN_DISABLE>;
525 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
526 };
26e19cdf 527 ulpi-stp-py3 {
85afd20e
MZ		 528 nvidia,pins = "ulpi_stp_py3";
529 nvidia,function = "spi1";
530 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
531 nvidia,tristate = <TEGRA_PIN_DISABLE>;
532 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
533 };
534
535 /* Apalis SPI2 */
536 pg5 {
537 nvidia,pins = "pg5";
538 nvidia,function = "spi4";
539 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
540 nvidia,tristate = <TEGRA_PIN_DISABLE>;
541 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
542 };
543 pg6 {
544 nvidia,pins = "pg6";
545 nvidia,function = "spi4";
546 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
547 nvidia,tristate = <TEGRA_PIN_DISABLE>;
548 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
549 };
550 pg7 {
551 nvidia,pins = "pg7";
552 nvidia,function = "spi4";
553 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
554 nvidia,tristate = <TEGRA_PIN_ENABLE>;
555 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
556 };
557 pi3 {
558 nvidia,pins = "pi3";
559 nvidia,function = "spi4";
560 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
561 nvidia,tristate = <TEGRA_PIN_DISABLE>;
562 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
563 };
564
565 /* Apalis UART1 */
566 pb1 { /* DCD GPIO */
567 nvidia,pins = "pb1";
568 nvidia,function = "rsvd2";
569 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
570 nvidia,tristate = <TEGRA_PIN_ENABLE>;
571 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
572 };
573 pk7 { /* RI GPIO */
574 nvidia,pins = "pk7";
575 nvidia,function = "rsvd2";
576 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
577 nvidia,tristate = <TEGRA_PIN_ENABLE>;
578 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
579 };
26e19cdf 580 uart1-txd-pu0 {
85afd20e
MZ		 581 nvidia,pins = "pu0";
582 nvidia,function = "uarta";
583 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
584 nvidia,tristate = <TEGRA_PIN_DISABLE>;
585 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
586 };
26e19cdf 587 uart1-rxd-pu1 {
85afd20e
MZ		 588 nvidia,pins = "pu1";
589 nvidia,function = "uarta";
590 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
591 nvidia,tristate = <TEGRA_PIN_ENABLE>;
592 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
593 };
26e19cdf 594 uart1-cts-n-pu2 {
85afd20e
MZ		 595 nvidia,pins = "pu2";
596 nvidia,function = "uarta";
597 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
598 nvidia,tristate = <TEGRA_PIN_ENABLE>;
599 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
600 };
26e19cdf 601 uart1-rts-n-pu3 {
85afd20e
MZ		 602 nvidia,pins = "pu3";
603 nvidia,function = "uarta";
604 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
605 nvidia,tristate = <TEGRA_PIN_DISABLE>;
606 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
607 };
26e19cdf 608 uart3-cts-n-pa1 { /* DSR GPIO */
85afd20e
MZ		 609 nvidia,pins = "uart3_cts_n_pa1";
610 nvidia,function = "gmi";
611 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
612 nvidia,tristate = <TEGRA_PIN_ENABLE>;
613 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
614 };
26e19cdf 615 uart3-rts-n-pc0 { /* DTR GPIO */
85afd20e
MZ		 616 nvidia,pins = "uart3_rts_n_pc0";
617 nvidia,function = "gmi";
618 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
619 nvidia,tristate = <TEGRA_PIN_DISABLE>;
620 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
621 };
622
623 /* Apalis UART2 */
26e19cdf 624 uart2-txd-pc2 {
85afd20e
MZ		 625 nvidia,pins = "uart2_txd_pc2";
626 nvidia,function = "irda";
627 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
628 nvidia,tristate = <TEGRA_PIN_DISABLE>;
629 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
630 };
26e19cdf 631 uart2-rxd-pc3 {
85afd20e
MZ		 632 nvidia,pins = "uart2_rxd_pc3";
633 nvidia,function = "irda";
634 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
635 nvidia,tristate = <TEGRA_PIN_ENABLE>;
636 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
637 };
26e19cdf 638 uart2-cts-n-pj5 {
85afd20e
MZ		 639 nvidia,pins = "uart2_cts_n_pj5";
640 nvidia,function = "uartb";
641 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
642 nvidia,tristate = <TEGRA_PIN_ENABLE>;
643 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
644 };
26e19cdf 645 uart2-rts-n-pj6 {
85afd20e
MZ		 646 nvidia,pins = "uart2_rts_n_pj6";
647 nvidia,function = "uartb";
648 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
649 nvidia,tristate = <TEGRA_PIN_DISABLE>;
650 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
651 };
652
653 /* Apalis UART3 */
26e19cdf 654 uart3-txd-pw6 {
85afd20e
MZ		 655 nvidia,pins = "uart3_txd_pw6";
656 nvidia,function = "uartc";
657 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
658 nvidia,tristate = <TEGRA_PIN_DISABLE>;
659 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
660 };
26e19cdf 661 uart3-rxd-pw7 {
85afd20e
MZ		 662 nvidia,pins = "uart3_rxd_pw7";
663 nvidia,function = "uartc";
664 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
665 nvidia,tristate = <TEGRA_PIN_ENABLE>;
666 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
667 };
668
669 /* Apalis UART4 */
26e19cdf 670 uart4-rxd-pb0 {
85afd20e
MZ		 671 nvidia,pins = "pb0";
672 nvidia,function = "uartd";
673 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
674 nvidia,tristate = <TEGRA_PIN_ENABLE>;
675 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
676 };
26e19cdf 677 uart4-txd-pj7 {
85afd20e
MZ		 678 nvidia,pins = "pj7";
679 nvidia,function = "uartd";
680 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
681 nvidia,tristate = <TEGRA_PIN_DISABLE>;
682 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
683 };
684
685 /* Apalis USBH_EN */
26e19cdf 686 usb-vbus-en1-pn5 {
85afd20e
MZ		 687 nvidia,pins = "usb_vbus_en1_pn5";
688 nvidia,function = "rsvd2";
689 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
690 nvidia,tristate = <TEGRA_PIN_DISABLE>;
691 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
692 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
693 };
694
695 /* Apalis USBH_OC# */
696 pbb0 {
697 nvidia,pins = "pbb0";
698 nvidia,function = "vgp6";
699 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
700 nvidia,tristate = <TEGRA_PIN_ENABLE>;
701 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
702 };
703
704 /* Apalis USBO1_EN */
26e19cdf 705 usb-vbus-en0-pn4 {
85afd20e
MZ		 706 nvidia,pins = "usb_vbus_en0_pn4";
707 nvidia,function = "rsvd2";
708 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
709 nvidia,tristate = <TEGRA_PIN_DISABLE>;
710 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
711 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
712 };
713
714 /* Apalis USBO1_OC# */
715 pbb4 {
716 nvidia,pins = "pbb4";
717 nvidia,function = "vgp4";
718 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
719 nvidia,tristate = <TEGRA_PIN_ENABLE>;
720 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
721 };
722
723 /* Apalis WAKE1_MICO */
26e19cdf 724 pex-wake-n-pdd3 {
85afd20e
MZ		 725 nvidia,pins = "pex_wake_n_pdd3";
726 nvidia,function = "rsvd2";
727 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
728 nvidia,tristate = <TEGRA_PIN_ENABLE>;
729 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
730 };
731
732 /* CORE_PWR_REQ */
26e19cdf 733 core-pwr-req {
85afd20e
MZ		 734 nvidia,pins = "core_pwr_req";
735 nvidia,function = "pwron";
736 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
737 nvidia,tristate = <TEGRA_PIN_DISABLE>;
738 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
739 };
740
741 /* CPU_PWR_REQ */
26e19cdf 742 cpu-pwr-req {
85afd20e
MZ		 743 nvidia,pins = "cpu_pwr_req";
744 nvidia,function = "cpu";
745 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
746 nvidia,tristate = <TEGRA_PIN_DISABLE>;
747 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
748 };
749
750 /* DVFS */
26e19cdf 751 dvfs-pwm-px0 {
85afd20e
MZ		 752 nvidia,pins = "dvfs_pwm_px0";
753 nvidia,function = "cldvfs";
754 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
755 nvidia,tristate = <TEGRA_PIN_DISABLE>;
756 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
757 };
26e19cdf 758 dvfs-clk-px2 {
85afd20e
MZ		 759 nvidia,pins = "dvfs_clk_px2";
760 nvidia,function = "cldvfs";
761 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
762 nvidia,tristate = <TEGRA_PIN_DISABLE>;
763 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
764 };
765
766 /* eMMC */
26e19cdf 767 sdmmc4-dat0-paa0 {
85afd20e
MZ		 768 nvidia,pins = "sdmmc4_dat0_paa0";
769 nvidia,function = "sdmmc4";
770 nvidia,pull = <TEGRA_PIN_PULL_UP>;
771 nvidia,tristate = <TEGRA_PIN_DISABLE>;
772 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
773 };
26e19cdf 774 sdmmc4-dat1-paa1 {
85afd20e
MZ		 775 nvidia,pins = "sdmmc4_dat1_paa1";
776 nvidia,function = "sdmmc4";
777 nvidia,pull = <TEGRA_PIN_PULL_UP>;
778 nvidia,tristate = <TEGRA_PIN_DISABLE>;
779 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
780 };
26e19cdf 781 sdmmc4-dat2-paa2 {
85afd20e
MZ		 782 nvidia,pins = "sdmmc4_dat2_paa2";
783 nvidia,function = "sdmmc4";
784 nvidia,pull = <TEGRA_PIN_PULL_UP>;
785 nvidia,tristate = <TEGRA_PIN_DISABLE>;
786 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
787 };
26e19cdf 788 sdmmc4-dat3-paa3 {
85afd20e
MZ		 789 nvidia,pins = "sdmmc4_dat3_paa3";
790 nvidia,function = "sdmmc4";
791 nvidia,pull = <TEGRA_PIN_PULL_UP>;
792 nvidia,tristate = <TEGRA_PIN_DISABLE>;
793 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
794 };
26e19cdf 795 sdmmc4-dat4-paa4 {
85afd20e
MZ		 796 nvidia,pins = "sdmmc4_dat4_paa4";
797 nvidia,function = "sdmmc4";
798 nvidia,pull = <TEGRA_PIN_PULL_UP>;
799 nvidia,tristate = <TEGRA_PIN_DISABLE>;
800 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
801 };
26e19cdf 802 sdmmc4-dat5-paa5 {
85afd20e
MZ		 803 nvidia,pins = "sdmmc4_dat5_paa5";
804 nvidia,function = "sdmmc4";
805 nvidia,pull = <TEGRA_PIN_PULL_UP>;
806 nvidia,tristate = <TEGRA_PIN_DISABLE>;
807 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
808 };
26e19cdf 809 sdmmc4-dat6-paa6 {
85afd20e
MZ		 810 nvidia,pins = "sdmmc4_dat6_paa6";
811 nvidia,function = "sdmmc4";
812 nvidia,pull = <TEGRA_PIN_PULL_UP>;
813 nvidia,tristate = <TEGRA_PIN_DISABLE>;
814 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
815 };
26e19cdf 816 sdmmc4-dat7-paa7 {
85afd20e
MZ		 817 nvidia,pins = "sdmmc4_dat7_paa7";
818 nvidia,function = "sdmmc4";
819 nvidia,pull = <TEGRA_PIN_PULL_UP>;
820 nvidia,tristate = <TEGRA_PIN_DISABLE>;
821 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
822 };
26e19cdf 823 sdmmc4-clk-pcc4 {
85afd20e
MZ		 824 nvidia,pins = "sdmmc4_clk_pcc4";
825 nvidia,function = "sdmmc4";
826 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
827 nvidia,tristate = <TEGRA_PIN_DISABLE>;
828 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
829 };
26e19cdf 830 sdmmc4-cmd-pt7 {
85afd20e
MZ		 831 nvidia,pins = "sdmmc4_cmd_pt7";
832 nvidia,function = "sdmmc4";
833 nvidia,pull = <TEGRA_PIN_PULL_UP>;
834 nvidia,tristate = <TEGRA_PIN_DISABLE>;
835 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
836 };
837
838 /* JTAG_RTCK */
26e19cdf 839 jtag-rtck {
85afd20e
MZ		 840 nvidia,pins = "jtag_rtck";
841 nvidia,function = "rtck";
842 nvidia,pull = <TEGRA_PIN_PULL_UP>;
843 nvidia,tristate = <TEGRA_PIN_DISABLE>;
844 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
845 };
846
847 /* LAN_DEV_OFF# */
26e19cdf 848 ulpi-data5-po6 {
85afd20e
MZ		 849 nvidia,pins = "ulpi_data5_po6";
850 nvidia,function = "ulpi";
851 nvidia,pull = <TEGRA_PIN_PULL_UP>;
852 nvidia,tristate = <TEGRA_PIN_DISABLE>;
853 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
854 };
855
856 /* LAN_RESET# */
26e19cdf 857 kb-row10-ps2 {
85afd20e
MZ		 858 nvidia,pins = "kb_row10_ps2";
859 nvidia,function = "rsvd2";
860 nvidia,pull = <TEGRA_PIN_PULL_UP>;
861 nvidia,tristate = <TEGRA_PIN_DISABLE>;
862 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
863 };
864
865 /* LAN_WAKE# */
26e19cdf 866 ulpi-data4-po5 {
85afd20e
MZ		 867 nvidia,pins = "ulpi_data4_po5";
868 nvidia,function = "ulpi";
869 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
870 nvidia,tristate = <TEGRA_PIN_ENABLE>;
871 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
872 };
873
874 /* MCU_INT1# */
875 pk2 {
876 nvidia,pins = "pk2";
877 nvidia,function = "rsvd1";
878 nvidia,pull = <TEGRA_PIN_PULL_UP>;
879 nvidia,tristate = <TEGRA_PIN_ENABLE>;
880 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
881 };
882
883 /* MCU_INT2# */
884 pj2 {
885 nvidia,pins = "pj2";
886 nvidia,function = "rsvd1";
887 nvidia,pull = <TEGRA_PIN_PULL_UP>;
888 nvidia,tristate = <TEGRA_PIN_ENABLE>;
889 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
890 };
891
892 /* MCU_INT3# */
893 pi5 {
894 nvidia,pins = "pi5";
895 nvidia,function = "rsvd2";
896 nvidia,pull = <TEGRA_PIN_PULL_UP>;
897 nvidia,tristate = <TEGRA_PIN_ENABLE>;
898 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
899 };
900
901 /* MCU_INT4# */
902 pj0 {
903 nvidia,pins = "pj0";
904 nvidia,function = "rsvd1";
905 nvidia,pull = <TEGRA_PIN_PULL_UP>;
906 nvidia,tristate = <TEGRA_PIN_ENABLE>;
907 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
908 };
909
910 /* MCU_RESET */
911 pbb6 {
912 nvidia,pins = "pbb6";
913 nvidia,function = "rsvd2";
914 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
915 nvidia,tristate = <TEGRA_PIN_DISABLE>;
916 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
917 };
918
919 /* MCU SPI */
26e19cdf 920 gpio-x4-aud-px4 {
85afd20e
MZ		 921 nvidia,pins = "gpio_x4_aud_px4";
922 nvidia,function = "spi2";
923 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
924 nvidia,tristate = <TEGRA_PIN_DISABLE>;
925 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
926 };
26e19cdf 927 gpio-x5-aud-px5 {
85afd20e
MZ		 928 nvidia,pins = "gpio_x5_aud_px5";
929 nvidia,function = "spi2";
930 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
931 nvidia,tristate = <TEGRA_PIN_DISABLE>;
932 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
933 };
26e19cdf 934 gpio-x6-aud-px6 { /* MCU_CS */
85afd20e
MZ		 935 nvidia,pins = "gpio_x6_aud_px6";
936 nvidia,function = "spi2";
937 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
938 nvidia,tristate = <TEGRA_PIN_DISABLE>;
939 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
940 };
26e19cdf 941 gpio-x7-aud-px7 {
85afd20e
MZ		 942 nvidia,pins = "gpio_x7_aud_px7";
943 nvidia,function = "spi2";
944 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
945 nvidia,tristate = <TEGRA_PIN_ENABLE>;
946 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
947 };
26e19cdf 948 gpio-w2-aud-pw2 { /* MCU_CSEZP */
85afd20e
MZ		 949 nvidia,pins = "gpio_w2_aud_pw2";
950 nvidia,function = "spi2";
951 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
952 nvidia,tristate = <TEGRA_PIN_DISABLE>;
953 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
954 };
955
956 /* PMIC_CLK_32K */
26e19cdf 957 clk-32k-in {
85afd20e
MZ		 958 nvidia,pins = "clk_32k_in";
959 nvidia,function = "clk";
960 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
961 nvidia,tristate = <TEGRA_PIN_ENABLE>;
962 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
963 };
964
965 /* PMIC_CPU_OC_INT */
26e19cdf 966 clk-32k-out-pa0 {
85afd20e
MZ		 967 nvidia,pins = "clk_32k_out_pa0";
968 nvidia,function = "soc";
969 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
970 nvidia,tristate = <TEGRA_PIN_ENABLE>;
971 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
972 };
973
974 /* PWR_I2C */
26e19cdf 975 pwr-i2c-scl-pz6 {
85afd20e
MZ		 976 nvidia,pins = "pwr_i2c_scl_pz6";
977 nvidia,function = "i2cpwr";
978 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
979 nvidia,tristate = <TEGRA_PIN_DISABLE>;
980 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
981 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
982 };
26e19cdf 983 pwr-i2c-sda-pz7 {
85afd20e
MZ		 984 nvidia,pins = "pwr_i2c_sda_pz7";
985 nvidia,function = "i2cpwr";
986 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
987 nvidia,tristate = <TEGRA_PIN_DISABLE>;
988 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
989 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
990 };
991
992 /* PWR_INT_N */
26e19cdf 993 pwr-int-n {
85afd20e
MZ		 994 nvidia,pins = "pwr_int_n";
995 nvidia,function = "pmi";
996 nvidia,pull = <TEGRA_PIN_PULL_UP>;
997 nvidia,tristate = <TEGRA_PIN_ENABLE>;
998 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
999 };
1000
1001 /* RESET_MOCI_CTRL */
1002 pu4 {
1003 nvidia,pins = "pu4";
1004 nvidia,function = "gmi";
1005 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1006 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1007 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1008 };
1009
1010 /* RESET_OUT_N */
26e19cdf 1011 reset-out-n {
85afd20e
MZ		 1012 nvidia,pins = "reset_out_n";
1013 nvidia,function = "reset_out_n";
1014 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1015 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1016 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1017 };
1018
1019 /* SHIFT_CTRL_DIR_IN */
26e19cdf 1020 kb-row0-pr0 {
85afd20e
MZ		 1021 nvidia,pins = "kb_row0_pr0";
1022 nvidia,function = "rsvd2";
1023 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1024 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1025 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1026 };
26e19cdf 1027 kb-row1-pr1 {
85afd20e
MZ		 1028 nvidia,pins = "kb_row1_pr1";
1029 nvidia,function = "rsvd2";
1030 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1031 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1032 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1033 };
1034
1035 /* Configure level-shifter as output for HDA */
26e19cdf 1036 kb-row11-ps3 {
85afd20e
MZ		 1037 nvidia,pins = "kb_row11_ps3";
1038 nvidia,function = "rsvd2";
1039 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1040 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1041 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1042 };
1043
1044 /* SHIFT_CTRL_DIR_OUT */
26e19cdf 1045 kb-col5-pq5 {
85afd20e
MZ		 1046 nvidia,pins = "kb_col5_pq5";
1047 nvidia,function = "rsvd2";
1048 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1049 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1050 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1051 };
26e19cdf 1052 kb-col6-pq6 {
85afd20e
MZ		 1053 nvidia,pins = "kb_col6_pq6";
1054 nvidia,function = "rsvd2";
1055 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1056 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1057 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1058 };
26e19cdf 1059 kb-col7-pq7 {
85afd20e
MZ		 1060 nvidia,pins = "kb_col7_pq7";
1061 nvidia,function = "rsvd2";
1062 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1063 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1064 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1065 };
1066
1067 /* SHIFT_CTRL_OE */
26e19cdf 1068 kb-col0-pq0 {
85afd20e
MZ		 1069 nvidia,pins = "kb_col0_pq0";
1070 nvidia,function = "rsvd2";
1071 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1072 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1073 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1074 };
26e19cdf 1075 kb-col1-pq1 {
85afd20e
MZ		 1076 nvidia,pins = "kb_col1_pq1";
1077 nvidia,function = "rsvd2";
1078 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1079 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1080 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1081 };
26e19cdf 1082 kb-col2-pq2 {
85afd20e
MZ		 1083 nvidia,pins = "kb_col2_pq2";
1084 nvidia,function = "rsvd2";
1085 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1086 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1087 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1088 };
26e19cdf 1089 kb-col4-pq4 {
85afd20e
MZ		 1090 nvidia,pins = "kb_col4_pq4";
1091 nvidia,function = "kbc";
1092 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1093 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1094 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1095 };
26e19cdf 1096 kb-row2-pr2 {
85afd20e
MZ		 1097 nvidia,pins = "kb_row2_pr2";
1098 nvidia,function = "rsvd2";
1099 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1100 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1101 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1102 };
1103
02888f8b 1104 /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */
85afd20e
MZ		 1105 pi6 {
1106 nvidia,pins = "pi6";
1107 nvidia,function = "rsvd1";
02888f8b 1108 nvidia,pull = <TEGRA_PIN_PULL_UP>;
85afd20e
MZ		 1109 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1110 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1111 };
1112
1113 /* TOUCH_INT */
26e19cdf 1114 gpio-w3-aud-pw3 {
85afd20e
MZ		 1115 nvidia,pins = "gpio_w3_aud_pw3";
1116 nvidia,function = "spi6";
1117 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1118 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1119 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1120 };
1121
1122 pc7 { /* NC */
1123 nvidia,pins = "pc7";
1124 nvidia,function = "rsvd1";
1125 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1126 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1127 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1128 };
1129 pg0 { /* NC */
1130 nvidia,pins = "pg0";
1131 nvidia,function = "rsvd1";
1132 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1133 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1134 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1135 };
1136 pg1 { /* NC */
1137 nvidia,pins = "pg1";
1138 nvidia,function = "rsvd1";
1139 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1140 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1141 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1142 };
1143 pg2 { /* NC */
1144 nvidia,pins = "pg2";
1145 nvidia,function = "rsvd1";
1146 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1147 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1148 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1149 };
1150 pg3 { /* NC */
1151 nvidia,pins = "pg3";
1152 nvidia,function = "rsvd1";
1153 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1154 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1155 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1156 };
1157 pg4 { /* NC */
1158 nvidia,pins = "pg4";
1159 nvidia,function = "rsvd1";
1160 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1161 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1162 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1163 };
1164 ph4 { /* NC */
1165 nvidia,pins = "ph4";
1166 nvidia,function = "rsvd2";
1167 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1168 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1169 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1170 };
1171 ph5 { /* NC */
1172 nvidia,pins = "ph5";
1173 nvidia,function = "rsvd2";
1174 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1175 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1176 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1177 };
1178 ph6 { /* NC */
1179 nvidia,pins = "ph6";
1180 nvidia,function = "gmi";
1181 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1182 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1183 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1184 };
1185 ph7 { /* NC */
1186 nvidia,pins = "ph7";
1187 nvidia,function = "gmi";
1188 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1189 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1190 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1191 };
1192 pi0 { /* NC */
1193 nvidia,pins = "pi0";
1194 nvidia,function = "rsvd1";
1195 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1196 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1197 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1198 };
1199 pi1 { /* NC */
1200 nvidia,pins = "pi1";
1201 nvidia,function = "rsvd1";
1202 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1203 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1204 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1205 };
1206 pi2 { /* NC */
1207 nvidia,pins = "pi2";
1208 nvidia,function = "rsvd4";
1209 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1210 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1211 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1212 };
1213 pi4 { /* NC */
1214 nvidia,pins = "pi4";
1215 nvidia,function = "gmi";
1216 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1217 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1218 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1219 };
1220 pi7 { /* NC */
1221 nvidia,pins = "pi7";
1222 nvidia,function = "rsvd1";
1223 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1224 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1225 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1226 };
1227 pk0 { /* NC */
1228 nvidia,pins = "pk0";
1229 nvidia,function = "rsvd1";
1230 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1231 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1232 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1233 };
1234 pk1 { /* NC */
1235 nvidia,pins = "pk1";
1236 nvidia,function = "rsvd4";
1237 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1238 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1239 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1240 };
1241 pk3 { /* NC */
1242 nvidia,pins = "pk3";
1243 nvidia,function = "gmi";
1244 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1245 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1246 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1247 };
1248 pk4 { /* NC */
1249 nvidia,pins = "pk4";
1250 nvidia,function = "rsvd2";
1251 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1252 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1253 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1254 };
26e19cdf 1255 dap1-fs-pn0 { /* NC */
85afd20e
MZ		 1256 nvidia,pins = "dap1_fs_pn0";
1257 nvidia,function = "rsvd4";
1258 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1259 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1260 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1261 };
26e19cdf 1262 dap1-din-pn1 { /* NC */
85afd20e
MZ		 1263 nvidia,pins = "dap1_din_pn1";
1264 nvidia,function = "rsvd4";
1265 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1266 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1267 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1268 };
26e19cdf 1269 dap1-sclk-pn3 { /* NC */
85afd20e
MZ		 1270 nvidia,pins = "dap1_sclk_pn3";
1271 nvidia,function = "rsvd4";
1272 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1273 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1274 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1275 };
26e19cdf 1276 ulpi-data7-po0 { /* NC */
85afd20e
MZ		 1277 nvidia,pins = "ulpi_data7_po0";
1278 nvidia,function = "ulpi";
1279 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1280 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1281 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1282 };
26e19cdf 1283 ulpi-data0-po1 { /* NC */
85afd20e
MZ		 1284 nvidia,pins = "ulpi_data0_po1";
1285 nvidia,function = "ulpi";
1286 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1287 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1288 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1289 };
26e19cdf 1290 ulpi-data1-po2 { /* NC */
85afd20e
MZ		 1291 nvidia,pins = "ulpi_data1_po2";
1292 nvidia,function = "ulpi";
1293 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1294 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1295 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1296 };
26e19cdf 1297 ulpi-data2-po3 { /* NC */
85afd20e
MZ		 1298 nvidia,pins = "ulpi_data2_po3";
1299 nvidia,function = "ulpi";
1300 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1301 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1302 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1303 };
26e19cdf 1304 ulpi-data3-po4 { /* NC */
85afd20e
MZ		 1305 nvidia,pins = "ulpi_data3_po4";
1306 nvidia,function = "ulpi";
1307 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1308 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1309 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1310 };
26e19cdf 1311 ulpi-data6-po7 { /* NC */
85afd20e
MZ		 1312 nvidia,pins = "ulpi_data6_po7";
1313 nvidia,function = "ulpi";
1314 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1315 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1316 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1317 };
26e19cdf 1318 dap4-fs-pp4 { /* NC */
85afd20e
MZ		 1319 nvidia,pins = "dap4_fs_pp4";
1320 nvidia,function = "rsvd4";
1321 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1322 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1323 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1324 };
26e19cdf 1325 dap4-din-pp5 { /* NC */
85afd20e
MZ		 1326 nvidia,pins = "dap4_din_pp5";
1327 nvidia,function = "rsvd3";
1328 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1329 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1330 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1331 };
26e19cdf 1332 dap4-dout-pp6 { /* NC */
85afd20e
MZ		 1333 nvidia,pins = "dap4_dout_pp6";
1334 nvidia,function = "rsvd4";
1335 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1336 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1337 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1338 };
26e19cdf 1339 dap4-sclk-pp7 { /* NC */
85afd20e
MZ		 1340 nvidia,pins = "dap4_sclk_pp7";
1341 nvidia,function = "rsvd3";
1342 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1343 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1344 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1345 };
26e19cdf 1346 kb-col3-pq3 { /* NC */
85afd20e
MZ		 1347 nvidia,pins = "kb_col3_pq3";
1348 nvidia,function = "kbc";
1349 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1350 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1351 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1352 };
26e19cdf 1353 kb-row3-pr3 { /* NC */
85afd20e
MZ		 1354 nvidia,pins = "kb_row3_pr3";
1355 nvidia,function = "kbc";
1356 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1357 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1358 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1359 };
26e19cdf 1360 kb-row4-pr4 { /* NC */
85afd20e
MZ		 1361 nvidia,pins = "kb_row4_pr4";
1362 nvidia,function = "rsvd3";
1363 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1364 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1365 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1366 };
26e19cdf 1367 kb-row5-pr5 { /* NC */
85afd20e
MZ		 1368 nvidia,pins = "kb_row5_pr5";
1369 nvidia,function = "rsvd3";
1370 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1371 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1372 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1373 };
26e19cdf 1374 kb-row6-pr6 { /* NC */
85afd20e
MZ		 1375 nvidia,pins = "kb_row6_pr6";
1376 nvidia,function = "kbc";
1377 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1378 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1379 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1380 };
26e19cdf 1381 kb-row7-pr7 { /* NC */
85afd20e
MZ		 1382 nvidia,pins = "kb_row7_pr7";
1383 nvidia,function = "rsvd2";
1384 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1385 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1386 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1387 };
26e19cdf 1388 kb-row8-ps0 { /* NC */
85afd20e
MZ		 1389 nvidia,pins = "kb_row8_ps0";
1390 nvidia,function = "rsvd2";
1391 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1392 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1393 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1394 };
26e19cdf 1395 kb-row9-ps1 { /* NC */
85afd20e
MZ		 1396 nvidia,pins = "kb_row9_ps1";
1397 nvidia,function = "rsvd2";
1398 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1399 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1400 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1401 };
26e19cdf 1402 kb-row12-ps4 { /* NC */
85afd20e
MZ		 1403 nvidia,pins = "kb_row12_ps4";
1404 nvidia,function = "rsvd2";
1405 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1406 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1407 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1408 };
26e19cdf 1409 kb-row13-ps5 { /* NC */
85afd20e
MZ		 1410 nvidia,pins = "kb_row13_ps5";
1411 nvidia,function = "rsvd2";
1412 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1413 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1414 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1415 };
26e19cdf 1416 kb-row14-ps6 { /* NC */
85afd20e
MZ		 1417 nvidia,pins = "kb_row14_ps6";
1418 nvidia,function = "rsvd2";
1419 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1420 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1421 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1422 };
26e19cdf 1423 kb-row15-ps7 { /* NC */
85afd20e
MZ		 1424 nvidia,pins = "kb_row15_ps7";
1425 nvidia,function = "rsvd3";
1426 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1427 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1428 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1429 };
26e19cdf 1430 kb-row16-pt0 { /* NC */
85afd20e
MZ		 1431 nvidia,pins = "kb_row16_pt0";
1432 nvidia,function = "rsvd2";
1433 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1434 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1435 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1436 };
26e19cdf 1437 kb-row17-pt1 { /* NC */
85afd20e
MZ		 1438 nvidia,pins = "kb_row17_pt1";
1439 nvidia,function = "rsvd2";
1440 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1441 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1442 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1443 };
1444 pu5 { /* NC */
1445 nvidia,pins = "pu5";
1446 nvidia,function = "gmi";
1447 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1448 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1449 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1450 };
1451 pv0 { /* NC */
1452 nvidia,pins = "pv0";
1453 nvidia,function = "rsvd1";
1454 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1455 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1456 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1457 };
1458 pv1 { /* NC */
1459 nvidia,pins = "pv1";
1460 nvidia,function = "rsvd1";
1461 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1462 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1463 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1464 };
26e19cdf 1465 gpio-x1-aud-px1 { /* NC */
85afd20e
MZ		 1466 nvidia,pins = "gpio_x1_aud_px1";
1467 nvidia,function = "rsvd2";
1468 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1469 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1470 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1471 };
26e19cdf 1472 gpio-x3-aud-px3 { /* NC */
85afd20e
MZ		 1473 nvidia,pins = "gpio_x3_aud_px3";
1474 nvidia,function = "rsvd4";
1475 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1476 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1477 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1478 };
1479 pbb7 { /* NC */
1480 nvidia,pins = "pbb7";
1481 nvidia,function = "rsvd2";
1482 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1483 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1484 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1485 };
1486 pcc1 { /* NC */
1487 nvidia,pins = "pcc1";
1488 nvidia,function = "rsvd2";
1489 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1490 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1491 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1492 };
1493 pcc2 { /* NC */
1494 nvidia,pins = "pcc2";
1495 nvidia,function = "rsvd2";
1496 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1497 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1498 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1499 };
26e19cdf 1500 clk3-req-pee1 { /* NC */
85afd20e
MZ		 1501 nvidia,pins = "clk3_req_pee1";
1502 nvidia,function = "rsvd2";
1503 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1504 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1505 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1506 };
26e19cdf 1507 dap-mclk1-req-pee2 { /* NC */
85afd20e
MZ		 1508 nvidia,pins = "dap_mclk1_req_pee2";
1509 nvidia,function = "rsvd4";
1510 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1511 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1512 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1513 };
5142bd65
MZ		 1514 /*
1515 * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
1516 * driver enabled aka not tristated and input driver
1517 * enabled as well as it features some magic properties
1518 * even though the external loopback is disabled and the
1519 * internal loopback used as per
1520 * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
1521 * bits being set to 0xfffd according to the TRM!
1522 */
26e19cdf 1523 sdmmc3-clk-lb-out-pee4 { /* NC */
5142bd65
MZ		 1524 nvidia,pins = "sdmmc3_clk_lb_out_pee4";
1525 nvidia,function = "sdmmc3";
1526 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1527 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1528 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1529 };
85afd20e
MZ		 1530 };
1531 };
1532
1533 serial@70006040 {
b036a75a 1534 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
85afd20e
MZ		 1535 };
1536
1537 serial@70006200 {
b036a75a 1538 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
85afd20e
MZ		 1539 };
1540
1541 serial@70006300 {
b036a75a 1542 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
85afd20e
MZ		 1543 };
1544
1545 hdmi_ddc: i2c@7000c400 {
1c3389e6 1546 clock-frequency = <10000>;
85afd20e
MZ		 1547 };
1548
1549 /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
1550 i2c@7000d000 {
1551 status = "okay";
1552 clock-frequency = <400000>;
1553
1554 /* SGTL5000 audio codec */
5e8a724d 1555 sgtl5000: codec@a {
85afd20e
MZ		 1556 compatible = "fsl,sgtl5000";
1557 reg = <0x0a>;
8c3a9d21
MZ		 1558 VDDA-supply = <&reg_module_3v3_audio>;
1559 VDDD-supply = <&reg_1v8_vddio>;
1bef3a57 1560 VDDIO-supply = <&reg_1v8_vddio>;
85afd20e
MZ		 1561 clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
1562 };
1563
1564 pmic: pmic@40 {
1565 compatible = "ams,as3722";
1566 reg = <0x40>;
1567 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
85afd20e 1568 ams,system-power-controller;
85afd20e
MZ		 1569 #interrupt-cells = <2>;
1570 interrupt-controller;
85afd20e
MZ		 1571 gpio-controller;
1572 #gpio-cells = <2>;
85afd20e
MZ		 1573 pinctrl-names = "default";
1574 pinctrl-0 = <&as3722_default>;
1575
1576 as3722_default: pinmux {
26e19cdf 1577 gpio2-7 {
85afd20e
MZ		 1578 pins = "gpio2", /* PWR_EN_+V3.3 */
1579 "gpio7"; /* +V1.6_LPO */
1580 function = "gpio";
1581 bias-pull-up;
1582 };
1583
26e19cdf 1584 gpio0-1-3-4-5-6 {
405698f0
MZ		 1585 pins = "gpio0", "gpio1", "gpio3",
1586 "gpio4", "gpio5", "gpio6";
85afd20e
MZ		 1587 bias-high-impedance;
1588 };
1589 };
1590
1591 regulators {
1bef3a57
MZ		 1592 vsup-sd2-supply = <&reg_module_3v3>;
1593 vsup-sd3-supply = <&reg_module_3v3>;
1594 vsup-sd4-supply = <&reg_module_3v3>;
1595 vsup-sd5-supply = <&reg_module_3v3>;
1596 vin-ldo0-supply = <&reg_1v35_vddio_ddr>;
1597 vin-ldo1-6-supply = <&reg_module_3v3>;
1598 vin-ldo2-5-7-supply = <&reg_1v8_vddio>;
1599 vin-ldo3-4-supply = <&reg_module_3v3>;
1600 vin-ldo9-10-supply = <&reg_module_3v3>;
1601 vin-ldo11-supply = <&reg_module_3v3>;
1602
1603 reg_vdd_cpu: sd0 {
85afd20e
MZ		 1604 regulator-name = "+VDD_CPU_AP";
1605 regulator-min-microvolt = <700000>;
1606 regulator-max-microvolt = <1400000>;
1607 regulator-min-microamp = <3500000>;
1608 regulator-max-microamp = <3500000>;
1609 regulator-always-on;
1610 regulator-boot-on;
1611 ams,ext-control = <2>;
1612 };
1613
1614 sd1 {
1615 regulator-name = "+VDD_CORE";
1616 regulator-min-microvolt = <700000>;
1617 regulator-max-microvolt = <1350000>;
1618 regulator-min-microamp = <2500000>;
1619 regulator-max-microamp = <4000000>;
1620 regulator-always-on;
1621 regulator-boot-on;
1622 ams,ext-control = <1>;
1623 };
1624
1bef3a57 1625 reg_1v35_vddio_ddr: sd2 {
85afd20e
MZ		 1626 regulator-name =
1627 "+V1.35_VDDIO_DDR(sd2)";
1628 regulator-min-microvolt = <1350000>;
1629 regulator-max-microvolt = <1350000>;
1630 regulator-always-on;
1631 regulator-boot-on;
1632 };
1633
1634 sd3 {
1635 regulator-name =
1636 "+V1.35_VDDIO_DDR(sd3)";
1637 regulator-min-microvolt = <1350000>;
1638 regulator-max-microvolt = <1350000>;
1639 regulator-always-on;
1640 regulator-boot-on;
1641 };
1642
1bef3a57 1643 reg_1v05_vdd: sd4 {
85afd20e
MZ		 1644 regulator-name = "+V1.05";
1645 regulator-min-microvolt = <1050000>;
1646 regulator-max-microvolt = <1050000>;
1647 };
1648
1bef3a57 1649 reg_1v8_vddio: sd5 {
85afd20e
MZ		 1650 regulator-name = "+V1.8";
1651 regulator-min-microvolt = <1800000>;
1652 regulator-max-microvolt = <1800000>;
1653 regulator-boot-on;
1654 regulator-always-on;
1655 };
1656
1bef3a57 1657 reg_vdd_gpu: sd6 {
85afd20e
MZ		 1658 regulator-name = "+VDD_GPU_AP";
1659 regulator-min-microvolt = <650000>;
1660 regulator-max-microvolt = <1200000>;
1661 regulator-min-microamp = <3500000>;
1662 regulator-max-microamp = <3500000>;
1663 regulator-boot-on;
1664 regulator-always-on;
1665 };
1666
1bef3a57 1667 reg_1v05_avdd: ldo0 {
85afd20e
MZ		 1668 regulator-name = "+V1.05_AVDD";
1669 regulator-min-microvolt = <1050000>;
1670 regulator-max-microvolt = <1050000>;
1671 regulator-boot-on;
1672 regulator-always-on;
1673 ams,ext-control = <1>;
1674 };
1675
1676 vddio_sdmmc1: ldo1 {
1677 regulator-name = "VDDIO_SDMMC1";
1678 regulator-min-microvolt = <1800000>;
1679 regulator-max-microvolt = <3300000>;
1680 };
1681
1682 ldo2 {
1683 regulator-name = "+V1.2";
1684 regulator-min-microvolt = <1200000>;
1685 regulator-max-microvolt = <1200000>;
1686 regulator-boot-on;
1687 regulator-always-on;
1688 };
1689
1690 ldo3 {
1691 regulator-name = "+V1.05_RTC";
1692 regulator-min-microvolt = <1000000>;
1693 regulator-max-microvolt = <1000000>;
1694 regulator-boot-on;
1695 regulator-always-on;
1696 ams,enable-tracking;
1697 };
1698
1699 /* 1.8V for LVDS, 3.3V for eDP */
1700 ldo4 {
1701 regulator-name = "AVDD_LVDS0_PLL";
1702 regulator-min-microvolt = <1800000>;
1703 regulator-max-microvolt = <1800000>;
1704 };
1705
1706 /* LDO5 not used */
1707
1708 vddio_sdmmc3: ldo6 {
1709 regulator-name = "VDDIO_SDMMC3";
1710 regulator-min-microvolt = <1800000>;
1711 regulator-max-microvolt = <3300000>;
1712 };
1713
1714 /* LDO7 not used */
1715
1716 ldo9 {
1717 regulator-name = "+V3.3_ETH(ldo9)";
1718 regulator-min-microvolt = <3300000>;
1719 regulator-max-microvolt = <3300000>;
1720 regulator-always-on;
1721 };
1722
1723 ldo10 {
1724 regulator-name = "+V3.3_ETH(ldo10)";
1725 regulator-min-microvolt = <3300000>;
1726 regulator-max-microvolt = <3300000>;
1727 regulator-always-on;
1728 };
1729
1730 ldo11 {
1731 regulator-name = "+V1.8_VPP_FUSE";
1732 regulator-min-microvolt = <1800000>;
1733 regulator-max-microvolt = <1800000>;
1734 };
1735 };
1736 };
1737
1738 /*
1739 * TMP451 temperature sensor
1740 * Note: THERM_N directly connected to AS3722 PMIC THERM
1741 */
6253f885 1742 temp-sensor@4c {
85afd20e
MZ		 1743 compatible = "ti,tmp451";
1744 reg = <0x4c>;
1745 interrupt-parent = <&gpio>;
1746 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
85afd20e 1747 #thermal-sensor-cells = <1>;
8c3a9d21 1748 vcc-supply = <&reg_module_3v3>;
85afd20e
MZ		 1749 };
1750 };
1751
1752 /* SPI2: MCU SPI */
1753 spi@7000d600 {
1754 status = "okay";
1755 spi-max-frequency = <25000000>;
1756 };
1757
1758 pmc@7000e400 {
1759 nvidia,invert-interrupt;
1760 nvidia,suspend-mode = <1>;
1761 nvidia,cpu-pwr-good-time = <500>;
1762 nvidia,cpu-pwr-off-time = <300>;
1763 nvidia,core-pwr-good-time = <641 3845>;
1764 nvidia,core-pwr-off-time = <61036>;
1765 nvidia,core-power-req-active-high;
1766 nvidia,sys-clock-req-active-high;
1767
1768 /* Set power_off bit in ResetControl register of AS3722 PMIC */
1769 i2c-thermtrip {
1770 nvidia,i2c-controller-id = <4>;
1771 nvidia,bus-addr = <0x40>;
1772 nvidia,reg-addr = <0x36>;
1773 nvidia,reg-data = <0x2>;
1774 };
1775 };
1776
1777 sata@70020000 {
1778 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
1779 phy-names = "sata-0";
1bef3a57
MZ		 1780 avdd-supply = <&reg_1v05_vdd>;
1781 hvdd-supply = <&reg_module_3v3>;
1782 vddio-supply = <&reg_1v05_vdd>;
85afd20e
MZ		 1783 };
1784
1785 usb@70090000 {
1786 /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
1787 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
1788 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
1789 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
1790 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
1791 <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
1792 phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
1bef3a57
MZ		 1793 avddio-pex-supply = <&reg_1v05_vdd>;
1794 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
1795 avdd-pll-utmip-supply = <&reg_1v8_vddio>;
1796 avdd-usb-ss-pll-supply = <&reg_1v05_vdd>;
1797 avdd-usb-supply = <&reg_module_3v3>;
1798 dvddio-pex-supply = <&reg_1v05_vdd>;
1799 hvdd-usb-ss-pll-e-supply = <&reg_module_3v3>;
1800 hvdd-usb-ss-supply = <&reg_module_3v3>;
85afd20e
MZ		 1801 };
1802
1803 padctl@7009f000 {
0c2f4ebb
TR		 1804 avdd-pll-utmip-supply = <&reg_1v8_vddio>;
1805 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
1806 avdd-pex-pll-supply = <&reg_1v05_vdd>;
1807 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
1808
85afd20e
MZ		 1809 pads {
1810 usb2 {
1811 status = "okay";
1812
1813 lanes {
1814 usb2-0 {
85afd20e 1815 status = "okay";
a945eae0 1816 nvidia,function = "xusb";
85afd20e
MZ		 1817 };
1818
1819 usb2-1 {
85afd20e 1820 status = "okay";
a945eae0 1821 nvidia,function = "xusb";
85afd20e
MZ		 1822 };
1823
1824 usb2-2 {
85afd20e 1825 status = "okay";
a945eae0 1826 nvidia,function = "xusb";
85afd20e
MZ		 1827 };
1828 };
1829 };
1830
1831 pcie {
1832 status = "okay";
1833
1834 lanes {
1835 pcie-0 {
85afd20e 1836 status = "okay";
a945eae0 1837 nvidia,function = "usb3-ss";
85afd20e
MZ		 1838 };
1839
1840 pcie-1 {
85afd20e 1841 status = "okay";
a945eae0 1842 nvidia,function = "usb3-ss";
85afd20e
MZ		 1843 };
1844
1845 pcie-2 {
85afd20e 1846 status = "okay";
a945eae0 1847 nvidia,function = "pcie";
85afd20e
MZ		 1848 };
1849
1850 pcie-3 {
85afd20e 1851 status = "okay";
a945eae0 1852 nvidia,function = "pcie";
85afd20e
MZ		 1853 };
1854
1855 pcie-4 {
85afd20e 1856 status = "okay";
a945eae0 1857 nvidia,function = "pcie";
85afd20e
MZ		 1858 };
1859 };
1860 };
1861
1862 sata {
1863 status = "okay";
1864
1865 lanes {
1866 sata-0 {
85afd20e 1867 status = "okay";
a945eae0 1868 nvidia,function = "sata";
85afd20e
MZ		 1869 };
1870 };
1871 };
1872 };
1873
1874 ports {
1875 /* USBO1 */
1876 usb2-0 {
1877 status = "okay";
1878 mode = "otg";
85afd20e
MZ		 1879 vbus-supply = <&reg_usbo1_vbus>;
1880 };
1881
1882 /* USBH2 */
1883 usb2-1 {
1884 status = "okay";
1885 mode = "host";
85afd20e
MZ		 1886 vbus-supply = <&reg_usbh_vbus>;
1887 };
1888
1889 /* USBH4 */
1890 usb2-2 {
1891 status = "okay";
1892 mode = "host";
85afd20e
MZ		 1893 vbus-supply = <&reg_usbh_vbus>;
1894 };
1895
1896 usb3-0 {
85afd20e 1897 status = "okay";
a945eae0 1898 nvidia,usb2-companion = <2>;
8c3a9d21 1899 vbus-supply = <&reg_usbh_vbus>;
85afd20e
MZ		 1900 };
1901
1902 usb3-1 {
85afd20e 1903 status = "okay";
a945eae0 1904 nvidia,usb2-companion = <0>;
8c3a9d21 1905 vbus-supply = <&reg_usbo1_vbus>;
85afd20e
MZ		 1906 };
1907 };
1908 };
1909
1910 /* eMMC */
1911 sdhci@700b0600 {
1912 status = "okay";
1913 bus-width = <8>;
1914 non-removable;
fca051b0
MZ		 1915 vmmc-supply = <&reg_module_3v3>; /* VCC */
1916 vqmmc-supply = <&reg_1v8_vddio>; /* VCCQ */
8be6e49a 1917 mmc-ddr-1_8v;
85afd20e
MZ		 1918 };
1919
1920 /* CPU DFLL clock */
1921 clock@70110000 {
1922 status = "okay";
85afd20e 1923 nvidia,i2c-fs-rate = <400000>;
e0cffa9a 1924 vdd-cpu-supply = <&reg_vdd_cpu>;
85afd20e
MZ		 1925 };
1926
1927 ahub@70300000 {
1928 i2s@70301200 {
1929 status = "okay";
1930 };
1931 };
1932
94c3847d
MZ		 1933 clk32k_in: osc3 {
1934 compatible = "fixed-clock";
1935 #clock-cells = <0>;
1936 clock-frequency = <32768>;
85afd20e
MZ		 1937 };
1938
1939 cpus {
1940 cpu@0 {
1bef3a57 1941 vdd-cpu-supply = <&reg_vdd_cpu>;
85afd20e
MZ		 1942 };
1943 };
1944
1945 reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
1946 compatible = "regulator-fixed";
1947 regulator-name = "+V1.05_AVDD_HDMI_PLL";
1948 regulator-min-microvolt = <1050000>;
1949 regulator-max-microvolt = <1050000>;
1950 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1bef3a57 1951 vin-supply = <&reg_1v05_vdd>;
85afd20e
MZ		 1952 };
1953
1954 reg_3v3_mxm: regulator-3v3-mxm {
1955 compatible = "regulator-fixed";
1956 regulator-name = "+V3.3_MXM";
1957 regulator-min-microvolt = <3300000>;
1958 regulator-max-microvolt = <3300000>;
1959 regulator-always-on;
1960 regulator-boot-on;
1961 };
1962
1bef3a57
MZ		 1963 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
1964 compatible = "regulator-fixed";
1965 regulator-name = "+V3.3_AVDD_HDMI";
1966 regulator-min-microvolt = <3300000>;
1967 regulator-max-microvolt = <3300000>;
1968 vin-supply = <&reg_1v05_vdd>;
1969 };
1970
1971 reg_module_3v3: regulator-module-3v3 {
85afd20e
MZ		 1972 compatible = "regulator-fixed";
1973 regulator-name = "+V3.3";
1974 regulator-min-microvolt = <3300000>;
1975 regulator-max-microvolt = <3300000>;
1976 regulator-always-on;
1977 regulator-boot-on;
1978 /* PWR_EN_+V3.3 */
1979 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
1980 enable-active-high;
1981 vin-supply = <&reg_3v3_mxm>;
1982 };
1983
8c3a9d21
MZ		 1984 reg_module_3v3_audio: regulator-module-3v3-audio {
1985 compatible = "regulator-fixed";
1986 regulator-name = "+V3.3_AUDIO_AVDD_S";
1987 regulator-min-microvolt = <3300000>;
1988 regulator-max-microvolt = <3300000>;
1989 regulator-always-on;
1990 };
1991
85afd20e
MZ		 1992 sound {
1993 compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
1994 "nvidia,tegra-audio-sgtl5000";
1995 nvidia,model = "Toradex Apalis TK1";
1996 nvidia,audio-routing =
1997 "Headphone Jack", "HP_OUT",
1998 "LINE_IN", "Line In Jack",
1999 "MIC_IN", "Mic Jack";
2000 nvidia,i2s-controller = <&tegra_i2s2>;
2001 nvidia,audio-codec = <&sgtl5000>;
2002 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
2003 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
2004 <&tegra_car TEGRA124_CLK_EXTERN1>;
2005 clock-names = "pll_a", "pll_a_out0", "mclk";
2006 };
2007
2008 thermal-zones {
2009 cpu {
2010 trips {
d174e946 2011 cpu-shutdown-trip {
85afd20e
MZ		 2012 temperature = <101000>;
2013 hysteresis = <0>;
2014 type = "critical";
2015 };
2016 };
85afd20e
MZ		 2017 };
2018
2019 mem {
2020 trips {
d174e946 2021 mem-shutdown-trip {
85afd20e
MZ		 2022 temperature = <101000>;
2023 hysteresis = <0>;
2024 type = "critical";
2025 };
2026 };
85afd20e
MZ		 2027 };
2028
2029 gpu {
2030 trips {
d174e946 2031 gpu-shutdown-trip {
85afd20e
MZ		 2032 temperature = <101000>;
2033 hysteresis = <0>;
2034 type = "critical";
2035 };
2036 };
85afd20e
MZ		 2037 };
2038 };
2039};
818e8729
MZ		 2040
2041&gpio {
2042 /* I210 Gigabit Ethernet Controller Reset */
26e19cdf 2043 lan-reset-n {
818e8729
MZ		 2044 gpio-hog;
2045 gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
2046 output-high;
2047 line-name = "LAN_RESET_N";
2048 };
2049
2050 /* Control MXM3 pin 26 Reset Module Output Carrier Input */
26e19cdf 2051 reset-moci-ctrl {
818e8729
MZ		 2052 gpio-hog;
2053 gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
2054 output-high;
2055 line-name = "RESET_MOCI_CTRL";
2056 };
2057};
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