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Commit | Line | Data |
---|---|---|
15e524a4 SW |
1 | /dts-v1/; |
2 | ||
3 | #include <dt-bindings/input/input.h> | |
4 | #include "tegra124.dtsi" | |
5 | ||
6 | / { | |
7 | model = "NVIDIA Tegra124 Jetson TK1"; | |
8 | compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; | |
9 | ||
10 | aliases { | |
11 | rtc0 = "/i2c@0,7000d000/pmic@40"; | |
12 | rtc1 = "/rtc@0,7000e000"; | |
13 | }; | |
14 | ||
15 | memory { | |
16 | reg = <0x0 0x80000000 0x0 0x80000000>; | |
17 | }; | |
18 | ||
6054dd39 TR |
19 | host1x@0,50000000 { |
20 | hdmi@0,54280000 { | |
21 | status = "okay"; | |
22 | ||
23 | hdmi-supply = <&vdd_5v0_hdmi>; | |
24 | pll-supply = <&vdd_hdmi_pll>; | |
25 | vdd-supply = <&vdd_3v3_hdmi>; | |
26 | ||
27 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
28 | nvidia,hpd-gpio = | |
29 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | |
30 | }; | |
31 | }; | |
32 | ||
15e524a4 | 33 | pinmux: pinmux@0,70000868 { |
6dbaff2b SW |
34 | pinctrl-names = "boot"; |
35 | pinctrl-0 = <&state_boot>; | |
15e524a4 | 36 | |
6dbaff2b | 37 | state_boot: pinmux { |
15e524a4 SW |
38 | clk_32k_out_pa0 { |
39 | nvidia,pins = "clk_32k_out_pa0"; | |
40 | nvidia,function = "soc"; | |
41 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
42 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
43 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
44 | }; | |
45 | uart3_cts_n_pa1 { | |
46 | nvidia,pins = "uart3_cts_n_pa1"; | |
47 | nvidia,function = "uartc"; | |
48 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
49 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
50 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
51 | }; | |
52 | dap2_fs_pa2 { | |
53 | nvidia,pins = "dap2_fs_pa2"; | |
54 | nvidia,function = "i2s1"; | |
55 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
56 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
57 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
58 | }; | |
59 | dap2_sclk_pa3 { | |
60 | nvidia,pins = "dap2_sclk_pa3"; | |
61 | nvidia,function = "i2s1"; | |
62 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
63 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
64 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
65 | }; | |
66 | dap2_din_pa4 { | |
67 | nvidia,pins = "dap2_din_pa4"; | |
68 | nvidia,function = "i2s1"; | |
69 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
70 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
71 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
72 | }; | |
73 | dap2_dout_pa5 { | |
74 | nvidia,pins = "dap2_dout_pa5"; | |
75 | nvidia,function = "i2s1"; | |
76 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
77 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
78 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
79 | }; | |
80 | sdmmc3_clk_pa6 { | |
81 | nvidia,pins = "sdmmc3_clk_pa6"; | |
82 | nvidia,function = "sdmmc3"; | |
83 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
84 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
85 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
86 | }; | |
87 | sdmmc3_cmd_pa7 { | |
88 | nvidia,pins = "sdmmc3_cmd_pa7"; | |
89 | nvidia,function = "sdmmc3"; | |
90 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
91 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
92 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
93 | }; | |
94 | pb0 { | |
95 | nvidia,pins = "pb0"; | |
96 | nvidia,function = "uartd"; | |
97 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
98 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
99 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
100 | }; | |
101 | pb1 { | |
102 | nvidia,pins = "pb1"; | |
103 | nvidia,function = "uartd"; | |
104 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
105 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
106 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
107 | }; | |
108 | sdmmc3_dat3_pb4 { | |
109 | nvidia,pins = "sdmmc3_dat3_pb4"; | |
110 | nvidia,function = "sdmmc3"; | |
111 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
112 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
113 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
114 | }; | |
115 | sdmmc3_dat2_pb5 { | |
116 | nvidia,pins = "sdmmc3_dat2_pb5"; | |
117 | nvidia,function = "sdmmc3"; | |
118 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
119 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
120 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
121 | }; | |
122 | sdmmc3_dat1_pb6 { | |
123 | nvidia,pins = "sdmmc3_dat1_pb6"; | |
124 | nvidia,function = "sdmmc3"; | |
125 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
126 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
127 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
128 | }; | |
129 | sdmmc3_dat0_pb7 { | |
130 | nvidia,pins = "sdmmc3_dat0_pb7"; | |
131 | nvidia,function = "sdmmc3"; | |
132 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
133 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
134 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
135 | }; | |
136 | uart3_rts_n_pc0 { | |
137 | nvidia,pins = "uart3_rts_n_pc0"; | |
138 | nvidia,function = "uartc"; | |
139 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
140 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
141 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
142 | }; | |
143 | uart2_txd_pc2 { | |
144 | nvidia,pins = "uart2_txd_pc2"; | |
145 | nvidia,function = "irda"; | |
146 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
147 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
148 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
149 | }; | |
150 | uart2_rxd_pc3 { | |
151 | nvidia,pins = "uart2_rxd_pc3"; | |
152 | nvidia,function = "irda"; | |
153 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
154 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
155 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
156 | }; | |
157 | gen1_i2c_scl_pc4 { | |
158 | nvidia,pins = "gen1_i2c_scl_pc4"; | |
159 | nvidia,function = "i2c1"; | |
160 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
161 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
162 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
163 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
164 | }; | |
165 | gen1_i2c_sda_pc5 { | |
166 | nvidia,pins = "gen1_i2c_sda_pc5"; | |
167 | nvidia,function = "i2c1"; | |
168 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
169 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
170 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
171 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
172 | }; | |
173 | pc7 { | |
174 | nvidia,pins = "pc7"; | |
175 | nvidia,function = "rsvd1"; | |
176 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
177 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
178 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
179 | }; | |
180 | pg0 { | |
181 | nvidia,pins = "pg0"; | |
182 | nvidia,function = "rsvd1"; | |
183 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
184 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
185 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
186 | }; | |
187 | pg1 { | |
188 | nvidia,pins = "pg1"; | |
189 | nvidia,function = "rsvd1"; | |
190 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
191 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
192 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
193 | }; | |
194 | pg2 { | |
195 | nvidia,pins = "pg2"; | |
196 | nvidia,function = "rsvd1"; | |
197 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
198 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
199 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
200 | }; | |
201 | pg3 { | |
202 | nvidia,pins = "pg3"; | |
203 | nvidia,function = "rsvd1"; | |
204 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
205 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
206 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
207 | }; | |
208 | pg4 { | |
209 | nvidia,pins = "pg4"; | |
210 | nvidia,function = "spi4"; | |
211 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
212 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
213 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
214 | }; | |
215 | pg5 { | |
216 | nvidia,pins = "pg5"; | |
217 | nvidia,function = "spi4"; | |
218 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
219 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
220 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
221 | }; | |
222 | pg6 { | |
223 | nvidia,pins = "pg6"; | |
224 | nvidia,function = "spi4"; | |
225 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
226 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
227 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
228 | }; | |
229 | pg7 { | |
230 | nvidia,pins = "pg7"; | |
231 | nvidia,function = "spi4"; | |
232 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
233 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
234 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
235 | }; | |
236 | ph0 { | |
237 | nvidia,pins = "ph0"; | |
238 | nvidia,function = "gmi"; | |
239 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
240 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
241 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
242 | }; | |
243 | ph1 { | |
244 | nvidia,pins = "ph1"; | |
245 | nvidia,function = "pwm1"; | |
246 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
247 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
248 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
249 | }; | |
250 | ph2 { | |
251 | nvidia,pins = "ph2"; | |
252 | nvidia,function = "gmi"; | |
253 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
254 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
255 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
256 | }; | |
257 | ph3 { | |
258 | nvidia,pins = "ph3"; | |
259 | nvidia,function = "gmi"; | |
260 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
261 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
262 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
263 | }; | |
264 | ph4 { | |
265 | nvidia,pins = "ph4"; | |
266 | nvidia,function = "rsvd2"; | |
267 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
268 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
269 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
270 | }; | |
271 | ph5 { | |
272 | nvidia,pins = "ph5"; | |
273 | nvidia,function = "rsvd2"; | |
274 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
275 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
276 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
277 | }; | |
278 | ph6 { | |
279 | nvidia,pins = "ph6"; | |
280 | nvidia,function = "gmi"; | |
281 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
282 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
283 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
284 | }; | |
285 | ph7 { | |
286 | nvidia,pins = "ph7"; | |
287 | nvidia,function = "gmi"; | |
288 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
289 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
290 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
291 | }; | |
292 | pi0 { | |
293 | nvidia,pins = "pi0"; | |
294 | nvidia,function = "rsvd1"; | |
295 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
296 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
297 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
298 | }; | |
299 | pi1 { | |
300 | nvidia,pins = "pi1"; | |
301 | nvidia,function = "rsvd1"; | |
302 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
303 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
304 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
305 | }; | |
306 | pi2 { | |
307 | nvidia,pins = "pi2"; | |
308 | nvidia,function = "rsvd4"; | |
309 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
310 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
311 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
312 | }; | |
313 | pi3 { | |
314 | nvidia,pins = "pi3"; | |
315 | nvidia,function = "spi4"; | |
316 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
317 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
318 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
319 | }; | |
320 | pi4 { | |
321 | nvidia,pins = "pi4"; | |
322 | nvidia,function = "gmi"; | |
323 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
324 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
325 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
326 | }; | |
327 | pi5 { | |
328 | nvidia,pins = "pi5"; | |
329 | nvidia,function = "rsvd2"; | |
330 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
331 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
332 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
333 | }; | |
334 | pi6 { | |
335 | nvidia,pins = "pi6"; | |
336 | nvidia,function = "rsvd1"; | |
337 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
338 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
339 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
340 | }; | |
341 | pi7 { | |
342 | nvidia,pins = "pi7"; | |
343 | nvidia,function = "rsvd1"; | |
344 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
345 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
346 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
347 | }; | |
348 | pj0 { | |
349 | nvidia,pins = "pj0"; | |
350 | nvidia,function = "rsvd1"; | |
351 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
352 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
353 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
354 | }; | |
355 | pj2 { | |
356 | nvidia,pins = "pj2"; | |
357 | nvidia,function = "rsvd1"; | |
358 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
359 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
360 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
361 | }; | |
362 | uart2_cts_n_pj5 { | |
363 | nvidia,pins = "uart2_cts_n_pj5"; | |
364 | nvidia,function = "uartb"; | |
365 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
366 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
367 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
368 | }; | |
369 | uart2_rts_n_pj6 { | |
370 | nvidia,pins = "uart2_rts_n_pj6"; | |
371 | nvidia,function = "uartb"; | |
372 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
373 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
374 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
375 | }; | |
376 | pj7 { | |
377 | nvidia,pins = "pj7"; | |
378 | nvidia,function = "uartd"; | |
379 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
380 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
381 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
382 | }; | |
383 | pk0 { | |
384 | nvidia,pins = "pk0"; | |
385 | nvidia,function = "soc"; | |
386 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
387 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
388 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
389 | }; | |
390 | pk1 { | |
391 | nvidia,pins = "pk1"; | |
392 | nvidia,function = "rsvd4"; | |
393 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
394 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
395 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
396 | }; | |
397 | pk2 { | |
398 | nvidia,pins = "pk2"; | |
399 | nvidia,function = "rsvd1"; | |
400 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
401 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
402 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
403 | }; | |
404 | pk3 { | |
405 | nvidia,pins = "pk3"; | |
406 | nvidia,function = "gmi"; | |
407 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
408 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
409 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
410 | }; | |
411 | pk4 { | |
412 | nvidia,pins = "pk4"; | |
413 | nvidia,function = "rsvd2"; | |
414 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
415 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
416 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
417 | }; | |
418 | spdif_out_pk5 { | |
419 | nvidia,pins = "spdif_out_pk5"; | |
420 | nvidia,function = "rsvd2"; | |
421 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
422 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
423 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
424 | }; | |
425 | spdif_in_pk6 { | |
426 | nvidia,pins = "spdif_in_pk6"; | |
427 | nvidia,function = "rsvd2"; | |
428 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
429 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
430 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
431 | }; | |
432 | pk7 { | |
433 | nvidia,pins = "pk7"; | |
434 | nvidia,function = "uartd"; | |
435 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
436 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
437 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
438 | }; | |
439 | dap1_fs_pn0 { | |
440 | nvidia,pins = "dap1_fs_pn0"; | |
441 | nvidia,function = "i2s0"; | |
442 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
443 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
444 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
445 | }; | |
446 | dap1_din_pn1 { | |
447 | nvidia,pins = "dap1_din_pn1"; | |
448 | nvidia,function = "i2s0"; | |
449 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
450 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
451 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
452 | }; | |
453 | dap1_dout_pn2 { | |
454 | nvidia,pins = "dap1_dout_pn2"; | |
455 | nvidia,function = "sata"; | |
456 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
457 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
458 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
459 | }; | |
460 | dap1_sclk_pn3 { | |
461 | nvidia,pins = "dap1_sclk_pn3"; | |
462 | nvidia,function = "i2s0"; | |
463 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
464 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
465 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
466 | }; | |
467 | usb_vbus_en0_pn4 { | |
468 | nvidia,pins = "usb_vbus_en0_pn4"; | |
469 | nvidia,function = "usb"; | |
470 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
471 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
472 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
473 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
474 | }; | |
475 | usb_vbus_en1_pn5 { | |
476 | nvidia,pins = "usb_vbus_en1_pn5"; | |
477 | nvidia,function = "usb"; | |
478 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
479 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
480 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
481 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
482 | }; | |
483 | hdmi_int_pn7 { | |
484 | nvidia,pins = "hdmi_int_pn7"; | |
485 | nvidia,function = "rsvd1"; | |
486 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
487 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
488 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
489 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
490 | }; | |
491 | ulpi_data7_po0 { | |
492 | nvidia,pins = "ulpi_data7_po0"; | |
493 | nvidia,function = "ulpi"; | |
494 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
495 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
496 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
497 | }; | |
498 | ulpi_data0_po1 { | |
499 | nvidia,pins = "ulpi_data0_po1"; | |
500 | nvidia,function = "ulpi"; | |
501 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
502 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
503 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
504 | }; | |
505 | ulpi_data1_po2 { | |
506 | nvidia,pins = "ulpi_data1_po2"; | |
507 | nvidia,function = "ulpi"; | |
508 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
509 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
510 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
511 | }; | |
512 | ulpi_data2_po3 { | |
513 | nvidia,pins = "ulpi_data2_po3"; | |
514 | nvidia,function = "ulpi"; | |
515 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
516 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
517 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
518 | }; | |
519 | ulpi_data3_po4 { | |
520 | nvidia,pins = "ulpi_data3_po4"; | |
521 | nvidia,function = "ulpi"; | |
522 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
523 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
524 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
525 | }; | |
526 | ulpi_data4_po5 { | |
527 | nvidia,pins = "ulpi_data4_po5"; | |
528 | nvidia,function = "ulpi"; | |
529 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
530 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
531 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
532 | }; | |
533 | ulpi_data5_po6 { | |
534 | nvidia,pins = "ulpi_data5_po6"; | |
535 | nvidia,function = "ulpi"; | |
536 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
537 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
538 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
539 | }; | |
540 | ulpi_data6_po7 { | |
541 | nvidia,pins = "ulpi_data6_po7"; | |
542 | nvidia,function = "ulpi"; | |
543 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
544 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
545 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
546 | }; | |
547 | dap3_fs_pp0 { | |
548 | nvidia,pins = "dap3_fs_pp0"; | |
549 | nvidia,function = "i2s2"; | |
550 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
551 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
552 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
553 | }; | |
554 | dap3_din_pp1 { | |
555 | nvidia,pins = "dap3_din_pp1"; | |
556 | nvidia,function = "i2s2"; | |
557 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
558 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
559 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
560 | }; | |
561 | dap3_dout_pp2 { | |
562 | nvidia,pins = "dap3_dout_pp2"; | |
563 | nvidia,function = "rsvd4"; | |
564 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
565 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
566 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
567 | }; | |
568 | dap3_sclk_pp3 { | |
569 | nvidia,pins = "dap3_sclk_pp3"; | |
570 | nvidia,function = "rsvd3"; | |
571 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
572 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
573 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
574 | }; | |
575 | dap4_fs_pp4 { | |
576 | nvidia,pins = "dap4_fs_pp4"; | |
577 | nvidia,function = "i2s3"; | |
578 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
579 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
580 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
581 | }; | |
582 | dap4_din_pp5 { | |
583 | nvidia,pins = "dap4_din_pp5"; | |
584 | nvidia,function = "i2s3"; | |
585 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
586 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
587 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
588 | }; | |
589 | dap4_dout_pp6 { | |
590 | nvidia,pins = "dap4_dout_pp6"; | |
591 | nvidia,function = "i2s3"; | |
592 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
593 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
594 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
595 | }; | |
596 | dap4_sclk_pp7 { | |
597 | nvidia,pins = "dap4_sclk_pp7"; | |
598 | nvidia,function = "i2s3"; | |
599 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
600 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
601 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
602 | }; | |
603 | kb_col0_pq0 { | |
604 | nvidia,pins = "kb_col0_pq0"; | |
605 | nvidia,function = "rsvd2"; | |
606 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
607 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
608 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
609 | }; | |
610 | kb_col1_pq1 { | |
611 | nvidia,pins = "kb_col1_pq1"; | |
612 | nvidia,function = "rsvd2"; | |
613 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
614 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
615 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
616 | }; | |
617 | kb_col2_pq2 { | |
618 | nvidia,pins = "kb_col2_pq2"; | |
619 | nvidia,function = "rsvd2"; | |
620 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
621 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
622 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
623 | }; | |
624 | kb_col3_pq3 { | |
625 | nvidia,pins = "kb_col3_pq3"; | |
626 | nvidia,function = "kbc"; | |
627 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
628 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
629 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
630 | }; | |
631 | kb_col4_pq4 { | |
632 | nvidia,pins = "kb_col4_pq4"; | |
633 | nvidia,function = "sdmmc3"; | |
634 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
635 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
636 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
637 | }; | |
638 | kb_col5_pq5 { | |
639 | nvidia,pins = "kb_col5_pq5"; | |
640 | nvidia,function = "rsvd2"; | |
641 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
642 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
643 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
644 | }; | |
645 | kb_col6_pq6 { | |
646 | nvidia,pins = "kb_col6_pq6"; | |
647 | nvidia,function = "rsvd2"; | |
648 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
649 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
650 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
651 | }; | |
652 | kb_col7_pq7 { | |
653 | nvidia,pins = "kb_col7_pq7"; | |
654 | nvidia,function = "rsvd2"; | |
655 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
656 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
657 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
658 | }; | |
659 | kb_row0_pr0 { | |
660 | nvidia,pins = "kb_row0_pr0"; | |
661 | nvidia,function = "rsvd2"; | |
662 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
663 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
664 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
665 | }; | |
666 | kb_row1_pr1 { | |
667 | nvidia,pins = "kb_row1_pr1"; | |
668 | nvidia,function = "rsvd2"; | |
669 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
670 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
671 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
672 | }; | |
673 | kb_row2_pr2 { | |
674 | nvidia,pins = "kb_row2_pr2"; | |
675 | nvidia,function = "rsvd2"; | |
676 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
677 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
678 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
679 | }; | |
680 | kb_row3_pr3 { | |
681 | nvidia,pins = "kb_row3_pr3"; | |
682 | nvidia,function = "sys"; | |
683 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
684 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
685 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
686 | }; | |
687 | kb_row4_pr4 { | |
688 | nvidia,pins = "kb_row4_pr4"; | |
689 | nvidia,function = "rsvd3"; | |
690 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
691 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
692 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
693 | }; | |
694 | kb_row5_pr5 { | |
695 | nvidia,pins = "kb_row5_pr5"; | |
696 | nvidia,function = "rsvd3"; | |
697 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
698 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
699 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
700 | }; | |
701 | kb_row6_pr6 { | |
702 | nvidia,pins = "kb_row6_pr6"; | |
703 | nvidia,function = "displaya_alt"; | |
704 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
705 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
706 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
707 | }; | |
708 | kb_row7_pr7 { | |
709 | nvidia,pins = "kb_row7_pr7"; | |
710 | nvidia,function = "rsvd2"; | |
711 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
712 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
713 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
714 | }; | |
715 | kb_row8_ps0 { | |
716 | nvidia,pins = "kb_row8_ps0"; | |
717 | nvidia,function = "rsvd2"; | |
718 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
719 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
720 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
721 | }; | |
722 | kb_row9_ps1 { | |
723 | nvidia,pins = "kb_row9_ps1"; | |
724 | nvidia,function = "rsvd2"; | |
725 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
726 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
727 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
728 | }; | |
729 | kb_row10_ps2 { | |
730 | nvidia,pins = "kb_row10_ps2"; | |
731 | nvidia,function = "rsvd2"; | |
732 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
733 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
734 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
735 | }; | |
736 | kb_row11_ps3 { | |
737 | nvidia,pins = "kb_row11_ps3"; | |
738 | nvidia,function = "rsvd2"; | |
739 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
740 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
741 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
742 | }; | |
743 | kb_row12_ps4 { | |
744 | nvidia,pins = "kb_row12_ps4"; | |
745 | nvidia,function = "rsvd2"; | |
746 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
747 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
748 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
749 | }; | |
750 | kb_row13_ps5 { | |
751 | nvidia,pins = "kb_row13_ps5"; | |
752 | nvidia,function = "rsvd2"; | |
753 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
754 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
755 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
756 | }; | |
757 | kb_row14_ps6 { | |
758 | nvidia,pins = "kb_row14_ps6"; | |
759 | nvidia,function = "rsvd2"; | |
760 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
761 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
762 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
763 | }; | |
764 | kb_row15_ps7 { | |
765 | nvidia,pins = "kb_row15_ps7"; | |
766 | nvidia,function = "soc"; | |
767 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
768 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
769 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
770 | }; | |
771 | kb_row16_pt0 { | |
772 | nvidia,pins = "kb_row16_pt0"; | |
773 | nvidia,function = "rsvd2"; | |
774 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
775 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
776 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
777 | }; | |
778 | kb_row17_pt1 { | |
779 | nvidia,pins = "kb_row17_pt1"; | |
780 | nvidia,function = "rsvd2"; | |
781 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
782 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
783 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
784 | }; | |
785 | gen2_i2c_scl_pt5 { | |
786 | nvidia,pins = "gen2_i2c_scl_pt5"; | |
787 | nvidia,function = "i2c2"; | |
788 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
789 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
790 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
791 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
792 | }; | |
793 | gen2_i2c_sda_pt6 { | |
794 | nvidia,pins = "gen2_i2c_sda_pt6"; | |
795 | nvidia,function = "i2c2"; | |
796 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
797 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
798 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
799 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
800 | }; | |
801 | sdmmc4_cmd_pt7 { | |
802 | nvidia,pins = "sdmmc4_cmd_pt7"; | |
803 | nvidia,function = "sdmmc4"; | |
804 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
805 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
806 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
807 | }; | |
808 | pu0 { | |
809 | nvidia,pins = "pu0"; | |
810 | nvidia,function = "rsvd4"; | |
811 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
812 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
813 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
814 | }; | |
815 | pu1 { | |
816 | nvidia,pins = "pu1"; | |
817 | nvidia,function = "rsvd1"; | |
818 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
819 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
820 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
821 | }; | |
822 | pu2 { | |
823 | nvidia,pins = "pu2"; | |
824 | nvidia,function = "rsvd1"; | |
825 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
826 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
827 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
828 | }; | |
829 | pu3 { | |
830 | nvidia,pins = "pu3"; | |
831 | nvidia,function = "gmi"; | |
832 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
833 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
834 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
835 | }; | |
836 | pu4 { | |
837 | nvidia,pins = "pu4"; | |
838 | nvidia,function = "gmi"; | |
839 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
840 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
841 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
842 | }; | |
843 | pu5 { | |
844 | nvidia,pins = "pu5"; | |
845 | nvidia,function = "gmi"; | |
846 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
847 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
848 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
849 | }; | |
850 | pu6 { | |
851 | nvidia,pins = "pu6"; | |
852 | nvidia,function = "rsvd3"; | |
853 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
854 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
855 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
856 | }; | |
857 | pv0 { | |
858 | nvidia,pins = "pv0"; | |
859 | nvidia,function = "rsvd1"; | |
860 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
861 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
862 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
863 | }; | |
864 | pv1 { | |
865 | nvidia,pins = "pv1"; | |
866 | nvidia,function = "rsvd1"; | |
867 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
868 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
869 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
870 | }; | |
871 | sdmmc3_cd_n_pv2 { | |
872 | nvidia,pins = "sdmmc3_cd_n_pv2"; | |
873 | nvidia,function = "sdmmc3"; | |
874 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
875 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
876 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
877 | }; | |
878 | sdmmc1_wp_n_pv3 { | |
879 | nvidia,pins = "sdmmc1_wp_n_pv3"; | |
880 | nvidia,function = "sdmmc1"; | |
881 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
882 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
883 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
884 | }; | |
885 | ddc_scl_pv4 { | |
886 | nvidia,pins = "ddc_scl_pv4"; | |
887 | nvidia,function = "i2c4"; | |
888 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
889 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
890 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
891 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
892 | }; | |
893 | ddc_sda_pv5 { | |
894 | nvidia,pins = "ddc_sda_pv5"; | |
895 | nvidia,function = "i2c4"; | |
896 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
897 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
898 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
899 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
900 | }; | |
901 | gpio_w2_aud_pw2 { | |
902 | nvidia,pins = "gpio_w2_aud_pw2"; | |
903 | nvidia,function = "rsvd2"; | |
904 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
905 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
906 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
907 | }; | |
908 | gpio_w3_aud_pw3 { | |
909 | nvidia,pins = "gpio_w3_aud_pw3"; | |
910 | nvidia,function = "spi6"; | |
911 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
912 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
913 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
914 | }; | |
915 | dap_mclk1_pw4 { | |
916 | nvidia,pins = "dap_mclk1_pw4"; | |
917 | nvidia,function = "extperiph1"; | |
918 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
919 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
920 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
921 | }; | |
922 | clk2_out_pw5 { | |
923 | nvidia,pins = "clk2_out_pw5"; | |
924 | nvidia,function = "extperiph2"; | |
925 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
926 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
927 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
928 | }; | |
929 | uart3_txd_pw6 { | |
930 | nvidia,pins = "uart3_txd_pw6"; | |
931 | nvidia,function = "uartc"; | |
932 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
933 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
934 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
935 | }; | |
936 | uart3_rxd_pw7 { | |
937 | nvidia,pins = "uart3_rxd_pw7"; | |
938 | nvidia,function = "uartc"; | |
939 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
940 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
941 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
942 | }; | |
943 | dvfs_pwm_px0 { | |
944 | nvidia,pins = "dvfs_pwm_px0"; | |
945 | nvidia,function = "cldvfs"; | |
946 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
947 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
948 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
949 | }; | |
950 | gpio_x1_aud_px1 { | |
951 | nvidia,pins = "gpio_x1_aud_px1"; | |
952 | nvidia,function = "rsvd2"; | |
953 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
954 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
955 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
956 | }; | |
957 | dvfs_clk_px2 { | |
958 | nvidia,pins = "dvfs_clk_px2"; | |
959 | nvidia,function = "cldvfs"; | |
960 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
961 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
962 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
963 | }; | |
964 | gpio_x3_aud_px3 { | |
965 | nvidia,pins = "gpio_x3_aud_px3"; | |
966 | nvidia,function = "rsvd4"; | |
967 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
968 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
969 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
970 | }; | |
971 | gpio_x4_aud_px4 { | |
972 | nvidia,pins = "gpio_x4_aud_px4"; | |
973 | nvidia,function = "gmi"; | |
974 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
975 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
976 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
977 | }; | |
978 | gpio_x5_aud_px5 { | |
979 | nvidia,pins = "gpio_x5_aud_px5"; | |
980 | nvidia,function = "rsvd4"; | |
981 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
982 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
983 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
984 | }; | |
985 | gpio_x6_aud_px6 { | |
986 | nvidia,pins = "gpio_x6_aud_px6"; | |
987 | nvidia,function = "gmi"; | |
988 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
989 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
990 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
991 | }; | |
992 | gpio_x7_aud_px7 { | |
993 | nvidia,pins = "gpio_x7_aud_px7"; | |
994 | nvidia,function = "rsvd1"; | |
995 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
996 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
997 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
998 | }; | |
999 | ulpi_clk_py0 { | |
1000 | nvidia,pins = "ulpi_clk_py0"; | |
1001 | nvidia,function = "spi1"; | |
1002 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1003 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1004 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1005 | }; | |
1006 | ulpi_dir_py1 { | |
1007 | nvidia,pins = "ulpi_dir_py1"; | |
1008 | nvidia,function = "spi1"; | |
1009 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1010 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1011 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1012 | }; | |
1013 | ulpi_nxt_py2 { | |
1014 | nvidia,pins = "ulpi_nxt_py2"; | |
1015 | nvidia,function = "spi1"; | |
1016 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1017 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1018 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1019 | }; | |
1020 | ulpi_stp_py3 { | |
1021 | nvidia,pins = "ulpi_stp_py3"; | |
1022 | nvidia,function = "spi1"; | |
1023 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1024 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1025 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1026 | }; | |
1027 | sdmmc1_dat3_py4 { | |
1028 | nvidia,pins = "sdmmc1_dat3_py4"; | |
1029 | nvidia,function = "sdmmc1"; | |
1030 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1031 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1032 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1033 | }; | |
1034 | sdmmc1_dat2_py5 { | |
1035 | nvidia,pins = "sdmmc1_dat2_py5"; | |
1036 | nvidia,function = "sdmmc1"; | |
1037 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1038 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1039 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1040 | }; | |
1041 | sdmmc1_dat1_py6 { | |
1042 | nvidia,pins = "sdmmc1_dat1_py6"; | |
1043 | nvidia,function = "sdmmc1"; | |
1044 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1045 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1046 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1047 | }; | |
1048 | sdmmc1_dat0_py7 { | |
1049 | nvidia,pins = "sdmmc1_dat0_py7"; | |
1050 | nvidia,function = "sdmmc1"; | |
1051 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1052 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1053 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1054 | }; | |
1055 | sdmmc1_clk_pz0 { | |
1056 | nvidia,pins = "sdmmc1_clk_pz0"; | |
1057 | nvidia,function = "sdmmc1"; | |
1058 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1059 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1060 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1061 | }; | |
1062 | sdmmc1_cmd_pz1 { | |
1063 | nvidia,pins = "sdmmc1_cmd_pz1"; | |
1064 | nvidia,function = "sdmmc1"; | |
1065 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1066 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1067 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1068 | }; | |
1069 | pwr_i2c_scl_pz6 { | |
1070 | nvidia,pins = "pwr_i2c_scl_pz6"; | |
1071 | nvidia,function = "i2cpwr"; | |
1072 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1073 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1074 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1075 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1076 | }; | |
1077 | pwr_i2c_sda_pz7 { | |
1078 | nvidia,pins = "pwr_i2c_sda_pz7"; | |
1079 | nvidia,function = "i2cpwr"; | |
1080 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1081 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1082 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1083 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1084 | }; | |
1085 | sdmmc4_dat0_paa0 { | |
1086 | nvidia,pins = "sdmmc4_dat0_paa0"; | |
1087 | nvidia,function = "sdmmc4"; | |
1088 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1089 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1090 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1091 | }; | |
1092 | sdmmc4_dat1_paa1 { | |
1093 | nvidia,pins = "sdmmc4_dat1_paa1"; | |
1094 | nvidia,function = "sdmmc4"; | |
1095 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1096 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1097 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1098 | }; | |
1099 | sdmmc4_dat2_paa2 { | |
1100 | nvidia,pins = "sdmmc4_dat2_paa2"; | |
1101 | nvidia,function = "sdmmc4"; | |
1102 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1103 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1104 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1105 | }; | |
1106 | sdmmc4_dat3_paa3 { | |
1107 | nvidia,pins = "sdmmc4_dat3_paa3"; | |
1108 | nvidia,function = "sdmmc4"; | |
1109 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1110 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1111 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1112 | }; | |
1113 | sdmmc4_dat4_paa4 { | |
1114 | nvidia,pins = "sdmmc4_dat4_paa4"; | |
1115 | nvidia,function = "sdmmc4"; | |
1116 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1117 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1118 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1119 | }; | |
1120 | sdmmc4_dat5_paa5 { | |
1121 | nvidia,pins = "sdmmc4_dat5_paa5"; | |
1122 | nvidia,function = "sdmmc4"; | |
1123 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1124 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1125 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1126 | }; | |
1127 | sdmmc4_dat6_paa6 { | |
1128 | nvidia,pins = "sdmmc4_dat6_paa6"; | |
1129 | nvidia,function = "sdmmc4"; | |
1130 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1131 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1132 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1133 | }; | |
1134 | sdmmc4_dat7_paa7 { | |
1135 | nvidia,pins = "sdmmc4_dat7_paa7"; | |
1136 | nvidia,function = "sdmmc4"; | |
1137 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1138 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1139 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1140 | }; | |
1141 | pbb0 { | |
1142 | nvidia,pins = "pbb0"; | |
1143 | nvidia,function = "vimclk2_alt"; | |
1144 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1145 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1146 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1147 | }; | |
1148 | cam_i2c_scl_pbb1 { | |
1149 | nvidia,pins = "cam_i2c_scl_pbb1"; | |
1150 | nvidia,function = "i2c3"; | |
1151 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1152 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1153 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1154 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1155 | }; | |
1156 | cam_i2c_sda_pbb2 { | |
1157 | nvidia,pins = "cam_i2c_sda_pbb2"; | |
1158 | nvidia,function = "i2c3"; | |
1159 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1160 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1161 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1162 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1163 | }; | |
1164 | pbb3 { | |
1165 | nvidia,pins = "pbb3"; | |
1166 | nvidia,function = "vgp3"; | |
1167 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1168 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1169 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1170 | }; | |
1171 | pbb4 { | |
1172 | nvidia,pins = "pbb4"; | |
1173 | nvidia,function = "vgp4"; | |
1174 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1175 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1176 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1177 | }; | |
1178 | pbb5 { | |
1179 | nvidia,pins = "pbb5"; | |
1180 | nvidia,function = "rsvd3"; | |
1181 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1182 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1183 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1184 | }; | |
1185 | pbb6 { | |
1186 | nvidia,pins = "pbb6"; | |
1187 | nvidia,function = "rsvd2"; | |
1188 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1189 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1190 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1191 | }; | |
1192 | pbb7 { | |
1193 | nvidia,pins = "pbb7"; | |
1194 | nvidia,function = "rsvd2"; | |
1195 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1196 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1197 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1198 | }; | |
1199 | cam_mclk_pcc0 { | |
1200 | nvidia,pins = "cam_mclk_pcc0"; | |
1201 | nvidia,function = "vi_alt3"; | |
1202 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1203 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1204 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1205 | }; | |
1206 | pcc1 { | |
1207 | nvidia,pins = "pcc1"; | |
1208 | nvidia,function = "rsvd2"; | |
1209 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1210 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1211 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1212 | }; | |
1213 | pcc2 { | |
1214 | nvidia,pins = "pcc2"; | |
1215 | nvidia,function = "rsvd2"; | |
1216 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1217 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1218 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1219 | }; | |
1220 | sdmmc4_clk_pcc4 { | |
1221 | nvidia,pins = "sdmmc4_clk_pcc4"; | |
1222 | nvidia,function = "sdmmc4"; | |
1223 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1224 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1225 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1226 | }; | |
1227 | clk2_req_pcc5 { | |
1228 | nvidia,pins = "clk2_req_pcc5"; | |
1229 | nvidia,function = "rsvd2"; | |
1230 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1231 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1232 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1233 | }; | |
b0da12d5 SW |
1234 | pex_l0_rst_n_pdd1 { |
1235 | nvidia,pins = "pex_l0_rst_n_pdd1"; | |
1236 | nvidia,function = "pe0"; | |
1237 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1238 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1239 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1240 | }; | |
1241 | pex_l0_clkreq_n_pdd2 { | |
1242 | nvidia,pins = "pex_l0_clkreq_n_pdd2"; | |
1243 | nvidia,function = "pe0"; | |
1244 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1245 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1246 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1247 | }; | |
1248 | pex_wake_n_pdd3 { | |
1249 | nvidia,pins = "pex_wake_n_pdd3"; | |
1250 | nvidia,function = "pe"; | |
1251 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1252 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1253 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1254 | }; | |
1255 | pex_l1_rst_n_pdd5 { | |
1256 | nvidia,pins = "pex_l1_rst_n_pdd5"; | |
1257 | nvidia,function = "pe1"; | |
1258 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1259 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1260 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1261 | }; | |
1262 | pex_l1_clkreq_n_pdd6 { | |
1263 | nvidia,pins = "pex_l1_clkreq_n_pdd6"; | |
1264 | nvidia,function = "pe1"; | |
1265 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1266 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1267 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1268 | }; | |
15e524a4 SW |
1269 | clk3_out_pee0 { |
1270 | nvidia,pins = "clk3_out_pee0"; | |
1271 | nvidia,function = "extperiph3"; | |
1272 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1273 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1274 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1275 | }; | |
1276 | clk3_req_pee1 { | |
1277 | nvidia,pins = "clk3_req_pee1"; | |
1278 | nvidia,function = "rsvd2"; | |
1279 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1280 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1281 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1282 | }; | |
1283 | dap_mclk1_req_pee2 { | |
1284 | nvidia,pins = "dap_mclk1_req_pee2"; | |
1285 | nvidia,function = "sata"; | |
1286 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1287 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1288 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1289 | }; | |
1290 | hdmi_cec_pee3 { | |
1291 | nvidia,pins = "hdmi_cec_pee3"; | |
1292 | nvidia,function = "cec"; | |
1293 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1294 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1295 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1296 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1297 | }; | |
1298 | sdmmc3_clk_lb_out_pee4 { | |
1299 | nvidia,pins = "sdmmc3_clk_lb_out_pee4"; | |
1300 | nvidia,function = "sdmmc3"; | |
1301 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1302 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1303 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1304 | }; | |
1305 | sdmmc3_clk_lb_in_pee5 { | |
1306 | nvidia,pins = "sdmmc3_clk_lb_in_pee5"; | |
1307 | nvidia,function = "sdmmc3"; | |
1308 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1309 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1310 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1311 | }; | |
1312 | dp_hpd_pff0 { | |
1313 | nvidia,pins = "dp_hpd_pff0"; | |
1314 | nvidia,function = "dp"; | |
1315 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1316 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1317 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1318 | }; | |
1319 | usb_vbus_en2_pff1 { | |
1320 | nvidia,pins = "usb_vbus_en2_pff1"; | |
1321 | nvidia,function = "rsvd2"; | |
1322 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1323 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1324 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1325 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1326 | }; | |
1327 | pff2 { | |
1328 | nvidia,pins = "pff2"; | |
1329 | nvidia,function = "rsvd2"; | |
1330 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1331 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1332 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1333 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1334 | }; | |
1335 | core_pwr_req { | |
1336 | nvidia,pins = "core_pwr_req"; | |
1337 | nvidia,function = "pwron"; | |
1338 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1339 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1340 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1341 | }; | |
1342 | cpu_pwr_req { | |
1343 | nvidia,pins = "cpu_pwr_req"; | |
1344 | nvidia,function = "rsvd2"; | |
1345 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1346 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1347 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1348 | }; | |
1349 | pwr_int_n { | |
1350 | nvidia,pins = "pwr_int_n"; | |
1351 | nvidia,function = "pmi"; | |
1352 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1353 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1354 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1355 | }; | |
1356 | reset_out_n { | |
1357 | nvidia,pins = "reset_out_n"; | |
1358 | nvidia,function = "reset_out_n"; | |
1359 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1360 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1361 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1362 | }; | |
1363 | owr { | |
1364 | nvidia,pins = "owr"; | |
1365 | nvidia,function = "rsvd2"; | |
1366 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1367 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1368 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1369 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
1370 | }; | |
1371 | clk_32k_in { | |
1372 | nvidia,pins = "clk_32k_in"; | |
1373 | nvidia,function = "rsvd2"; | |
1374 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1375 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1376 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1377 | }; | |
1378 | jtag_rtck { | |
1379 | nvidia,pins = "jtag_rtck"; | |
1380 | nvidia,function = "rtck"; | |
1381 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1382 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1383 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1384 | }; | |
1385 | }; | |
1386 | }; | |
1387 | ||
1388 | /* DB9 serial port */ | |
1389 | serial@0,70006300 { | |
1390 | status = "okay"; | |
1391 | }; | |
1392 | ||
1393 | /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */ | |
1394 | i2c@0,7000c000 { | |
1395 | status = "okay"; | |
1396 | clock-frequency = <100000>; | |
1397 | ||
98de744e SW |
1398 | rt5639: audio-codec@1c { |
1399 | compatible = "realtek,rt5639"; | |
15e524a4 SW |
1400 | reg = <0x1c>; |
1401 | interrupt-parent = <&gpio>; | |
1402 | interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; | |
1403 | realtek,ldo1-en-gpios = | |
1404 | <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; | |
1405 | }; | |
1406 | ||
1407 | temperature-sensor@4c { | |
1408 | compatible = "ti,tmp451"; | |
1409 | reg = <0x4c>; | |
1410 | interrupt-parent = <&gpio>; | |
1411 | interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; | |
1412 | }; | |
1413 | ||
1414 | eeprom@56 { | |
1415 | compatible = "atmel,24c02"; | |
1416 | reg = <0x56>; | |
1417 | pagesize = <8>; | |
1418 | }; | |
1419 | }; | |
1420 | ||
1421 | /* Expansion GEN2_I2C_* */ | |
1422 | i2c@0,7000c400 { | |
1423 | status = "okay"; | |
1424 | clock-frequency = <100000>; | |
1425 | }; | |
1426 | ||
1427 | /* Expansion CAM_I2C_* */ | |
1428 | i2c@0,7000c500 { | |
1429 | status = "okay"; | |
1430 | clock-frequency = <100000>; | |
1431 | }; | |
1432 | ||
1433 | /* HDMI DDC */ | |
6054dd39 | 1434 | hdmi_ddc: i2c@0,7000c700 { |
15e524a4 SW |
1435 | status = "okay"; |
1436 | clock-frequency = <100000>; | |
1437 | }; | |
1438 | ||
1439 | /* Expansion PWR_I2C_*, on-board components */ | |
1440 | i2c@0,7000d000 { | |
1441 | status = "okay"; | |
1442 | clock-frequency = <400000>; | |
1443 | ||
1444 | pmic: pmic@40 { | |
1445 | compatible = "ams,as3722"; | |
1446 | reg = <0x40>; | |
1447 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; | |
1448 | ||
1449 | ams,system-power-controller; | |
1450 | ||
1451 | #interrupt-cells = <2>; | |
1452 | interrupt-controller; | |
1453 | ||
1454 | gpio-controller; | |
1455 | #gpio-cells = <2>; | |
1456 | ||
1457 | pinctrl-names = "default"; | |
1458 | pinctrl-0 = <&as3722_default>; | |
1459 | ||
1460 | as3722_default: pinmux { | |
1461 | gpio0 { | |
1462 | pins = "gpio0"; | |
1463 | function = "gpio"; | |
1464 | bias-pull-down; | |
1465 | }; | |
1466 | ||
1467 | gpio1_2_4_7 { | |
1468 | pins = "gpio1", "gpio2", "gpio4", "gpio7"; | |
1469 | function = "gpio"; | |
1470 | bias-pull-up; | |
1471 | }; | |
1472 | ||
1473 | gpio3_5_6 { | |
1474 | pins = "gpio3", "gpio5", "gpio6"; | |
1475 | bias-high-impedance; | |
1476 | }; | |
1477 | }; | |
22b35776 SW |
1478 | |
1479 | regulators { | |
1480 | vsup-sd2-supply = <&vdd_5v0_sys>; | |
1481 | vsup-sd3-supply = <&vdd_5v0_sys>; | |
1482 | vsup-sd4-supply = <&vdd_5v0_sys>; | |
1483 | vsup-sd5-supply = <&vdd_5v0_sys>; | |
1484 | vin-ldo0-supply = <&vdd_1v35_lp0>; | |
1485 | vin-ldo1-6-supply = <&vdd_3v3_run>; | |
1486 | vin-ldo2-5-7-supply = <&vddio_1v8>; | |
1487 | vin-ldo3-4-supply = <&vdd_3v3_sys>; | |
1488 | vin-ldo9-10-supply = <&vdd_5v0_sys>; | |
1489 | vin-ldo11-supply = <&vdd_3v3_run>; | |
1490 | ||
1491 | sd0 { | |
1492 | regulator-name = "+VDD_CPU_AP"; | |
1493 | regulator-min-microvolt = <700000>; | |
1494 | regulator-max-microvolt = <1400000>; | |
1495 | regulator-min-microamp = <3500000>; | |
1496 | regulator-max-microamp = <3500000>; | |
1497 | regulator-always-on; | |
1498 | regulator-boot-on; | |
ee913f7a | 1499 | ams,ext-control = <2>; |
22b35776 SW |
1500 | }; |
1501 | ||
1502 | sd1 { | |
1503 | regulator-name = "+VDD_CORE"; | |
1504 | regulator-min-microvolt = <700000>; | |
1505 | regulator-max-microvolt = <1350000>; | |
1506 | regulator-min-microamp = <2500000>; | |
1507 | regulator-max-microamp = <2500000>; | |
1508 | regulator-always-on; | |
1509 | regulator-boot-on; | |
ee913f7a | 1510 | ams,ext-control = <1>; |
22b35776 SW |
1511 | }; |
1512 | ||
1513 | vdd_1v35_lp0: sd2 { | |
1514 | regulator-name = "+1.35V_LP0(sd2)"; | |
1515 | regulator-min-microvolt = <1350000>; | |
1516 | regulator-max-microvolt = <1350000>; | |
1517 | regulator-always-on; | |
1518 | regulator-boot-on; | |
1519 | }; | |
1520 | ||
1521 | sd3 { | |
1522 | regulator-name = "+1.35V_LP0(sd3)"; | |
1523 | regulator-min-microvolt = <1350000>; | |
1524 | regulator-max-microvolt = <1350000>; | |
1525 | regulator-always-on; | |
1526 | regulator-boot-on; | |
1527 | }; | |
1528 | ||
6054dd39 | 1529 | vdd_1v05_run: sd4 { |
22b35776 SW |
1530 | regulator-name = "+1.05V_RUN"; |
1531 | regulator-min-microvolt = <1050000>; | |
1532 | regulator-max-microvolt = <1050000>; | |
1533 | }; | |
1534 | ||
1535 | vddio_1v8: sd5 { | |
1536 | regulator-name = "+1.8V_VDDIO"; | |
1537 | regulator-min-microvolt = <1800000>; | |
1538 | regulator-max-microvolt = <1800000>; | |
1539 | regulator-boot-on; | |
1540 | regulator-always-on; | |
1541 | }; | |
1542 | ||
1543 | sd6 { | |
1544 | regulator-name = "+VDD_GPU_AP"; | |
1545 | regulator-min-microvolt = <650000>; | |
1546 | regulator-max-microvolt = <1200000>; | |
1547 | regulator-min-microamp = <3500000>; | |
1548 | regulator-max-microamp = <3500000>; | |
1549 | regulator-boot-on; | |
1550 | regulator-always-on; | |
1551 | }; | |
1552 | ||
1553 | ldo0 { | |
1554 | regulator-name = "+1.05V_RUN_AVDD"; | |
1555 | regulator-min-microvolt = <1050000>; | |
1556 | regulator-max-microvolt = <1050000>; | |
1557 | regulator-boot-on; | |
1558 | regulator-always-on; | |
ee913f7a | 1559 | ams,ext-control = <1>; |
22b35776 SW |
1560 | }; |
1561 | ||
1562 | ldo1 { | |
1563 | regulator-name = "+1.8V_RUN_CAM"; | |
1564 | regulator-min-microvolt = <1800000>; | |
1565 | regulator-max-microvolt = <1800000>; | |
1566 | }; | |
1567 | ||
1568 | ldo2 { | |
1569 | regulator-name = "+1.2V_GEN_AVDD"; | |
1570 | regulator-min-microvolt = <1200000>; | |
1571 | regulator-max-microvolt = <1200000>; | |
1572 | regulator-boot-on; | |
1573 | regulator-always-on; | |
1574 | }; | |
1575 | ||
1576 | ldo3 { | |
1577 | regulator-name = "+1.05V_LP0_VDD_RTC"; | |
1578 | regulator-min-microvolt = <1000000>; | |
1579 | regulator-max-microvolt = <1000000>; | |
1580 | regulator-boot-on; | |
1581 | regulator-always-on; | |
1582 | ams,enable-tracking; | |
1583 | }; | |
1584 | ||
1585 | ldo4 { | |
1586 | regulator-name = "+2.8V_RUN_CAM"; | |
1587 | regulator-min-microvolt = <2800000>; | |
1588 | regulator-max-microvolt = <2800000>; | |
1589 | }; | |
1590 | ||
1591 | ldo5 { | |
1592 | regulator-name = "+1.2V_RUN_CAM_FRONT"; | |
1593 | regulator-min-microvolt = <1200000>; | |
1594 | regulator-max-microvolt = <1200000>; | |
1595 | }; | |
1596 | ||
1597 | vddio_sdmmc3: ldo6 { | |
1598 | regulator-name = "+VDDIO_SDMMC3"; | |
1599 | regulator-min-microvolt = <1800000>; | |
1600 | regulator-max-microvolt = <3300000>; | |
1601 | }; | |
1602 | ||
1603 | ldo7 { | |
1604 | regulator-name = "+1.05V_RUN_CAM_REAR"; | |
1605 | regulator-min-microvolt = <1050000>; | |
1606 | regulator-max-microvolt = <1050000>; | |
1607 | }; | |
1608 | ||
1609 | ldo9 { | |
1610 | regulator-name = "+3.3V_RUN_TOUCH"; | |
1611 | regulator-min-microvolt = <2800000>; | |
1612 | regulator-max-microvolt = <2800000>; | |
1613 | }; | |
1614 | ||
1615 | ldo10 { | |
1616 | regulator-name = "+2.8V_RUN_CAM_AF"; | |
1617 | regulator-min-microvolt = <2800000>; | |
1618 | regulator-max-microvolt = <2800000>; | |
1619 | }; | |
1620 | ||
1621 | ldo11 { | |
1622 | regulator-name = "+1.8V_RUN_VPP_FUSE"; | |
1623 | regulator-min-microvolt = <1800000>; | |
1624 | regulator-max-microvolt = <1800000>; | |
1625 | }; | |
1626 | }; | |
15e524a4 SW |
1627 | }; |
1628 | }; | |
1629 | ||
1630 | /* Expansion TS_SPI_* */ | |
1631 | spi@0,7000d400 { | |
1632 | status = "okay"; | |
1633 | }; | |
1634 | ||
1635 | /* Internal SPI */ | |
1636 | spi@0,7000da00 { | |
1637 | status = "okay"; | |
1638 | spi-max-frequency = <25000000>; | |
1639 | spi-flash@0 { | |
1640 | compatible = "winbond,w25q32dw"; | |
1641 | reg = <0>; | |
1642 | spi-max-frequency = <20000000>; | |
1643 | }; | |
1644 | }; | |
1645 | ||
1646 | pmc@0,7000e400 { | |
1647 | nvidia,invert-interrupt; | |
1648 | nvidia,suspend-mode = <1>; | |
1649 | nvidia,cpu-pwr-good-time = <500>; | |
1650 | nvidia,cpu-pwr-off-time = <300>; | |
1651 | nvidia,core-pwr-good-time = <641 3845>; | |
1652 | nvidia,core-pwr-off-time = <61036>; | |
1653 | nvidia,core-power-req-active-high; | |
1654 | nvidia,sys-clock-req-active-high; | |
1655 | }; | |
1656 | ||
1b3ce99f MP |
1657 | /* Serial ATA */ |
1658 | sata@0,70020000 { | |
1659 | status = "okay"; | |
1660 | ||
1661 | hvdd-supply = <&vdd_3v3_lp0>; | |
1662 | vddio-supply = <&vdd_1v05_run>; | |
1663 | avdd-supply = <&vdd_1v05_run>; | |
1664 | ||
1665 | target-5v-supply = <&vdd_5v0_sata>; | |
1666 | target-12v-supply = <&vdd_12v0_sata>; | |
1667 | }; | |
1668 | ||
62b8db08 TR |
1669 | padctl@0,7009f000 { |
1670 | pinctrl-0 = <&padctl_default>; | |
1671 | pinctrl-names = "default"; | |
1672 | ||
1673 | padctl_default: pinmux { | |
1674 | usb3 { | |
1675 | nvidia,lanes = "pcie-0", "pcie-1"; | |
1676 | nvidia,function = "usb3"; | |
1677 | nvidia,iddq = <0>; | |
1678 | }; | |
1679 | ||
1680 | pcie { | |
1681 | nvidia,lanes = "pcie-2", "pcie-3", | |
1682 | "pcie-4"; | |
1683 | nvidia,function = "pcie"; | |
1684 | nvidia,iddq = <0>; | |
1685 | }; | |
1686 | ||
1687 | sata { | |
1688 | nvidia,lanes = "sata-0"; | |
1689 | nvidia,function = "sata"; | |
1690 | nvidia,iddq = <0>; | |
1691 | }; | |
1692 | }; | |
1693 | }; | |
1694 | ||
15e524a4 SW |
1695 | /* SD card */ |
1696 | sdhci@0,700b0400 { | |
1697 | status = "okay"; | |
1698 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; | |
1699 | power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; | |
215f21c9 | 1700 | wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; |
15e524a4 | 1701 | bus-width = <4>; |
9260764c | 1702 | vqmmc-supply = <&vddio_sdmmc3>; |
15e524a4 SW |
1703 | }; |
1704 | ||
1705 | /* eMMC */ | |
1706 | sdhci@0,700b0600 { | |
1707 | status = "okay"; | |
1708 | bus-width = <8>; | |
33f34f0c | 1709 | non-removable; |
15e524a4 SW |
1710 | }; |
1711 | ||
1712 | ahub@0,70300000 { | |
1713 | i2s@0,70301100 { | |
1714 | status = "okay"; | |
1715 | }; | |
1716 | }; | |
1717 | ||
1718 | /* mini-PCIe USB */ | |
1719 | usb@0,7d004000 { | |
1720 | status = "okay"; | |
1721 | }; | |
1722 | ||
1723 | usb-phy@0,7d004000 { | |
1724 | status = "okay"; | |
1725 | }; | |
1726 | ||
1727 | /* USB A connector */ | |
1728 | usb@0,7d008000 { | |
1729 | status = "okay"; | |
1730 | }; | |
1731 | ||
1732 | usb-phy@0,7d008000 { | |
1733 | status = "okay"; | |
1734 | vbus-supply = <&vdd_usb3_vbus>; | |
1735 | }; | |
1736 | ||
1737 | clocks { | |
1738 | compatible = "simple-bus"; | |
1739 | #address-cells = <1>; | |
1740 | #size-cells = <0>; | |
1741 | ||
1742 | clk32k_in: clock@0 { | |
1743 | compatible = "fixed-clock"; | |
1744 | reg = <0>; | |
1745 | #clock-cells = <0>; | |
1746 | clock-frequency = <32768>; | |
1747 | }; | |
1748 | }; | |
1749 | ||
1750 | gpio-keys { | |
1751 | compatible = "gpio-keys"; | |
1752 | ||
1753 | power { | |
1754 | label = "Power"; | |
1755 | gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; | |
1756 | linux,code = <KEY_POWER>; | |
1757 | debounce-interval = <10>; | |
1758 | gpio-key,wakeup; | |
1759 | }; | |
1760 | }; | |
1761 | ||
1762 | regulators { | |
1763 | compatible = "simple-bus"; | |
1764 | #address-cells = <1>; | |
1765 | #size-cells = <0>; | |
1766 | ||
22b35776 SW |
1767 | vdd_mux: regulator@0 { |
1768 | compatible = "regulator-fixed"; | |
1769 | reg = <0>; | |
1770 | regulator-name = "+VDD_MUX"; | |
1771 | regulator-min-microvolt = <12000000>; | |
1772 | regulator-max-microvolt = <12000000>; | |
1773 | regulator-always-on; | |
1774 | regulator-boot-on; | |
1775 | }; | |
1776 | ||
1777 | vdd_5v0_sys: regulator@1 { | |
1778 | compatible = "regulator-fixed"; | |
1779 | reg = <1>; | |
1780 | regulator-name = "+5V_SYS"; | |
1781 | regulator-min-microvolt = <5000000>; | |
1782 | regulator-max-microvolt = <5000000>; | |
1783 | regulator-always-on; | |
1784 | regulator-boot-on; | |
1785 | vin-supply = <&vdd_mux>; | |
1786 | }; | |
1787 | ||
1788 | vdd_3v3_sys: regulator@2 { | |
1789 | compatible = "regulator-fixed"; | |
1790 | reg = <2>; | |
1791 | regulator-name = "+3.3V_SYS"; | |
1792 | regulator-min-microvolt = <3300000>; | |
1793 | regulator-max-microvolt = <3300000>; | |
1794 | regulator-always-on; | |
1795 | regulator-boot-on; | |
1796 | vin-supply = <&vdd_mux>; | |
1797 | }; | |
1798 | ||
1799 | vdd_3v3_run: regulator@3 { | |
1800 | compatible = "regulator-fixed"; | |
1801 | reg = <3>; | |
1802 | regulator-name = "+3.3V_RUN"; | |
1803 | regulator-min-microvolt = <3300000>; | |
1804 | regulator-max-microvolt = <3300000>; | |
1805 | regulator-always-on; | |
1806 | regulator-boot-on; | |
1807 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; | |
1808 | enable-active-high; | |
1809 | vin-supply = <&vdd_3v3_sys>; | |
1810 | }; | |
1811 | ||
1812 | vdd_3v3_hdmi: regulator@4 { | |
1813 | compatible = "regulator-fixed"; | |
1814 | reg = <4>; | |
1815 | regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; | |
1816 | regulator-min-microvolt = <3300000>; | |
1817 | regulator-max-microvolt = <3300000>; | |
1818 | vin-supply = <&vdd_3v3_run>; | |
1819 | }; | |
1820 | ||
1821 | vdd_usb1_vbus: regulator@7 { | |
1822 | compatible = "regulator-fixed"; | |
1823 | reg = <7>; | |
1824 | regulator-name = "+USB0_VBUS_SW"; | |
1825 | regulator-min-microvolt = <5000000>; | |
1826 | regulator-max-microvolt = <5000000>; | |
1827 | gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; | |
1828 | enable-active-high; | |
1829 | gpio-open-drain; | |
1830 | vin-supply = <&vdd_5v0_sys>; | |
1831 | }; | |
1832 | ||
15e524a4 SW |
1833 | vdd_usb3_vbus: regulator@8 { |
1834 | compatible = "regulator-fixed"; | |
1835 | reg = <8>; | |
1836 | regulator-name = "+5V_USB_HS"; | |
1837 | regulator-min-microvolt = <5000000>; | |
1838 | regulator-max-microvolt = <5000000>; | |
1839 | gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; | |
1840 | enable-active-high; | |
1841 | gpio-open-drain; | |
22b35776 SW |
1842 | vin-supply = <&vdd_5v0_sys>; |
1843 | }; | |
1844 | ||
1845 | vdd_3v3_lp0: regulator@10 { | |
1846 | compatible = "regulator-fixed"; | |
1847 | reg = <10>; | |
1848 | regulator-name = "+3.3V_LP0"; | |
1849 | regulator-min-microvolt = <3300000>; | |
1850 | regulator-max-microvolt = <3300000>; | |
1851 | regulator-always-on; | |
1852 | regulator-boot-on; | |
1853 | gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; | |
1854 | enable-active-high; | |
1855 | vin-supply = <&vdd_3v3_sys>; | |
15e524a4 | 1856 | }; |
6054dd39 TR |
1857 | |
1858 | vdd_hdmi_pll: regulator@11 { | |
1859 | compatible = "regulator-fixed"; | |
1860 | reg = <11>; | |
1861 | regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; | |
1862 | regulator-min-microvolt = <1050000>; | |
1863 | regulator-max-microvolt = <1050000>; | |
1864 | gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; | |
1865 | vin-supply = <&vdd_1v05_run>; | |
1866 | }; | |
1867 | ||
1868 | vdd_5v0_hdmi: regulator@12 { | |
1869 | compatible = "regulator-fixed"; | |
1870 | reg = <12>; | |
1871 | regulator-name = "+5V_HDMI_CON"; | |
1872 | regulator-min-microvolt = <5000000>; | |
1873 | regulator-max-microvolt = <5000000>; | |
1874 | gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; | |
1875 | enable-active-high; | |
1876 | vin-supply = <&vdd_5v0_sys>; | |
1877 | }; | |
1b3ce99f MP |
1878 | |
1879 | /* Molex power connector */ | |
1880 | vdd_5v0_sata: regulator@13 { | |
1881 | compatible = "regulator-fixed"; | |
1882 | reg = <13>; | |
1883 | regulator-name = "+5V_SATA"; | |
1884 | regulator-min-microvolt = <5000000>; | |
1885 | regulator-max-microvolt = <5000000>; | |
1886 | gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; | |
1887 | enable-active-high; | |
1888 | vin-supply = <&vdd_5v0_sys>; | |
1889 | }; | |
1890 | ||
1891 | vdd_12v0_sata: regulator@14 { | |
1892 | compatible = "regulator-fixed"; | |
1893 | reg = <14>; | |
1894 | regulator-name = "+12V_SATA"; | |
1895 | regulator-min-microvolt = <12000000>; | |
1896 | regulator-max-microvolt = <12000000>; | |
1897 | gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; | |
1898 | enable-active-high; | |
1899 | vin-supply = <&vdd_mux>; | |
1900 | }; | |
15e524a4 SW |
1901 | }; |
1902 | ||
1903 | sound { | |
1904 | compatible = "nvidia,tegra-audio-rt5640-jetson-tk1", | |
1905 | "nvidia,tegra-audio-rt5640"; | |
1906 | nvidia,model = "NVIDIA Tegra Jetson TK1"; | |
1907 | ||
1908 | nvidia,audio-routing = | |
1909 | "Headphones", "HPOR", | |
1910 | "Headphones", "HPOL", | |
1911 | "Mic Jack", "MICBIAS1", | |
1912 | "IN2P", "Mic Jack"; | |
1913 | ||
1914 | nvidia,i2s-controller = <&tegra_i2s1>; | |
98de744e | 1915 | nvidia,audio-codec = <&rt5639>; |
15e524a4 SW |
1916 | |
1917 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; | |
1918 | ||
1919 | clocks = <&tegra_car TEGRA124_CLK_PLL_A>, | |
1920 | <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, | |
1921 | <&tegra_car TEGRA124_CLK_EXTERN1>; | |
1922 | clock-names = "pll_a", "pll_a_out0", "mclk"; | |
1923 | }; | |
1924 | }; |