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Commit | Line | Data |
---|---|---|
eb481f9a DR |
1 | /dts-v1/; |
2 | ||
53d02858 | 3 | #include "tegra124-nyan.dtsi" |
eb481f9a DR |
4 | |
5 | / { | |
6 | model = "Acer Chromebook 13 CB5-311"; | |
7 | compatible = "google,nyan-big", "nvidia,tegra124"; | |
8 | ||
53d02858 TV |
9 | panel: panel { |
10 | compatible = "auo,b133xtn01"; | |
eb481f9a | 11 | |
53d02858 TV |
12 | backlight = <&backlight>; |
13 | ddc-i2c-bus = <&dpaux>; | |
eb481f9a DR |
14 | }; |
15 | ||
53d02858 TV |
16 | sdhci@0,700b0400 { /* SD Card on this bus */ |
17 | wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; | |
18 | }; | |
eb481f9a | 19 | |
53d02858 TV |
20 | sound { |
21 | compatible = "nvidia,tegra-audio-max98090-nyan-big", | |
22 | "nvidia,tegra-audio-max98090-nyan", | |
23 | "nvidia,tegra-audio-max98090"; | |
24 | nvidia,model = "GoogleNyanBig"; | |
eb481f9a DR |
25 | }; |
26 | ||
27 | pinmux@0,70000868 { | |
28 | pinctrl-names = "default"; | |
29 | pinctrl-0 = <&pinmux_default>; | |
30 | ||
31 | pinmux_default: common { | |
33b274ba TV |
32 | clk_32k_out_pa0 { |
33 | nvidia,pins = "clk_32k_out_pa0"; | |
eb481f9a DR |
34 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
35 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
eb481f9a | 36 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
eb481f9a | 37 | }; |
33b274ba TV |
38 | uart3_cts_n_pa1 { |
39 | nvidia,pins = "uart3_cts_n_pa1"; | |
40 | nvidia,function = "gmi"; | |
41 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
42 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
eb481f9a | 43 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
eb481f9a | 44 | }; |
33b274ba TV |
45 | dap2_fs_pa2 { |
46 | nvidia,pins = "dap2_fs_pa2"; | |
47 | nvidia,function = "i2s1"; | |
eb481f9a DR |
48 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
49 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
33b274ba | 50 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
eb481f9a | 51 | }; |
33b274ba TV |
52 | dap2_sclk_pa3 { |
53 | nvidia,pins = "dap2_sclk_pa3"; | |
54 | nvidia,function = "i2s1"; | |
eb481f9a DR |
55 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
56 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
eb481f9a | 57 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
eb481f9a | 58 | }; |
33b274ba TV |
59 | dap2_din_pa4 { |
60 | nvidia,pins = "dap2_din_pa4"; | |
61 | nvidia,function = "i2s1"; | |
eb481f9a DR |
62 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
63 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
eb481f9a | 64 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
eb481f9a | 65 | }; |
33b274ba TV |
66 | dap2_dout_pa5 { |
67 | nvidia,pins = "dap2_dout_pa5"; | |
68 | nvidia,function = "i2s1"; | |
eb481f9a DR |
69 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
70 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
eb481f9a | 71 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
eb481f9a | 72 | }; |
33b274ba TV |
73 | sdmmc3_clk_pa6 { |
74 | nvidia,pins = "sdmmc3_clk_pa6"; | |
75 | nvidia,function = "sdmmc3"; | |
eb481f9a DR |
76 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
77 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
33b274ba | 78 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
eb481f9a | 79 | }; |
33b274ba TV |
80 | sdmmc3_cmd_pa7 { |
81 | nvidia,pins = "sdmmc3_cmd_pa7"; | |
82 | nvidia,function = "sdmmc3"; | |
eb481f9a DR |
83 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
84 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
85 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
86 | }; | |
33b274ba TV |
87 | pb0 { |
88 | nvidia,pins = "pb0"; | |
89 | nvidia,function = "rsvd2"; | |
90 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
91 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
eb481f9a | 92 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
eb481f9a | 93 | }; |
33b274ba TV |
94 | pb1 { |
95 | nvidia,pins = "pb1"; | |
96 | nvidia,function = "rsvd2"; | |
97 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
98 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
99 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
eb481f9a | 100 | }; |
33b274ba TV |
101 | sdmmc3_dat3_pb4 { |
102 | nvidia,pins = "sdmmc3_dat3_pb4"; | |
eb481f9a | 103 | nvidia,function = "sdmmc3"; |
33b274ba | 104 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
eb481f9a | 105 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
33b274ba | 106 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
eb481f9a | 107 | }; |
33b274ba TV |
108 | sdmmc3_dat2_pb5 { |
109 | nvidia,pins = "sdmmc3_dat2_pb5"; | |
eb481f9a | 110 | nvidia,function = "sdmmc3"; |
eb481f9a DR |
111 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
112 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
eb481f9a | 113 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
eb481f9a | 114 | }; |
33b274ba TV |
115 | sdmmc3_dat1_pb6 { |
116 | nvidia,pins = "sdmmc3_dat1_pb6"; | |
117 | nvidia,function = "sdmmc3"; | |
eb481f9a DR |
118 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
119 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
eb481f9a | 120 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
eb481f9a | 121 | }; |
33b274ba TV |
122 | sdmmc3_dat0_pb7 { |
123 | nvidia,pins = "sdmmc3_dat0_pb7"; | |
124 | nvidia,function = "sdmmc3"; | |
eb481f9a DR |
125 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
126 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
eb481f9a | 127 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
eb481f9a | 128 | }; |
33b274ba TV |
129 | uart3_rts_n_pc0 { |
130 | nvidia,pins = "uart3_rts_n_pc0"; | |
131 | nvidia,function = "gmi"; | |
132 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
133 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
eb481f9a | 134 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
eb481f9a | 135 | }; |
33b274ba TV |
136 | uart2_txd_pc2 { |
137 | nvidia,pins = "uart2_txd_pc2"; | |
138 | nvidia,function = "irda"; | |
139 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
140 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
eb481f9a | 141 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
eb481f9a | 142 | }; |
33b274ba TV |
143 | uart2_rxd_pc3 { |
144 | nvidia,pins = "uart2_rxd_pc3"; | |
145 | nvidia,function = "irda"; | |
146 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
147 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
eb481f9a | 148 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
eb481f9a | 149 | }; |
33b274ba TV |
150 | gen1_i2c_scl_pc4 { |
151 | nvidia,pins = "gen1_i2c_scl_pc4"; | |
152 | nvidia,function = "i2c1"; | |
eb481f9a DR |
153 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
154 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
33b274ba TV |
155 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
156 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
eb481f9a DR |
157 | }; |
158 | gen1_i2c_sda_pc5 { | |
33b274ba | 159 | nvidia,pins = "gen1_i2c_sda_pc5"; |
eb481f9a | 160 | nvidia,function = "i2c1"; |
eb481f9a DR |
161 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
162 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
33b274ba | 163 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
eb481f9a DR |
164 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
165 | }; | |
33b274ba TV |
166 | pc7 { |
167 | nvidia,pins = "pc7"; | |
eb481f9a DR |
168 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
169 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
eb481f9a | 170 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
33b274ba TV |
171 | }; |
172 | pg0 { | |
173 | nvidia,pins = "pg0"; | |
174 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
eb481f9a | 175 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
33b274ba | 176 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
eb481f9a | 177 | }; |
33b274ba TV |
178 | pg1 { |
179 | nvidia,pins = "pg1"; | |
180 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
181 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
eb481f9a | 182 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
33b274ba TV |
183 | }; |
184 | pg2 { | |
185 | nvidia,pins = "pg2"; | |
eb481f9a DR |
186 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
187 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
33b274ba | 188 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
eb481f9a | 189 | }; |
33b274ba TV |
190 | pg3 { |
191 | nvidia,pins = "pg3"; | |
192 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
eb481f9a DR |
193 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
194 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
195 | }; | |
33b274ba TV |
196 | pg4 { |
197 | nvidia,pins = "pg4"; | |
198 | nvidia,function = "spi4"; | |
eb481f9a DR |
199 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
200 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
201 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
202 | }; | |
33b274ba TV |
203 | pg5 { |
204 | nvidia,pins = "pg5"; | |
205 | nvidia,function = "spi4"; | |
eb481f9a DR |
206 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
207 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
33b274ba | 208 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
eb481f9a | 209 | }; |
33b274ba TV |
210 | pg6 { |
211 | nvidia,pins = "pg6"; | |
212 | nvidia,function = "spi4"; | |
213 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
214 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
215 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
216 | }; | |
217 | pg7 { | |
218 | nvidia,pins = "pg7"; | |
219 | nvidia,function = "spi4"; | |
eb481f9a DR |
220 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
221 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
222 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
223 | }; | |
33b274ba TV |
224 | ph0 { |
225 | nvidia,pins = "ph0"; | |
eb481f9a DR |
226 | nvidia,function = "gmi"; |
227 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
33b274ba | 228 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
eb481f9a DR |
229 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
230 | }; | |
33b274ba TV |
231 | ph1 { |
232 | nvidia,pins = "ph1"; | |
233 | nvidia,function = "pwm1"; | |
eb481f9a DR |
234 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
235 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
33b274ba | 236 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
eb481f9a | 237 | }; |
33b274ba TV |
238 | ph2 { |
239 | nvidia,pins = "ph2"; | |
eb481f9a DR |
240 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
241 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
242 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
243 | }; | |
33b274ba TV |
244 | ph3 { |
245 | nvidia,pins = "ph3"; | |
eb481f9a | 246 | nvidia,function = "gmi"; |
33b274ba TV |
247 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
248 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
249 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
250 | }; | |
251 | ph4 { | |
252 | nvidia,pins = "ph4"; | |
eb481f9a DR |
253 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
254 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
255 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
256 | }; | |
33b274ba TV |
257 | ph5 { |
258 | nvidia,pins = "ph5"; | |
259 | nvidia,function = "rsvd2"; | |
260 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
261 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
eb481f9a DR |
262 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
263 | }; | |
33b274ba TV |
264 | ph6 { |
265 | nvidia,pins = "ph6"; | |
266 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
eb481f9a | 267 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
33b274ba | 268 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
eb481f9a DR |
269 | }; |
270 | ph7 { | |
271 | nvidia,pins = "ph7"; | |
eb481f9a DR |
272 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
273 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
33b274ba | 274 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
eb481f9a | 275 | }; |
33b274ba TV |
276 | pi0 { |
277 | nvidia,pins = "pi0"; | |
278 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
eb481f9a DR |
279 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
280 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
281 | }; | |
33b274ba TV |
282 | pi1 { |
283 | nvidia,pins = "pi1"; | |
284 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
eb481f9a DR |
285 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
286 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
287 | }; | |
33b274ba TV |
288 | pi2 { |
289 | nvidia,pins = "pi2"; | |
eb481f9a | 290 | nvidia,function = "rsvd4"; |
33b274ba TV |
291 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
292 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
293 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
294 | }; | |
295 | pi3 { | |
296 | nvidia,pins = "pi3"; | |
297 | nvidia,function = "spi4"; | |
eb481f9a DR |
298 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
299 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
300 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
301 | }; | |
33b274ba TV |
302 | pi4 { |
303 | nvidia,pins = "pi4"; | |
eb481f9a | 304 | nvidia,function = "gmi"; |
33b274ba TV |
305 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
306 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
307 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
308 | }; | |
309 | pi5 { | |
310 | nvidia,pins = "pi5"; | |
eb481f9a DR |
311 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
312 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
33b274ba | 313 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
eb481f9a | 314 | }; |
33b274ba | 315 | pi6 { |
eb481f9a | 316 | nvidia,pins = "pi6"; |
eb481f9a DR |
317 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
318 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
319 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
320 | }; | |
33b274ba TV |
321 | pi7 { |
322 | nvidia,pins = "pi7"; | |
eb481f9a DR |
323 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
324 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
33b274ba | 325 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
eb481f9a | 326 | }; |
33b274ba TV |
327 | pj0 { |
328 | nvidia,pins = "pj0"; | |
329 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
330 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
331 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
332 | }; | |
333 | pj2 { | |
334 | nvidia,pins = "pj2"; | |
335 | nvidia,function = "rsvd1"; | |
336 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
337 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
eb481f9a DR |
338 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
339 | }; | |
33b274ba TV |
340 | uart2_cts_n_pj5 { |
341 | nvidia,pins = "uart2_cts_n_pj5"; | |
342 | nvidia,function = "gmi"; | |
343 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
344 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
345 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
346 | }; | |
347 | uart2_rts_n_pj6 { | |
348 | nvidia,pins = "uart2_rts_n_pj6"; | |
349 | nvidia,function = "gmi"; | |
350 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
351 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
352 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
353 | }; | |
354 | pj7 { | |
355 | nvidia,pins = "pj7"; | |
356 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
357 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
358 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
359 | }; | |
360 | pk0 { | |
361 | nvidia,pins = "pk0"; | |
362 | nvidia,function = "rsvd1"; | |
eb481f9a | 363 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
33b274ba TV |
364 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
365 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
366 | }; | |
367 | pk1 { | |
368 | nvidia,pins = "pk1"; | |
369 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
eb481f9a DR |
370 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
371 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
372 | }; | |
33b274ba TV |
373 | pk2 { |
374 | nvidia,pins = "pk2"; | |
375 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
376 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
377 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
378 | }; | |
379 | pk3 { | |
380 | nvidia,pins = "pk3"; | |
eb481f9a | 381 | nvidia,function = "gmi"; |
33b274ba TV |
382 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
383 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
384 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
385 | }; | |
386 | pk4 { | |
387 | nvidia,pins = "pk4"; | |
eb481f9a DR |
388 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
389 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
390 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
391 | }; | |
33b274ba TV |
392 | spdif_out_pk5 { |
393 | nvidia,pins = "spdif_out_pk5"; | |
394 | nvidia,function = "rsvd2"; | |
395 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
396 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
397 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
398 | }; | |
399 | spdif_in_pk6 { | |
400 | nvidia,pins = "spdif_in_pk6"; | |
401 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
402 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
403 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
404 | }; | |
405 | pk7 { | |
406 | nvidia,pins = "pk7"; | |
eb481f9a DR |
407 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
408 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
409 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
410 | }; | |
33b274ba TV |
411 | dap1_fs_pn0 { |
412 | nvidia,pins = "dap1_fs_pn0"; | |
413 | nvidia,function = "rsvd4"; | |
414 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
415 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
416 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
417 | }; | |
418 | dap1_din_pn1 { | |
419 | nvidia,pins = "dap1_din_pn1"; | |
420 | nvidia,function = "rsvd4"; | |
421 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
422 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
423 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
424 | }; | |
425 | dap1_dout_pn2 { | |
426 | nvidia,pins = "dap1_dout_pn2"; | |
427 | nvidia,function = "i2s0"; | |
428 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
429 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
430 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
431 | }; | |
432 | dap1_sclk_pn3 { | |
433 | nvidia,pins = "dap1_sclk_pn3"; | |
434 | nvidia,function = "rsvd4"; | |
435 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
436 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
437 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
438 | }; | |
439 | usb_vbus_en0_pn4 { | |
440 | nvidia,pins = "usb_vbus_en0_pn4"; | |
441 | nvidia,function = "usb"; | |
442 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
443 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
444 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
445 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
446 | }; | |
447 | usb_vbus_en1_pn5 { | |
448 | nvidia,pins = "usb_vbus_en1_pn5"; | |
449 | nvidia,function = "usb"; | |
450 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
451 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
452 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
453 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
454 | }; | |
455 | hdmi_int_pn7 { | |
456 | nvidia,pins = "hdmi_int_pn7"; | |
457 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
458 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
459 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
460 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
461 | }; | |
462 | ulpi_data7_po0 { | |
463 | nvidia,pins = "ulpi_data7_po0"; | |
464 | nvidia,function = "ulpi"; | |
465 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
466 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
467 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
468 | }; | |
469 | ulpi_data0_po1 { | |
470 | nvidia,pins = "ulpi_data0_po1"; | |
471 | nvidia,function = "ulpi"; | |
472 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
473 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
474 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
475 | }; | |
476 | ulpi_data1_po2 { | |
477 | nvidia,pins = "ulpi_data1_po2"; | |
478 | nvidia,function = "ulpi"; | |
479 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
480 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
481 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
482 | }; | |
483 | ulpi_data2_po3 { | |
484 | nvidia,pins = "ulpi_data2_po3"; | |
485 | nvidia,function = "ulpi"; | |
486 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
487 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
488 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
489 | }; | |
490 | ulpi_data3_po4 { | |
491 | nvidia,pins = "ulpi_data3_po4"; | |
492 | nvidia,function = "ulpi"; | |
493 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
494 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
495 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
496 | }; | |
497 | ulpi_data4_po5 { | |
498 | nvidia,pins = "ulpi_data4_po5"; | |
499 | nvidia,function = "ulpi"; | |
500 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
501 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
502 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
503 | }; | |
504 | ulpi_data5_po6 { | |
505 | nvidia,pins = "ulpi_data5_po6"; | |
506 | nvidia,function = "ulpi"; | |
507 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
508 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
509 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
510 | }; | |
511 | ulpi_data6_po7 { | |
512 | nvidia,pins = "ulpi_data6_po7"; | |
513 | nvidia,function = "ulpi"; | |
514 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
515 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
516 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
517 | }; | |
518 | dap3_fs_pp0 { | |
519 | nvidia,pins = "dap3_fs_pp0"; | |
520 | nvidia,function = "i2s2"; | |
521 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
522 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
523 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
524 | }; | |
525 | dap3_din_pp1 { | |
526 | nvidia,pins = "dap3_din_pp1"; | |
527 | nvidia,function = "i2s2"; | |
528 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
529 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
530 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
531 | }; | |
532 | dap3_dout_pp2 { | |
533 | nvidia,pins = "dap3_dout_pp2"; | |
534 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
535 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
536 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
537 | }; | |
538 | dap3_sclk_pp3 { | |
539 | nvidia,pins = "dap3_sclk_pp3"; | |
540 | nvidia,function = "rsvd3"; | |
541 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
542 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
543 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
544 | }; | |
545 | dap4_fs_pp4 { | |
546 | nvidia,pins = "dap4_fs_pp4"; | |
547 | nvidia,function = "rsvd4"; | |
548 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
549 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
550 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
551 | }; | |
552 | dap4_din_pp5 { | |
553 | nvidia,pins = "dap4_din_pp5"; | |
554 | nvidia,function = "rsvd3"; | |
555 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
556 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
557 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
558 | }; | |
559 | dap4_dout_pp6 { | |
560 | nvidia,pins = "dap4_dout_pp6"; | |
561 | nvidia,function = "rsvd4"; | |
562 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
563 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
564 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
565 | }; | |
566 | dap4_sclk_pp7 { | |
567 | nvidia,pins = "dap4_sclk_pp7"; | |
568 | nvidia,function = "rsvd3"; | |
569 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
570 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
571 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
572 | }; | |
573 | kb_col0_pq0 { | |
574 | nvidia,pins = "kb_col0_pq0"; | |
575 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
576 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
577 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
578 | }; | |
579 | kb_col1_pq1 { | |
580 | nvidia,pins = "kb_col1_pq1"; | |
eb481f9a | 581 | nvidia,function = "rsvd2"; |
33b274ba TV |
582 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
583 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
584 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
585 | }; | |
586 | kb_col2_pq2 { | |
587 | nvidia,pins = "kb_col2_pq2"; | |
588 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
589 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
590 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
591 | }; | |
592 | kb_col3_pq3 { | |
593 | nvidia,pins = "kb_col3_pq3"; | |
594 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
595 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
596 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
597 | }; | |
598 | kb_col4_pq4 { | |
599 | nvidia,pins = "kb_col4_pq4"; | |
600 | nvidia,function = "sdmmc3"; | |
eb481f9a DR |
601 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
602 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
603 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
604 | }; | |
33b274ba TV |
605 | kb_col5_pq5 { |
606 | nvidia,pins = "kb_col5_pq5"; | |
607 | nvidia,function = "rsvd2"; | |
608 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
609 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
610 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
611 | }; | |
612 | kb_col6_pq6 { | |
613 | nvidia,pins = "kb_col6_pq6"; | |
614 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
615 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
616 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
617 | }; | |
618 | kb_col7_pq7 { | |
619 | nvidia,pins = "kb_col7_pq7"; | |
620 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
621 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
622 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
623 | }; | |
624 | kb_row0_pr0 { | |
625 | nvidia,pins = "kb_row0_pr0"; | |
626 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
627 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
628 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
629 | }; | |
630 | kb_row1_pr1 { | |
631 | nvidia,pins = "kb_row1_pr1"; | |
632 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
633 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
634 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
635 | }; | |
636 | kb_row2_pr2 { | |
637 | nvidia,pins = "kb_row2_pr2"; | |
638 | nvidia,function = "rsvd2"; | |
639 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
640 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
641 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
642 | }; | |
643 | kb_row3_pr3 { | |
644 | nvidia,pins = "kb_row3_pr3"; | |
645 | nvidia,function = "kbc"; | |
646 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
647 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
648 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
649 | }; | |
650 | kb_row4_pr4 { | |
651 | nvidia,pins = "kb_row4_pr4"; | |
652 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
653 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
654 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
655 | }; | |
656 | kb_row5_pr5 { | |
657 | nvidia,pins = "kb_row5_pr5"; | |
658 | nvidia,function = "rsvd3"; | |
659 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
660 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
661 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
662 | }; | |
663 | kb_row6_pr6 { | |
664 | nvidia,pins = "kb_row6_pr6"; | |
665 | nvidia,function = "kbc"; | |
666 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
667 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
668 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
669 | }; | |
670 | kb_row7_pr7 { | |
671 | nvidia,pins = "kb_row7_pr7"; | |
672 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
673 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
674 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
675 | }; | |
676 | kb_row8_ps0 { | |
677 | nvidia,pins = "kb_row8_ps0"; | |
678 | nvidia,function = "rsvd2"; | |
679 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
680 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
681 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
682 | }; | |
683 | kb_row9_ps1 { | |
684 | nvidia,pins = "kb_row9_ps1"; | |
685 | nvidia,function = "uarta"; | |
686 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
687 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
688 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
689 | }; | |
690 | kb_row10_ps2 { | |
691 | nvidia,pins = "kb_row10_ps2"; | |
692 | nvidia,function = "uarta"; | |
693 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
694 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
695 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
696 | }; | |
697 | kb_row11_ps3 { | |
698 | nvidia,pins = "kb_row11_ps3"; | |
699 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
700 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
701 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
702 | }; | |
703 | kb_row12_ps4 { | |
704 | nvidia,pins = "kb_row12_ps4"; | |
705 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
706 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
707 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
708 | }; | |
709 | kb_row13_ps5 { | |
710 | nvidia,pins = "kb_row13_ps5"; | |
711 | nvidia,function = "rsvd2"; | |
712 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
713 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
714 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
715 | }; | |
716 | kb_row14_ps6 { | |
717 | nvidia,pins = "kb_row14_ps6"; | |
718 | nvidia,function = "rsvd2"; | |
719 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
720 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
721 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
722 | }; | |
723 | kb_row15_ps7 { | |
724 | nvidia,pins = "kb_row15_ps7"; | |
725 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
726 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
727 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
728 | }; | |
729 | kb_row16_pt0 { | |
730 | nvidia,pins = "kb_row16_pt0"; | |
731 | nvidia,function = "rsvd2"; | |
732 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
733 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
734 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
735 | }; | |
736 | kb_row17_pt1 { | |
737 | nvidia,pins = "kb_row17_pt1"; | |
738 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
739 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
740 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
741 | }; | |
742 | gen2_i2c_scl_pt5 { | |
743 | nvidia,pins = "gen2_i2c_scl_pt5"; | |
744 | nvidia,function = "i2c2"; | |
745 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
746 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
747 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
748 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
749 | }; | |
750 | gen2_i2c_sda_pt6 { | |
751 | nvidia,pins = "gen2_i2c_sda_pt6"; | |
752 | nvidia,function = "i2c2"; | |
753 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
754 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
755 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
756 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
757 | }; | |
758 | sdmmc4_cmd_pt7 { | |
759 | nvidia,pins = "sdmmc4_cmd_pt7"; | |
760 | nvidia,function = "sdmmc4"; | |
761 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
762 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
763 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
764 | }; | |
765 | pu0 { | |
766 | nvidia,pins = "pu0"; | |
767 | nvidia,function = "rsvd4"; | |
768 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
769 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
770 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
771 | }; | |
772 | pu1 { | |
773 | nvidia,pins = "pu1"; | |
774 | nvidia,function = "rsvd1"; | |
775 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
776 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
777 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
778 | }; | |
779 | pu2 { | |
780 | nvidia,pins = "pu2"; | |
781 | nvidia,function = "rsvd1"; | |
782 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
783 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
784 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
785 | }; | |
786 | pu3 { | |
787 | nvidia,pins = "pu3"; | |
788 | nvidia,function = "gmi"; | |
789 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
790 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
791 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
792 | }; | |
793 | pu4 { | |
794 | nvidia,pins = "pu4"; | |
795 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
796 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
797 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
798 | }; | |
799 | pu5 { | |
800 | nvidia,pins = "pu5"; | |
801 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
802 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
803 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
804 | }; | |
805 | pu6 { | |
806 | nvidia,pins = "pu6"; | |
807 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
808 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
809 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
810 | }; | |
811 | pv0 { | |
812 | nvidia,pins = "pv0"; | |
813 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
814 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
815 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
816 | }; | |
817 | pv1 { | |
818 | nvidia,pins = "pv1"; | |
819 | nvidia,function = "rsvd1"; | |
820 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
821 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
822 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
823 | }; | |
824 | sdmmc3_cd_n_pv2 { | |
825 | nvidia,pins = "sdmmc3_cd_n_pv2"; | |
826 | nvidia,function = "sdmmc3"; | |
827 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
828 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
829 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
830 | }; | |
831 | sdmmc1_wp_n_pv3 { | |
832 | nvidia,pins = "sdmmc1_wp_n_pv3"; | |
833 | nvidia,function = "sdmmc1"; | |
834 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
835 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
836 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
837 | }; | |
838 | ddc_scl_pv4 { | |
839 | nvidia,pins = "ddc_scl_pv4"; | |
840 | nvidia,function = "i2c4"; | |
841 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
842 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
843 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
844 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
845 | }; | |
846 | ddc_sda_pv5 { | |
847 | nvidia,pins = "ddc_sda_pv5"; | |
848 | nvidia,function = "i2c4"; | |
849 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
850 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
851 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
852 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
853 | }; | |
854 | gpio_w2_aud_pw2 { | |
855 | nvidia,pins = "gpio_w2_aud_pw2"; | |
856 | nvidia,function = "rsvd2"; | |
857 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
858 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
859 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
860 | }; | |
861 | gpio_w3_aud_pw3 { | |
862 | nvidia,pins = "gpio_w3_aud_pw3"; | |
863 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
864 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
865 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
866 | }; | |
867 | dap_mclk1_pw4 { | |
868 | nvidia,pins = "dap_mclk1_pw4"; | |
869 | nvidia,function = "extperiph1"; | |
870 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
871 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
872 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
873 | }; | |
874 | clk2_out_pw5 { | |
875 | nvidia,pins = "clk2_out_pw5"; | |
876 | nvidia,function = "rsvd2"; | |
877 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
878 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
879 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
880 | }; | |
881 | uart3_txd_pw6 { | |
882 | nvidia,pins = "uart3_txd_pw6"; | |
883 | nvidia,function = "rsvd2"; | |
884 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
885 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
886 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
887 | }; | |
888 | uart3_rxd_pw7 { | |
889 | nvidia,pins = "uart3_rxd_pw7"; | |
890 | nvidia,function = "rsvd2"; | |
891 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
892 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
893 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
894 | }; | |
895 | dvfs_pwm_px0 { | |
896 | nvidia,pins = "dvfs_pwm_px0"; | |
897 | nvidia,function = "cldvfs"; | |
898 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
899 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
900 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
901 | }; | |
902 | gpio_x1_aud_px1 { | |
903 | nvidia,pins = "gpio_x1_aud_px1"; | |
904 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
905 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
906 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
907 | }; | |
908 | dvfs_clk_px2 { | |
909 | nvidia,pins = "dvfs_clk_px2"; | |
910 | nvidia,function = "cldvfs"; | |
911 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
912 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
913 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
914 | }; | |
915 | gpio_x3_aud_px3 { | |
916 | nvidia,pins = "gpio_x3_aud_px3"; | |
917 | nvidia,function = "rsvd4"; | |
918 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
919 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
920 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
921 | }; | |
922 | gpio_x4_aud_px4 { | |
923 | nvidia,pins = "gpio_x4_aud_px4"; | |
924 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
925 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
926 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
927 | }; | |
928 | gpio_x5_aud_px5 { | |
929 | nvidia,pins = "gpio_x5_aud_px5"; | |
930 | nvidia,function = "rsvd4"; | |
931 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
932 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
933 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
934 | }; | |
935 | gpio_x6_aud_px6 { | |
936 | nvidia,pins = "gpio_x6_aud_px6"; | |
937 | nvidia,function = "gmi"; | |
938 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
939 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
940 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
941 | }; | |
942 | gpio_x7_aud_px7 { | |
943 | nvidia,pins = "gpio_x7_aud_px7"; | |
944 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
945 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
946 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
947 | }; | |
948 | ulpi_clk_py0 { | |
949 | nvidia,pins = "ulpi_clk_py0"; | |
950 | nvidia,function = "spi1"; | |
951 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
952 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
953 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
954 | }; | |
955 | ulpi_dir_py1 { | |
956 | nvidia,pins = "ulpi_dir_py1"; | |
957 | nvidia,function = "spi1"; | |
958 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
959 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
960 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
961 | }; | |
962 | ulpi_nxt_py2 { | |
963 | nvidia,pins = "ulpi_nxt_py2"; | |
964 | nvidia,function = "spi1"; | |
965 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
966 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
967 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
968 | }; | |
969 | ulpi_stp_py3 { | |
970 | nvidia,pins = "ulpi_stp_py3"; | |
971 | nvidia,function = "spi1"; | |
972 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
973 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
974 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
975 | }; | |
976 | sdmmc1_dat3_py4 { | |
977 | nvidia,pins = "sdmmc1_dat3_py4"; | |
978 | nvidia,function = "sdmmc1"; | |
979 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
980 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
981 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
982 | }; | |
983 | sdmmc1_dat2_py5 { | |
984 | nvidia,pins = "sdmmc1_dat2_py5"; | |
985 | nvidia,function = "sdmmc1"; | |
986 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
987 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
988 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
989 | }; | |
990 | sdmmc1_dat1_py6 { | |
991 | nvidia,pins = "sdmmc1_dat1_py6"; | |
992 | nvidia,function = "sdmmc1"; | |
993 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
994 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
995 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
996 | }; | |
997 | sdmmc1_dat0_py7 { | |
998 | nvidia,pins = "sdmmc1_dat0_py7"; | |
999 | nvidia,function = "sdmmc1"; | |
1000 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1001 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1002 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1003 | }; | |
1004 | sdmmc1_clk_pz0 { | |
1005 | nvidia,pins = "sdmmc1_clk_pz0"; | |
1006 | nvidia,function = "sdmmc1"; | |
1007 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1008 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1009 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1010 | }; | |
1011 | sdmmc1_cmd_pz1 { | |
1012 | nvidia,pins = "sdmmc1_cmd_pz1"; | |
1013 | nvidia,function = "sdmmc1"; | |
1014 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1015 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1016 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1017 | }; | |
1018 | pwr_i2c_scl_pz6 { | |
1019 | nvidia,pins = "pwr_i2c_scl_pz6"; | |
1020 | nvidia,function = "i2cpwr"; | |
1021 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1022 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1023 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1024 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1025 | }; | |
1026 | pwr_i2c_sda_pz7 { | |
1027 | nvidia,pins = "pwr_i2c_sda_pz7"; | |
1028 | nvidia,function = "i2cpwr"; | |
1029 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1030 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1031 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1032 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1033 | }; | |
1034 | sdmmc4_dat0_paa0 { | |
1035 | nvidia,pins = "sdmmc4_dat0_paa0"; | |
1036 | nvidia,function = "sdmmc4"; | |
1037 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1038 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1039 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1040 | }; | |
1041 | sdmmc4_dat1_paa1 { | |
1042 | nvidia,pins = "sdmmc4_dat1_paa1"; | |
1043 | nvidia,function = "sdmmc4"; | |
1044 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1045 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1046 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1047 | }; | |
1048 | sdmmc4_dat2_paa2 { | |
1049 | nvidia,pins = "sdmmc4_dat2_paa2"; | |
1050 | nvidia,function = "sdmmc4"; | |
1051 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1052 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1053 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1054 | }; | |
1055 | sdmmc4_dat3_paa3 { | |
1056 | nvidia,pins = "sdmmc4_dat3_paa3"; | |
1057 | nvidia,function = "sdmmc4"; | |
1058 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1059 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1060 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1061 | }; | |
1062 | sdmmc4_dat4_paa4 { | |
1063 | nvidia,pins = "sdmmc4_dat4_paa4"; | |
1064 | nvidia,function = "sdmmc4"; | |
1065 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1066 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1067 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1068 | }; | |
1069 | sdmmc4_dat5_paa5 { | |
1070 | nvidia,pins = "sdmmc4_dat5_paa5"; | |
1071 | nvidia,function = "sdmmc4"; | |
1072 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1073 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1074 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1075 | }; | |
1076 | sdmmc4_dat6_paa6 { | |
1077 | nvidia,pins = "sdmmc4_dat6_paa6"; | |
1078 | nvidia,function = "sdmmc4"; | |
1079 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1080 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1081 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1082 | }; | |
1083 | sdmmc4_dat7_paa7 { | |
1084 | nvidia,pins = "sdmmc4_dat7_paa7"; | |
1085 | nvidia,function = "sdmmc4"; | |
1086 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1087 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1088 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1089 | }; | |
1090 | pbb0 { | |
1091 | nvidia,pins = "pbb0"; | |
1092 | nvidia,function = "vgp6"; | |
1093 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1094 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1095 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1096 | }; | |
1097 | cam_i2c_scl_pbb1 { | |
1098 | nvidia,pins = "cam_i2c_scl_pbb1"; | |
1099 | nvidia,function = "rsvd3"; | |
1100 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1101 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1102 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1103 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1104 | }; | |
1105 | cam_i2c_sda_pbb2 { | |
1106 | nvidia,pins = "cam_i2c_sda_pbb2"; | |
1107 | nvidia,function = "rsvd3"; | |
1108 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1109 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1110 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1111 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1112 | }; | |
1113 | pbb3 { | |
1114 | nvidia,pins = "pbb3"; | |
1115 | nvidia,function = "vgp3"; | |
1116 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1117 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1118 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1119 | }; | |
1120 | pbb4 { | |
1121 | nvidia,pins = "pbb4"; | |
1122 | nvidia,function = "vgp4"; | |
1123 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1124 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1125 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1126 | }; | |
1127 | pbb5 { | |
1128 | nvidia,pins = "pbb5"; | |
1129 | nvidia,function = "rsvd3"; | |
1130 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1131 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1132 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1133 | }; | |
1134 | pbb6 { | |
1135 | nvidia,pins = "pbb6"; | |
1136 | nvidia,function = "rsvd2"; | |
1137 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1138 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1139 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1140 | }; | |
1141 | pbb7 { | |
1142 | nvidia,pins = "pbb7"; | |
1143 | nvidia,function = "rsvd2"; | |
1144 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1145 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1146 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1147 | }; | |
1148 | cam_mclk_pcc0 { | |
1149 | nvidia,pins = "cam_mclk_pcc0"; | |
1150 | nvidia,function = "vi"; | |
1151 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1152 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1153 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1154 | }; | |
1155 | pcc1 { | |
1156 | nvidia,pins = "pcc1"; | |
1157 | nvidia,function = "rsvd2"; | |
1158 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1159 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1160 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1161 | }; | |
1162 | pcc2 { | |
1163 | nvidia,pins = "pcc2"; | |
1164 | nvidia,function = "rsvd2"; | |
1165 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1166 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1167 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1168 | }; | |
1169 | sdmmc4_clk_pcc4 { | |
1170 | nvidia,pins = "sdmmc4_clk_pcc4"; | |
1171 | nvidia,function = "sdmmc4"; | |
1172 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1173 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1174 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1175 | }; | |
1176 | clk2_req_pcc5 { | |
1177 | nvidia,pins = "clk2_req_pcc5"; | |
1178 | nvidia,function = "rsvd2"; | |
1179 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1180 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1181 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1182 | }; | |
1183 | pex_l0_rst_n_pdd1 { | |
1184 | nvidia,pins = "pex_l0_rst_n_pdd1"; | |
1185 | nvidia,function = "rsvd2"; | |
1186 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1187 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1188 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1189 | }; | |
1190 | pex_l0_clkreq_n_pdd2 { | |
1191 | nvidia,pins = "pex_l0_clkreq_n_pdd2"; | |
1192 | nvidia,function = "rsvd2"; | |
1193 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1194 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1195 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1196 | }; | |
1197 | pex_wake_n_pdd3 { | |
1198 | nvidia,pins = "pex_wake_n_pdd3"; | |
1199 | nvidia,function = "rsvd2"; | |
1200 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1201 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1202 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1203 | }; | |
1204 | pex_l1_rst_n_pdd5 { | |
1205 | nvidia,pins = "pex_l1_rst_n_pdd5"; | |
1206 | nvidia,function = "rsvd2"; | |
1207 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1208 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1209 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1210 | }; | |
1211 | pex_l1_clkreq_n_pdd6 { | |
1212 | nvidia,pins = "pex_l1_clkreq_n_pdd6"; | |
1213 | nvidia,function = "rsvd2"; | |
1214 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1215 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1216 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1217 | }; | |
1218 | clk3_out_pee0 { | |
1219 | nvidia,pins = "clk3_out_pee0"; | |
1220 | nvidia,function = "rsvd2"; | |
1221 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1222 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1223 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1224 | }; | |
1225 | clk3_req_pee1 { | |
1226 | nvidia,pins = "clk3_req_pee1"; | |
1227 | nvidia,function = "rsvd2"; | |
1228 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1229 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1230 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1231 | }; | |
1232 | dap_mclk1_req_pee2 { | |
1233 | nvidia,pins = "dap_mclk1_req_pee2"; | |
1234 | nvidia,function = "rsvd4"; | |
1235 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1236 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1237 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1238 | }; | |
1239 | hdmi_cec_pee3 { | |
1240 | nvidia,pins = "hdmi_cec_pee3"; | |
1241 | nvidia,function = "cec"; | |
1242 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1243 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1244 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1245 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1246 | }; | |
1247 | sdmmc3_clk_lb_out_pee4 { | |
1248 | nvidia,pins = "sdmmc3_clk_lb_out_pee4"; | |
1249 | nvidia,function = "sdmmc3"; | |
1250 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1251 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1252 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1253 | }; | |
1254 | sdmmc3_clk_lb_in_pee5 { | |
1255 | nvidia,pins = "sdmmc3_clk_lb_in_pee5"; | |
1256 | nvidia,function = "sdmmc3"; | |
1257 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1258 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1259 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1260 | }; | |
1261 | dp_hpd_pff0 { | |
1262 | nvidia,pins = "dp_hpd_pff0"; | |
1263 | nvidia,function = "dp"; | |
1264 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1265 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1266 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1267 | }; | |
1268 | usb_vbus_en2_pff1 { | |
1269 | nvidia,pins = "usb_vbus_en2_pff1"; | |
1270 | nvidia,function = "rsvd2"; | |
1271 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1272 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1273 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1274 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1275 | }; | |
1276 | pff2 { | |
1277 | nvidia,pins = "pff2"; | |
1278 | nvidia,function = "rsvd2"; | |
1279 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1280 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1281 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1282 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1283 | }; | |
1284 | core_pwr_req { | |
1285 | nvidia,pins = "core_pwr_req"; | |
1286 | nvidia,function = "pwron"; | |
1287 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1288 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1289 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1290 | }; | |
1291 | cpu_pwr_req { | |
1292 | nvidia,pins = "cpu_pwr_req"; | |
1293 | nvidia,function = "cpu"; | |
1294 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1295 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1296 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1297 | }; | |
1298 | pwr_int_n { | |
1299 | nvidia,pins = "pwr_int_n"; | |
1300 | nvidia,function = "pmi"; | |
1301 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1302 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1303 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1304 | }; | |
1305 | reset_out_n { | |
1306 | nvidia,pins = "reset_out_n"; | |
1307 | nvidia,function = "reset_out_n"; | |
1308 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1309 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1310 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1311 | }; | |
1312 | owr { | |
1313 | nvidia,pins = "owr"; | |
1314 | nvidia,function = "rsvd2"; | |
1315 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1316 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1317 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1318 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
1319 | }; | |
1320 | clk_32k_in { | |
1321 | nvidia,pins = "clk_32k_in"; | |
1322 | nvidia,function = "clk"; | |
1323 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1324 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1325 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1326 | }; | |
1327 | jtag_rtck { | |
1328 | nvidia,pins = "jtag_rtck"; | |
1329 | nvidia,function = "rtck"; | |
1330 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1331 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1332 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1333 | }; | |
eb481f9a DR |
1334 | }; |
1335 | }; | |
eb481f9a | 1336 | }; |