projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 59fe02cb TV |
1 | /dts-v1/; |
| 2 | ||
| 3 | #include "tegra124-nyan.dtsi" | |
| 4 | ||
| 5 | / { | |
| 6 | model = "HP Chromebook 14"; | |
| 7 | compatible = "google,nyan-blaze", "google,nyan", "nvidia,tegra124"; | |
| 8 | ||
| 9 | panel: panel { | |
| 10 | compatible = "samsung,ltn140at29-301"; | |
| 11 | ||
| 12 | backlight = <&backlight>; | |
| 13 | ddc-i2c-bus = <&dpaux>; | |
| 14 | }; | |
| 15 | ||
| 16 | sound { | |
| 17 | compatible = "nvidia,tegra-audio-max98090-nyan-blaze", | |
| 18 | "nvidia,tegra-audio-max98090-nyan", | |
| 19 | "nvidia,tegra-audio-max98090"; | |
| 20 | nvidia,model = "GoogleNyanBlaze"; | |
| 21 | }; | |
| 22 | ||
| 23 | pinmux@0,70000868 { | |
| 24 | pinctrl-names = "default"; | |
| 25 | pinctrl-0 = <&pinmux_default>; | |
| 26 | ||
| 27 | pinmux_default: common { | |
| 28 | clk_32k_out_pa0 { | |
| 29 | nvidia,pins = "clk_32k_out_pa0"; | |
| 30 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 31 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 32 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 33 | }; | |
| 34 | uart3_cts_n_pa1 { | |
| 35 | nvidia,pins = "uart3_cts_n_pa1"; | |
| 36 | nvidia,function = "gmi"; | |
| 37 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 38 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 39 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 40 | }; | |
| 41 | dap2_fs_pa2 { | |
| 42 | nvidia,pins = "dap2_fs_pa2"; | |
| 43 | nvidia,function = "i2s1"; | |
| 44 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 45 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 46 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 47 | }; | |
| 48 | dap2_sclk_pa3 { | |
| 49 | nvidia,pins = "dap2_sclk_pa3"; | |
| 50 | nvidia,function = "i2s1"; | |
| 51 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 52 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 53 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 54 | }; | |
| 55 | dap2_din_pa4 { | |
| 56 | nvidia,pins = "dap2_din_pa4"; | |
| 57 | nvidia,function = "i2s1"; | |
| 58 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 59 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 60 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 61 | }; | |
| 62 | dap2_dout_pa5 { | |
| 63 | nvidia,pins = "dap2_dout_pa5"; | |
| 64 | nvidia,function = "i2s1"; | |
| 65 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 66 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 67 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 68 | }; | |
| 69 | sdmmc3_clk_pa6 { | |
| 70 | nvidia,pins = "sdmmc3_clk_pa6"; | |
| 71 | nvidia,function = "sdmmc3"; | |
| 72 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 73 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 74 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 75 | }; | |
| 76 | sdmmc3_cmd_pa7 { | |
| 77 | nvidia,pins = "sdmmc3_cmd_pa7"; | |
| 78 | nvidia,function = "sdmmc3"; | |
| 79 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 80 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 81 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 82 | }; | |
| 83 | pb0 { | |
| 84 | nvidia,pins = "pb0"; | |
| 85 | nvidia,function = "rsvd2"; | |
| 86 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 87 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 88 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 89 | }; | |
| 90 | pb1 { | |
| 91 | nvidia,pins = "pb1"; | |
| 92 | nvidia,function = "rsvd2"; | |
| 93 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 94 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 95 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 96 | }; | |
| 97 | sdmmc3_dat3_pb4 { | |
| 98 | nvidia,pins = "sdmmc3_dat3_pb4"; | |
| 99 | nvidia,function = "sdmmc3"; | |
| 100 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 101 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 102 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 103 | }; | |
| 104 | sdmmc3_dat2_pb5 { | |
| 105 | nvidia,pins = "sdmmc3_dat2_pb5"; | |
| 106 | nvidia,function = "sdmmc3"; | |
| 107 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 108 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 109 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 110 | }; | |
| 111 | sdmmc3_dat1_pb6 { | |
| 112 | nvidia,pins = "sdmmc3_dat1_pb6"; | |
| 113 | nvidia,function = "sdmmc3"; | |
| 114 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 115 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 116 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 117 | }; | |
| 118 | sdmmc3_dat0_pb7 { | |
| 119 | nvidia,pins = "sdmmc3_dat0_pb7"; | |
| 120 | nvidia,function = "sdmmc3"; | |
| 121 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 122 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 123 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 124 | }; | |
| 125 | uart3_rts_n_pc0 { | |
| 126 | nvidia,pins = "uart3_rts_n_pc0"; | |
| 127 | nvidia,function = "gmi"; | |
| 128 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 129 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 130 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 131 | }; | |
| 132 | uart2_txd_pc2 { | |
| 133 | nvidia,pins = "uart2_txd_pc2"; | |
| 134 | nvidia,function = "irda"; | |
| 135 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 136 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 137 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 138 | }; | |
| 139 | uart2_rxd_pc3 { | |
| 140 | nvidia,pins = "uart2_rxd_pc3"; | |
| 141 | nvidia,function = "irda"; | |
| 142 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 143 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 144 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 145 | }; | |
| 146 | gen1_i2c_scl_pc4 { | |
| 147 | nvidia,pins = "gen1_i2c_scl_pc4"; | |
| 148 | nvidia,function = "i2c1"; | |
| 149 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 150 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 151 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 152 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| 153 | }; | |
| 154 | gen1_i2c_sda_pc5 { | |
| 155 | nvidia,pins = "gen1_i2c_sda_pc5"; | |
| 156 | nvidia,function = "i2c1"; | |
| 157 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 158 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 159 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 160 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| 161 | }; | |
| 162 | pc7 { | |
| 163 | nvidia,pins = "pc7"; | |
| 164 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 165 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 166 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 167 | }; | |
| 168 | pg0 { | |
| 169 | nvidia,pins = "pg0"; | |
| 170 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 171 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 172 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 173 | }; | |
| 174 | pg1 { | |
| 175 | nvidia,pins = "pg1"; | |
| 176 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 177 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 178 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 179 | }; | |
| 180 | pg2 { | |
| 181 | nvidia,pins = "pg2"; | |
| 182 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 183 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 184 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 185 | }; | |
| 186 | pg3 { | |
| 187 | nvidia,pins = "pg3"; | |
| 188 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 189 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 190 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 191 | }; | |
| 192 | pg4 { | |
| 193 | nvidia,pins = "pg4"; | |
| 194 | nvidia,function = "spi4"; | |
| 195 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 196 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 197 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 198 | }; | |
| 199 | pg5 { | |
| 200 | nvidia,pins = "pg5"; | |
| 201 | nvidia,function = "spi4"; | |
| 202 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 203 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 204 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 205 | }; | |
| 206 | pg6 { | |
| 207 | nvidia,pins = "pg6"; | |
| 208 | nvidia,function = "spi4"; | |
| 209 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 210 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 211 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 212 | }; | |
| 213 | pg7 { | |
| 214 | nvidia,pins = "pg7"; | |
| 215 | nvidia,function = "spi4"; | |
| 216 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 217 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 218 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 219 | }; | |
| 220 | ph0 { | |
| 221 | nvidia,pins = "ph0"; | |
| 222 | nvidia,function = "gmi"; | |
| 223 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 224 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 225 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 226 | }; | |
| 227 | ph1 { | |
| 228 | nvidia,pins = "ph1"; | |
| 229 | nvidia,function = "pwm1"; | |
| 230 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 231 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 232 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 233 | }; | |
| 234 | ph2 { | |
| 235 | nvidia,pins = "ph2"; | |
| 236 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 237 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 238 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 239 | }; | |
| 240 | ph3 { | |
| 241 | nvidia,pins = "ph3"; | |
| 242 | nvidia,function = "gmi"; | |
| 243 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 244 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 245 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 246 | }; | |
| 247 | ph4 { | |
| 248 | nvidia,pins = "ph4"; | |
| 249 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 250 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 251 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 252 | }; | |
| 253 | ph5 { | |
| 254 | nvidia,pins = "ph5"; | |
| 255 | nvidia,function = "rsvd2"; | |
| 256 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 257 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 258 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 259 | }; | |
| 260 | ph6 { | |
| 261 | nvidia,pins = "ph6"; | |
| 262 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 263 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 264 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 265 | }; | |
| 266 | ph7 { | |
| 267 | nvidia,pins = "ph7"; | |
| 268 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 269 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 270 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 271 | }; | |
| 272 | pi0 { | |
| 273 | nvidia,pins = "pi0"; | |
| 274 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 275 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 276 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 277 | }; | |
| 278 | pi1 { | |
| 279 | nvidia,pins = "pi1"; | |
| 280 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 281 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 282 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 283 | }; | |
| 284 | pi2 { | |
| 285 | nvidia,pins = "pi2"; | |
| 286 | nvidia,function = "rsvd4"; | |
| 287 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 288 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 289 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 290 | }; | |
| 291 | pi3 { | |
| 292 | nvidia,pins = "pi3"; | |
| 293 | nvidia,function = "spi4"; | |
| 294 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 295 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 296 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 297 | }; | |
| 298 | pi4 { | |
| 299 | nvidia,pins = "pi4"; | |
| 300 | nvidia,function = "gmi"; | |
| 301 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 302 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 303 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 304 | }; | |
| 305 | pi5 { | |
| 306 | nvidia,pins = "pi5"; | |
| 307 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 308 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 309 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 310 | }; | |
| 311 | pi6 { | |
| 312 | nvidia,pins = "pi6"; | |
| 313 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 314 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 315 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 316 | }; | |
| 317 | pi7 { | |
| 318 | nvidia,pins = "pi7"; | |
| 319 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 320 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 321 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 322 | }; | |
| 323 | pj0 { | |
| 324 | nvidia,pins = "pj0"; | |
| 325 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 326 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 327 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 328 | }; | |
| 329 | pj2 { | |
| 330 | nvidia,pins = "pj2"; | |
| 331 | nvidia,function = "rsvd1"; | |
| 332 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 333 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 334 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 335 | }; | |
| 336 | uart2_cts_n_pj5 { | |
| 337 | nvidia,pins = "uart2_cts_n_pj5"; | |
| 338 | nvidia,function = "gmi"; | |
| 339 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 340 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 341 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 342 | }; | |
| 343 | uart2_rts_n_pj6 { | |
| 344 | nvidia,pins = "uart2_rts_n_pj6"; | |
| 345 | nvidia,function = "gmi"; | |
| 346 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 347 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 348 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 349 | }; | |
| 350 | pj7 { | |
| 351 | nvidia,pins = "pj7"; | |
| 352 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 353 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 354 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 355 | }; | |
| 356 | pk0 { | |
| 357 | nvidia,pins = "pk0"; | |
| 358 | nvidia,function = "rsvd1"; | |
| 359 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 360 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 361 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 362 | }; | |
| 363 | pk1 { | |
| 364 | nvidia,pins = "pk1"; | |
| 365 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 366 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 367 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 368 | }; | |
| 369 | pk2 { | |
| 370 | nvidia,pins = "pk2"; | |
| 371 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 372 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 373 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 374 | }; | |
| 375 | pk3 { | |
| 376 | nvidia,pins = "pk3"; | |
| 377 | nvidia,function = "gmi"; | |
| 378 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 379 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 380 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 381 | }; | |
| 382 | pk4 { | |
| 383 | nvidia,pins = "pk4"; | |
| 384 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 385 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 386 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 387 | }; | |
| 388 | spdif_out_pk5 { | |
| 389 | nvidia,pins = "spdif_out_pk5"; | |
| 390 | nvidia,function = "rsvd2"; | |
| 391 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 392 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 393 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 394 | }; | |
| 395 | spdif_in_pk6 { | |
| 396 | nvidia,pins = "spdif_in_pk6"; | |
| 397 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 398 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 399 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 400 | }; | |
| 401 | pk7 { | |
| 402 | nvidia,pins = "pk7"; | |
| 403 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 404 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 405 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 406 | }; | |
| 407 | dap1_fs_pn0 { | |
| 408 | nvidia,pins = "dap1_fs_pn0"; | |
| 409 | nvidia,function = "rsvd4"; | |
| 410 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 411 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 412 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 413 | }; | |
| 414 | dap1_din_pn1 { | |
| 415 | nvidia,pins = "dap1_din_pn1"; | |
| 416 | nvidia,function = "rsvd4"; | |
| 417 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 418 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 419 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 420 | }; | |
| 421 | dap1_dout_pn2 { | |
| 422 | nvidia,pins = "dap1_dout_pn2"; | |
| 423 | nvidia,function = "i2s0"; | |
| 424 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 425 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 426 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 427 | }; | |
| 428 | dap1_sclk_pn3 { | |
| 429 | nvidia,pins = "dap1_sclk_pn3"; | |
| 430 | nvidia,function = "rsvd4"; | |
| 431 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 432 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 433 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 434 | }; | |
| 435 | usb_vbus_en0_pn4 { | |
| 436 | nvidia,pins = "usb_vbus_en0_pn4"; | |
| 437 | nvidia,function = "usb"; | |
| 438 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 439 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 440 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 441 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
| 442 | }; | |
| 443 | usb_vbus_en1_pn5 { | |
| 444 | nvidia,pins = "usb_vbus_en1_pn5"; | |
| 445 | nvidia,function = "usb"; | |
| 446 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 447 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 448 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 449 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
| 450 | }; | |
| 451 | hdmi_int_pn7 { | |
| 452 | nvidia,pins = "hdmi_int_pn7"; | |
| 453 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 454 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 455 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 456 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
| 457 | }; | |
| 458 | ulpi_data7_po0 { | |
| 459 | nvidia,pins = "ulpi_data7_po0"; | |
| 460 | nvidia,function = "ulpi"; | |
| 461 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 462 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 463 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 464 | }; | |
| 465 | ulpi_data0_po1 { | |
| 466 | nvidia,pins = "ulpi_data0_po1"; | |
| 467 | nvidia,function = "ulpi"; | |
| 468 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 469 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 470 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 471 | }; | |
| 472 | ulpi_data1_po2 { | |
| 473 | nvidia,pins = "ulpi_data1_po2"; | |
| 474 | nvidia,function = "ulpi"; | |
| 475 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 476 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 477 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 478 | }; | |
| 479 | ulpi_data2_po3 { | |
| 480 | nvidia,pins = "ulpi_data2_po3"; | |
| 481 | nvidia,function = "ulpi"; | |
| 482 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 483 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 484 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 485 | }; | |
| 486 | ulpi_data3_po4 { | |
| 487 | nvidia,pins = "ulpi_data3_po4"; | |
| 488 | nvidia,function = "ulpi"; | |
| 489 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 490 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 491 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 492 | }; | |
| 493 | ulpi_data4_po5 { | |
| 494 | nvidia,pins = "ulpi_data4_po5"; | |
| 495 | nvidia,function = "ulpi"; | |
| 496 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 497 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 498 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 499 | }; | |
| 500 | ulpi_data5_po6 { | |
| 501 | nvidia,pins = "ulpi_data5_po6"; | |
| 502 | nvidia,function = "ulpi"; | |
| 503 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 504 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 505 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 506 | }; | |
| 507 | ulpi_data6_po7 { | |
| 508 | nvidia,pins = "ulpi_data6_po7"; | |
| 509 | nvidia,function = "ulpi"; | |
| 510 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 511 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 512 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 513 | }; | |
| 514 | dap3_fs_pp0 { | |
| 515 | nvidia,pins = "dap3_fs_pp0"; | |
| 516 | nvidia,function = "i2s2"; | |
| 517 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 518 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 519 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 520 | }; | |
| 521 | dap3_din_pp1 { | |
| 522 | nvidia,pins = "dap3_din_pp1"; | |
| 523 | nvidia,function = "i2s2"; | |
| 524 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 525 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 526 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 527 | }; | |
| 528 | dap3_dout_pp2 { | |
| 529 | nvidia,pins = "dap3_dout_pp2"; | |
| 530 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 531 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 532 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 533 | }; | |
| 534 | dap3_sclk_pp3 { | |
| 535 | nvidia,pins = "dap3_sclk_pp3"; | |
| 536 | nvidia,function = "rsvd3"; | |
| 537 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 538 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 539 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 540 | }; | |
| 541 | dap4_fs_pp4 { | |
| 542 | nvidia,pins = "dap4_fs_pp4"; | |
| 543 | nvidia,function = "rsvd4"; | |
| 544 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 545 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 546 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 547 | }; | |
| 548 | dap4_din_pp5 { | |
| 549 | nvidia,pins = "dap4_din_pp5"; | |
| 550 | nvidia,function = "rsvd3"; | |
| 551 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 552 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 553 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 554 | }; | |
| 555 | dap4_dout_pp6 { | |
| 556 | nvidia,pins = "dap4_dout_pp6"; | |
| 557 | nvidia,function = "rsvd4"; | |
| 558 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 559 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 560 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 561 | }; | |
| 562 | dap4_sclk_pp7 { | |
| 563 | nvidia,pins = "dap4_sclk_pp7"; | |
| 564 | nvidia,function = "rsvd3"; | |
| 565 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 566 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 567 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 568 | }; | |
| 569 | kb_col0_pq0 { | |
| 570 | nvidia,pins = "kb_col0_pq0"; | |
| 571 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 572 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 573 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 574 | }; | |
| 575 | kb_col1_pq1 { | |
| 576 | nvidia,pins = "kb_col1_pq1"; | |
| 577 | nvidia,function = "rsvd2"; | |
| 578 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 579 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 580 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 581 | }; | |
| 582 | kb_col2_pq2 { | |
| 583 | nvidia,pins = "kb_col2_pq2"; | |
| 584 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 585 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 586 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 587 | }; | |
| 588 | kb_col3_pq3 { | |
| 589 | nvidia,pins = "kb_col3_pq3"; | |
| 590 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 591 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 592 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 593 | }; | |
| 594 | kb_col4_pq4 { | |
| 595 | nvidia,pins = "kb_col4_pq4"; | |
| 596 | nvidia,function = "sdmmc3"; | |
| 597 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 598 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 599 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 600 | }; | |
| 601 | kb_col5_pq5 { | |
| 602 | nvidia,pins = "kb_col5_pq5"; | |
| 603 | nvidia,function = "rsvd2"; | |
| 604 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 605 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 606 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 607 | }; | |
| 608 | kb_col6_pq6 { | |
| 609 | nvidia,pins = "kb_col6_pq6"; | |
| 610 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 611 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 612 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 613 | }; | |
| 614 | kb_col7_pq7 { | |
| 615 | nvidia,pins = "kb_col7_pq7"; | |
| 616 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 617 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 618 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 619 | }; | |
| 620 | kb_row0_pr0 { | |
| 621 | nvidia,pins = "kb_row0_pr0"; | |
| 622 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 623 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 624 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 625 | }; | |
| 626 | kb_row1_pr1 { | |
| 627 | nvidia,pins = "kb_row1_pr1"; | |
| 628 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 629 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 630 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 631 | }; | |
| 632 | kb_row2_pr2 { | |
| 633 | nvidia,pins = "kb_row2_pr2"; | |
| 634 | nvidia,function = "rsvd2"; | |
| 635 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 636 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 637 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 638 | }; | |
| 639 | kb_row3_pr3 { | |
| 640 | nvidia,pins = "kb_row3_pr3"; | |
| 641 | nvidia,function = "kbc"; | |
| 642 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 643 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 644 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 645 | }; | |
| 646 | kb_row4_pr4 { | |
| 647 | nvidia,pins = "kb_row4_pr4"; | |
| 648 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 649 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 650 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 651 | }; | |
| 652 | kb_row5_pr5 { | |
| 653 | nvidia,pins = "kb_row5_pr5"; | |
| 654 | nvidia,function = "rsvd3"; | |
| 655 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 656 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 657 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 658 | }; | |
| 659 | kb_row6_pr6 { | |
| 660 | nvidia,pins = "kb_row6_pr6"; | |
| 661 | nvidia,function = "kbc"; | |
| 662 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 663 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 664 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 665 | }; | |
| 666 | kb_row7_pr7 { | |
| 667 | nvidia,pins = "kb_row7_pr7"; | |
| 668 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 669 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 670 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 671 | }; | |
| 672 | kb_row8_ps0 { | |
| 673 | nvidia,pins = "kb_row8_ps0"; | |
| 674 | nvidia,function = "rsvd2"; | |
| 675 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 676 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 677 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 678 | }; | |
| 679 | kb_row9_ps1 { | |
| 680 | nvidia,pins = "kb_row9_ps1"; | |
| 681 | nvidia,function = "uarta"; | |
| 682 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 683 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 684 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 685 | }; | |
| 686 | kb_row10_ps2 { | |
| 687 | nvidia,pins = "kb_row10_ps2"; | |
| 688 | nvidia,function = "uarta"; | |
| 689 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 690 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 691 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 692 | }; | |
| 693 | kb_row11_ps3 { | |
| 694 | nvidia,pins = "kb_row11_ps3"; | |
| 695 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 696 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 697 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 698 | }; | |
| 699 | kb_row12_ps4 { | |
| 700 | nvidia,pins = "kb_row12_ps4"; | |
| 701 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 702 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 703 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 704 | }; | |
| 705 | kb_row13_ps5 { | |
| 706 | nvidia,pins = "kb_row13_ps5"; | |
| 707 | nvidia,function = "rsvd2"; | |
| 708 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 709 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 710 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 711 | }; | |
| 712 | kb_row14_ps6 { | |
| 713 | nvidia,pins = "kb_row14_ps6"; | |
| 714 | nvidia,function = "rsvd2"; | |
| 715 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 716 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 717 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 718 | }; | |
| 719 | kb_row15_ps7 { | |
| 720 | nvidia,pins = "kb_row15_ps7"; | |
| 721 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 722 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 723 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 724 | }; | |
| 725 | kb_row16_pt0 { | |
| 726 | nvidia,pins = "kb_row16_pt0"; | |
| 727 | nvidia,function = "rsvd2"; | |
| 728 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 729 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 730 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 731 | }; | |
| 732 | kb_row17_pt1 { | |
| 733 | nvidia,pins = "kb_row17_pt1"; | |
| 734 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 735 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 736 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 737 | }; | |
| 738 | gen2_i2c_scl_pt5 { | |
| 739 | nvidia,pins = "gen2_i2c_scl_pt5"; | |
| 740 | nvidia,function = "i2c2"; | |
| 741 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 742 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 743 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 744 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| 745 | }; | |
| 746 | gen2_i2c_sda_pt6 { | |
| 747 | nvidia,pins = "gen2_i2c_sda_pt6"; | |
| 748 | nvidia,function = "i2c2"; | |
| 749 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 750 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 751 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 752 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| 753 | }; | |
| 754 | sdmmc4_cmd_pt7 { | |
| 755 | nvidia,pins = "sdmmc4_cmd_pt7"; | |
| 756 | nvidia,function = "sdmmc4"; | |
| 757 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 758 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 759 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 760 | }; | |
| 761 | pu0 { | |
| 762 | nvidia,pins = "pu0"; | |
| 763 | nvidia,function = "rsvd4"; | |
| 764 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 765 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 766 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 767 | }; | |
| 768 | pu1 { | |
| 769 | nvidia,pins = "pu1"; | |
| 770 | nvidia,function = "rsvd1"; | |
| 771 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 772 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 773 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 774 | }; | |
| 775 | pu2 { | |
| 776 | nvidia,pins = "pu2"; | |
| 777 | nvidia,function = "rsvd1"; | |
| 778 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 779 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 780 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 781 | }; | |
| 782 | pu3 { | |
| 783 | nvidia,pins = "pu3"; | |
| 784 | nvidia,function = "gmi"; | |
| 785 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 786 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 787 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 788 | }; | |
| 789 | pu4 { | |
| 790 | nvidia,pins = "pu4"; | |
| 791 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 792 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 793 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 794 | }; | |
| 795 | pu5 { | |
| 796 | nvidia,pins = "pu5"; | |
| 797 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 798 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 799 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 800 | }; | |
| 801 | pu6 { | |
| 802 | nvidia,pins = "pu6"; | |
| 803 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 804 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 805 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 806 | }; | |
| 807 | pv0 { | |
| 808 | nvidia,pins = "pv0"; | |
| 809 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 810 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 811 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 812 | }; | |
| 813 | pv1 { | |
| 814 | nvidia,pins = "pv1"; | |
| 815 | nvidia,function = "rsvd1"; | |
| 816 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 817 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 818 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 819 | }; | |
| 820 | sdmmc3_cd_n_pv2 { | |
| 821 | nvidia,pins = "sdmmc3_cd_n_pv2"; | |
| 822 | nvidia,function = "sdmmc3"; | |
| 823 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 824 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 825 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 826 | }; | |
| 827 | sdmmc1_wp_n_pv3 { | |
| 828 | nvidia,pins = "sdmmc1_wp_n_pv3"; | |
| 829 | nvidia,function = "sdmmc1"; | |
| 830 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 831 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 832 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 833 | }; | |
| 834 | ddc_scl_pv4 { | |
| 835 | nvidia,pins = "ddc_scl_pv4"; | |
| 836 | nvidia,function = "i2c4"; | |
| 837 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 838 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 839 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 840 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
| 841 | }; | |
| 842 | ddc_sda_pv5 { | |
| 843 | nvidia,pins = "ddc_sda_pv5"; | |
| 844 | nvidia,function = "i2c4"; | |
| 845 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 846 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 847 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 848 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
| 849 | }; | |
| 850 | gpio_w2_aud_pw2 { | |
| 851 | nvidia,pins = "gpio_w2_aud_pw2"; | |
| 852 | nvidia,function = "rsvd2"; | |
| 853 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 854 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 855 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 856 | }; | |
| 857 | gpio_w3_aud_pw3 { | |
| 858 | nvidia,pins = "gpio_w3_aud_pw3"; | |
| 859 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 860 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 861 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 862 | }; | |
| 863 | dap_mclk1_pw4 { | |
| 864 | nvidia,pins = "dap_mclk1_pw4"; | |
| 865 | nvidia,function = "extperiph1"; | |
| 866 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 867 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 868 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 869 | }; | |
| 870 | clk2_out_pw5 { | |
| 871 | nvidia,pins = "clk2_out_pw5"; | |
| 872 | nvidia,function = "rsvd2"; | |
| 873 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 874 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 875 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 876 | }; | |
| 877 | uart3_txd_pw6 { | |
| 878 | nvidia,pins = "uart3_txd_pw6"; | |
| 879 | nvidia,function = "rsvd2"; | |
| 880 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 881 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 882 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 883 | }; | |
| 884 | uart3_rxd_pw7 { | |
| 885 | nvidia,pins = "uart3_rxd_pw7"; | |
| 886 | nvidia,function = "rsvd2"; | |
| 887 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 888 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 889 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 890 | }; | |
| 891 | dvfs_pwm_px0 { | |
| 892 | nvidia,pins = "dvfs_pwm_px0"; | |
| 893 | nvidia,function = "cldvfs"; | |
| 894 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 895 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 896 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 897 | }; | |
| 898 | gpio_x1_aud_px1 { | |
| 899 | nvidia,pins = "gpio_x1_aud_px1"; | |
| 900 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 901 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 902 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 903 | }; | |
| 904 | dvfs_clk_px2 { | |
| 905 | nvidia,pins = "dvfs_clk_px2"; | |
| 906 | nvidia,function = "cldvfs"; | |
| 907 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 908 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 909 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 910 | }; | |
| 911 | gpio_x3_aud_px3 { | |
| 912 | nvidia,pins = "gpio_x3_aud_px3"; | |
| 913 | nvidia,function = "rsvd4"; | |
| 914 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 915 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 916 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 917 | }; | |
| 918 | gpio_x4_aud_px4 { | |
| 919 | nvidia,pins = "gpio_x4_aud_px4"; | |
| 920 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 921 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 922 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 923 | }; | |
| 924 | gpio_x5_aud_px5 { | |
| 925 | nvidia,pins = "gpio_x5_aud_px5"; | |
| 926 | nvidia,function = "rsvd4"; | |
| 927 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 928 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 929 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 930 | }; | |
| 931 | gpio_x6_aud_px6 { | |
| 932 | nvidia,pins = "gpio_x6_aud_px6"; | |
| 933 | nvidia,function = "gmi"; | |
| 934 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 935 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 936 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 937 | }; | |
| 938 | gpio_x7_aud_px7 { | |
| 939 | nvidia,pins = "gpio_x7_aud_px7"; | |
| 940 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 941 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 942 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 943 | }; | |
| 944 | ulpi_clk_py0 { | |
| 945 | nvidia,pins = "ulpi_clk_py0"; | |
| 946 | nvidia,function = "spi1"; | |
| 947 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 948 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 949 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 950 | }; | |
| 951 | ulpi_dir_py1 { | |
| 952 | nvidia,pins = "ulpi_dir_py1"; | |
| 953 | nvidia,function = "spi1"; | |
| 954 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 955 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 956 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 957 | }; | |
| 958 | ulpi_nxt_py2 { | |
| 959 | nvidia,pins = "ulpi_nxt_py2"; | |
| 960 | nvidia,function = "spi1"; | |
| 961 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 962 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 963 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 964 | }; | |
| 965 | ulpi_stp_py3 { | |
| 966 | nvidia,pins = "ulpi_stp_py3"; | |
| 967 | nvidia,function = "spi1"; | |
| 968 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 969 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 970 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 971 | }; | |
| 972 | sdmmc1_dat3_py4 { | |
| 973 | nvidia,pins = "sdmmc1_dat3_py4"; | |
| 974 | nvidia,function = "sdmmc1"; | |
| 975 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 976 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 977 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 978 | }; | |
| 979 | sdmmc1_dat2_py5 { | |
| 980 | nvidia,pins = "sdmmc1_dat2_py5"; | |
| 981 | nvidia,function = "sdmmc1"; | |
| 982 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 983 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 984 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 985 | }; | |
| 986 | sdmmc1_dat1_py6 { | |
| 987 | nvidia,pins = "sdmmc1_dat1_py6"; | |
| 988 | nvidia,function = "sdmmc1"; | |
| 989 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 990 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 991 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 992 | }; | |
| 993 | sdmmc1_dat0_py7 { | |
| 994 | nvidia,pins = "sdmmc1_dat0_py7"; | |
| 995 | nvidia,function = "sdmmc1"; | |
| 996 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 997 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 998 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 999 | }; | |
| 1000 | sdmmc1_clk_pz0 { | |
| 1001 | nvidia,pins = "sdmmc1_clk_pz0"; | |
| 1002 | nvidia,function = "sdmmc1"; | |
| 1003 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1004 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1005 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1006 | }; | |
| 1007 | sdmmc1_cmd_pz1 { | |
| 1008 | nvidia,pins = "sdmmc1_cmd_pz1"; | |
| 1009 | nvidia,function = "sdmmc1"; | |
| 1010 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1011 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1012 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1013 | }; | |
| 1014 | pwr_i2c_scl_pz6 { | |
| 1015 | nvidia,pins = "pwr_i2c_scl_pz6"; | |
| 1016 | nvidia,function = "i2cpwr"; | |
| 1017 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1018 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1019 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1020 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| 1021 | }; | |
| 1022 | pwr_i2c_sda_pz7 { | |
| 1023 | nvidia,pins = "pwr_i2c_sda_pz7"; | |
| 1024 | nvidia,function = "i2cpwr"; | |
| 1025 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1026 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1027 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1028 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| 1029 | }; | |
| 1030 | sdmmc4_dat0_paa0 { | |
| 1031 | nvidia,pins = "sdmmc4_dat0_paa0"; | |
| 1032 | nvidia,function = "sdmmc4"; | |
| 1033 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1034 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1035 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1036 | }; | |
| 1037 | sdmmc4_dat1_paa1 { | |
| 1038 | nvidia,pins = "sdmmc4_dat1_paa1"; | |
| 1039 | nvidia,function = "sdmmc4"; | |
| 1040 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1041 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1042 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1043 | }; | |
| 1044 | sdmmc4_dat2_paa2 { | |
| 1045 | nvidia,pins = "sdmmc4_dat2_paa2"; | |
| 1046 | nvidia,function = "sdmmc4"; | |
| 1047 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1048 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1049 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1050 | }; | |
| 1051 | sdmmc4_dat3_paa3 { | |
| 1052 | nvidia,pins = "sdmmc4_dat3_paa3"; | |
| 1053 | nvidia,function = "sdmmc4"; | |
| 1054 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1055 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1056 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1057 | }; | |
| 1058 | sdmmc4_dat4_paa4 { | |
| 1059 | nvidia,pins = "sdmmc4_dat4_paa4"; | |
| 1060 | nvidia,function = "sdmmc4"; | |
| 1061 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1062 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1063 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1064 | }; | |
| 1065 | sdmmc4_dat5_paa5 { | |
| 1066 | nvidia,pins = "sdmmc4_dat5_paa5"; | |
| 1067 | nvidia,function = "sdmmc4"; | |
| 1068 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1069 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1070 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1071 | }; | |
| 1072 | sdmmc4_dat6_paa6 { | |
| 1073 | nvidia,pins = "sdmmc4_dat6_paa6"; | |
| 1074 | nvidia,function = "sdmmc4"; | |
| 1075 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1076 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1077 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1078 | }; | |
| 1079 | sdmmc4_dat7_paa7 { | |
| 1080 | nvidia,pins = "sdmmc4_dat7_paa7"; | |
| 1081 | nvidia,function = "sdmmc4"; | |
| 1082 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1083 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1084 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1085 | }; | |
| 1086 | pbb0 { | |
| 1087 | nvidia,pins = "pbb0"; | |
| 1088 | nvidia,function = "vgp6"; | |
| 1089 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1090 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1091 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1092 | }; | |
| 1093 | cam_i2c_scl_pbb1 { | |
| 1094 | nvidia,pins = "cam_i2c_scl_pbb1"; | |
| 1095 | nvidia,function = "rsvd3"; | |
| 1096 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1097 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1098 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1099 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
| 1100 | }; | |
| 1101 | cam_i2c_sda_pbb2 { | |
| 1102 | nvidia,pins = "cam_i2c_sda_pbb2"; | |
| 1103 | nvidia,function = "rsvd3"; | |
| 1104 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1105 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1106 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1107 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
| 1108 | }; | |
| 1109 | pbb3 { | |
| 1110 | nvidia,pins = "pbb3"; | |
| 1111 | nvidia,function = "vgp3"; | |
| 1112 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1113 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1114 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1115 | }; | |
| 1116 | pbb4 { | |
| 1117 | nvidia,pins = "pbb4"; | |
| 1118 | nvidia,function = "vgp4"; | |
| 1119 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1120 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1121 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1122 | }; | |
| 1123 | pbb5 { | |
| 1124 | nvidia,pins = "pbb5"; | |
| 1125 | nvidia,function = "rsvd3"; | |
| 1126 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1127 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1128 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1129 | }; | |
| 1130 | pbb6 { | |
| 1131 | nvidia,pins = "pbb6"; | |
| 1132 | nvidia,function = "rsvd2"; | |
| 1133 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1134 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1135 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1136 | }; | |
| 1137 | pbb7 { | |
| 1138 | nvidia,pins = "pbb7"; | |
| 1139 | nvidia,function = "rsvd2"; | |
| 1140 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1141 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1142 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1143 | }; | |
| 1144 | cam_mclk_pcc0 { | |
| 1145 | nvidia,pins = "cam_mclk_pcc0"; | |
| 1146 | nvidia,function = "vi"; | |
| 1147 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1148 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1149 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1150 | }; | |
| 1151 | pcc1 { | |
| 1152 | nvidia,pins = "pcc1"; | |
| 1153 | nvidia,function = "rsvd2"; | |
| 1154 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1155 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1156 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1157 | }; | |
| 1158 | pcc2 { | |
| 1159 | nvidia,pins = "pcc2"; | |
| 1160 | nvidia,function = "rsvd2"; | |
| 1161 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1162 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1163 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1164 | }; | |
| 1165 | sdmmc4_clk_pcc4 { | |
| 1166 | nvidia,pins = "sdmmc4_clk_pcc4"; | |
| 1167 | nvidia,function = "sdmmc4"; | |
| 1168 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1169 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1170 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1171 | }; | |
| 1172 | clk2_req_pcc5 { | |
| 1173 | nvidia,pins = "clk2_req_pcc5"; | |
| 1174 | nvidia,function = "rsvd2"; | |
| 1175 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1176 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1177 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1178 | }; | |
| 1179 | pex_l0_rst_n_pdd1 { | |
| 1180 | nvidia,pins = "pex_l0_rst_n_pdd1"; | |
| 1181 | nvidia,function = "rsvd2"; | |
| 1182 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1183 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1184 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1185 | }; | |
| 1186 | pex_l0_clkreq_n_pdd2 { | |
| 1187 | nvidia,pins = "pex_l0_clkreq_n_pdd2"; | |
| 1188 | nvidia,function = "rsvd2"; | |
| 1189 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1190 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1191 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1192 | }; | |
| 1193 | pex_wake_n_pdd3 { | |
| 1194 | nvidia,pins = "pex_wake_n_pdd3"; | |
| 1195 | nvidia,function = "rsvd2"; | |
| 1196 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1197 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1198 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1199 | }; | |
| 1200 | pex_l1_rst_n_pdd5 { | |
| 1201 | nvidia,pins = "pex_l1_rst_n_pdd5"; | |
| 1202 | nvidia,function = "rsvd2"; | |
| 1203 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1204 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1205 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1206 | }; | |
| 1207 | pex_l1_clkreq_n_pdd6 { | |
| 1208 | nvidia,pins = "pex_l1_clkreq_n_pdd6"; | |
| 1209 | nvidia,function = "rsvd2"; | |
| 1210 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1211 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1212 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1213 | }; | |
| 1214 | clk3_out_pee0 { | |
| 1215 | nvidia,pins = "clk3_out_pee0"; | |
| 1216 | nvidia,function = "rsvd2"; | |
| 1217 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1218 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1219 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1220 | }; | |
| 1221 | clk3_req_pee1 { | |
| 1222 | nvidia,pins = "clk3_req_pee1"; | |
| 1223 | nvidia,function = "rsvd2"; | |
| 1224 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1225 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1226 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1227 | }; | |
| 1228 | dap_mclk1_req_pee2 { | |
| 1229 | nvidia,pins = "dap_mclk1_req_pee2"; | |
| 1230 | nvidia,function = "rsvd4"; | |
| 1231 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1232 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1233 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1234 | }; | |
| 1235 | hdmi_cec_pee3 { | |
| 1236 | nvidia,pins = "hdmi_cec_pee3"; | |
| 1237 | nvidia,function = "cec"; | |
| 1238 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1239 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1240 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1241 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
| 1242 | }; | |
| 1243 | sdmmc3_clk_lb_out_pee4 { | |
| 1244 | nvidia,pins = "sdmmc3_clk_lb_out_pee4"; | |
| 1245 | nvidia,function = "sdmmc3"; | |
| 1246 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1247 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1248 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1249 | }; | |
| 1250 | sdmmc3_clk_lb_in_pee5 { | |
| 1251 | nvidia,pins = "sdmmc3_clk_lb_in_pee5"; | |
| 1252 | nvidia,function = "sdmmc3"; | |
| 1253 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
| 1254 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1255 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1256 | }; | |
| 1257 | dp_hpd_pff0 { | |
| 1258 | nvidia,pins = "dp_hpd_pff0"; | |
| 1259 | nvidia,function = "dp"; | |
| 1260 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1261 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1262 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1263 | }; | |
| 1264 | usb_vbus_en2_pff1 { | |
| 1265 | nvidia,pins = "usb_vbus_en2_pff1"; | |
| 1266 | nvidia,function = "rsvd2"; | |
| 1267 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1268 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1269 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1270 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
| 1271 | }; | |
| 1272 | pff2 { | |
| 1273 | nvidia,pins = "pff2"; | |
| 1274 | nvidia,function = "rsvd2"; | |
| 1275 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1276 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1277 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1278 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
| 1279 | }; | |
| 1280 | core_pwr_req { | |
| 1281 | nvidia,pins = "core_pwr_req"; | |
| 1282 | nvidia,function = "pwron"; | |
| 1283 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1284 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1285 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1286 | }; | |
| 1287 | cpu_pwr_req { | |
| 1288 | nvidia,pins = "cpu_pwr_req"; | |
| 1289 | nvidia,function = "cpu"; | |
| 1290 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1291 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1292 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1293 | }; | |
| 1294 | pwr_int_n { | |
| 1295 | nvidia,pins = "pwr_int_n"; | |
| 1296 | nvidia,function = "pmi"; | |
| 1297 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1298 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1299 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1300 | }; | |
| 1301 | reset_out_n { | |
| 1302 | nvidia,pins = "reset_out_n"; | |
| 1303 | nvidia,function = "reset_out_n"; | |
| 1304 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1305 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1306 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1307 | }; | |
| 1308 | owr { | |
| 1309 | nvidia,pins = "owr"; | |
| 1310 | nvidia,function = "rsvd2"; | |
| 1311 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
| 1312 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
| 1313 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1314 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
| 1315 | }; | |
| 1316 | clk_32k_in { | |
| 1317 | nvidia,pins = "clk_32k_in"; | |
| 1318 | nvidia,function = "clk"; | |
| 1319 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1320 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1321 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
| 1322 | }; | |
| 1323 | jtag_rtck { | |
| 1324 | nvidia,pins = "jtag_rtck"; | |
| 1325 | nvidia,function = "rtck"; | |
| 1326 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
| 1327 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
| 1328 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
| 1329 | }; | |
| 1330 | }; | |
| 1331 | }; | |
| 1332 | }; |