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3b86baf2 | 1 | #include <dt-bindings/clock/tegra124-car.h> |
0a9375d1 | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
4b20bcbe | 3 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
ce90d32d | 4 | #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> |
ad03b1a7 JL |
5 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
6 | ||
7 | #include "skeleton.dtsi" | |
8 | ||
9 | / { | |
10 | compatible = "nvidia,tegra124"; | |
11 | interrupt-parent = <&gic>; | |
e30cb238 SW |
12 | #address-cells = <2>; |
13 | #size-cells = <2>; | |
ad03b1a7 | 14 | |
e30cb238 | 15 | host1x@0,50000000 { |
ad6be7d1 | 16 | compatible = "nvidia,tegra124-host1x", "simple-bus"; |
e30cb238 | 17 | reg = <0x0 0x50000000 0x0 0x00034000>; |
ad6be7d1 TR |
18 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
19 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ | |
20 | clocks = <&tegra_car TEGRA124_CLK_HOST1X>; | |
21 | resets = <&tegra_car 28>; | |
22 | reset-names = "host1x"; | |
23 | ||
e30cb238 SW |
24 | #address-cells = <2>; |
25 | #size-cells = <2>; | |
ad6be7d1 | 26 | |
e30cb238 | 27 | ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; |
ad6be7d1 | 28 | |
e30cb238 | 29 | dc@0,54200000 { |
ad6be7d1 | 30 | compatible = "nvidia,tegra124-dc"; |
e30cb238 | 31 | reg = <0x0 0x54200000 0x0 0x00040000>; |
ad6be7d1 TR |
32 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
33 | clocks = <&tegra_car TEGRA124_CLK_DISP1>, | |
34 | <&tegra_car TEGRA124_CLK_PLL_P>; | |
35 | clock-names = "dc", "parent"; | |
36 | resets = <&tegra_car 27>; | |
37 | reset-names = "dc"; | |
38 | ||
39 | nvidia,head = <0>; | |
40 | }; | |
41 | ||
e30cb238 | 42 | dc@0,54240000 { |
ad6be7d1 | 43 | compatible = "nvidia,tegra124-dc"; |
e30cb238 | 44 | reg = <0x0 0x54240000 0x0 0x00040000>; |
ad6be7d1 TR |
45 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
46 | clocks = <&tegra_car TEGRA124_CLK_DISP2>, | |
47 | <&tegra_car TEGRA124_CLK_PLL_P>; | |
48 | clock-names = "dc", "parent"; | |
49 | resets = <&tegra_car 26>; | |
50 | reset-names = "dc"; | |
51 | ||
52 | nvidia,head = <1>; | |
53 | }; | |
d72be031 | 54 | |
9dd604df TR |
55 | hdmi@0,54280000 { |
56 | compatible = "nvidia,tegra124-hdmi"; | |
57 | reg = <0x0 0x54280000 0x0 0x00040000>; | |
58 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
59 | clocks = <&tegra_car TEGRA124_CLK_HDMI>, | |
60 | <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; | |
61 | clock-names = "hdmi", "parent"; | |
62 | resets = <&tegra_car 51>; | |
63 | reset-names = "hdmi"; | |
64 | status = "disabled"; | |
65 | }; | |
66 | ||
e30cb238 | 67 | sor@0,54540000 { |
d72be031 | 68 | compatible = "nvidia,tegra124-sor"; |
e30cb238 | 69 | reg = <0x0 0x54540000 0x0 0x00040000>; |
d72be031 TR |
70 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
71 | clocks = <&tegra_car TEGRA124_CLK_SOR0>, | |
72 | <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, | |
73 | <&tegra_car TEGRA124_CLK_PLL_DP>, | |
74 | <&tegra_car TEGRA124_CLK_CLK_M>; | |
75 | clock-names = "sor", "parent", "dp", "safe"; | |
76 | resets = <&tegra_car 182>; | |
77 | reset-names = "sor"; | |
78 | status = "disabled"; | |
79 | }; | |
80 | ||
e30cb238 | 81 | dpaux@0,545c0000 { |
d72be031 | 82 | compatible = "nvidia,tegra124-dpaux"; |
e30cb238 | 83 | reg = <0x0 0x545c0000 0x0 0x00040000>; |
d72be031 TR |
84 | interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; |
85 | clocks = <&tegra_car TEGRA124_CLK_DPAUX>, | |
86 | <&tegra_car TEGRA124_CLK_PLL_DP>; | |
87 | clock-names = "dpaux", "parent"; | |
88 | resets = <&tegra_car 181>; | |
89 | reset-names = "dpaux"; | |
90 | status = "disabled"; | |
91 | }; | |
ad6be7d1 TR |
92 | }; |
93 | ||
e30cb238 | 94 | gic: interrupt-controller@0,50041000 { |
ad03b1a7 JL |
95 | compatible = "arm,cortex-a15-gic"; |
96 | #interrupt-cells = <3>; | |
97 | interrupt-controller; | |
e30cb238 SW |
98 | reg = <0x0 0x50041000 0x0 0x1000>, |
99 | <0x0 0x50042000 0x0 0x1000>, | |
100 | <0x0 0x50044000 0x0 0x2000>, | |
101 | <0x0 0x50046000 0x0 0x2000>; | |
ad03b1a7 JL |
102 | interrupts = <GIC_PPI 9 |
103 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
104 | }; | |
105 | ||
d86b1e8d TR |
106 | gpu@0,57000000 { |
107 | compatible = "nvidia,gk20a"; | |
108 | reg = <0x0 0x57000000 0x0 0x01000000>, | |
109 | <0x0 0x58000000 0x0 0x01000000>; | |
110 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, | |
111 | <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; | |
112 | interrupt-names = "stall", "nonstall"; | |
113 | clocks = <&tegra_car TEGRA124_CLK_GPU>, | |
114 | <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; | |
115 | clock-names = "gpu", "pwr"; | |
116 | resets = <&tegra_car 184>; | |
117 | reset-names = "gpu"; | |
118 | status = "disabled"; | |
119 | }; | |
120 | ||
e30cb238 | 121 | timer@0,60005000 { |
ad03b1a7 | 122 | compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; |
e30cb238 | 123 | reg = <0x0 0x60005000 0x0 0x400>; |
ad03b1a7 JL |
124 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
125 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
126 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
127 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
128 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
129 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; | |
3b86baf2 JL |
130 | clocks = <&tegra_car TEGRA124_CLK_TIMER>; |
131 | }; | |
132 | ||
e30cb238 | 133 | tegra_car: clock@0,60006000 { |
3b86baf2 | 134 | compatible = "nvidia,tegra124-car"; |
e30cb238 | 135 | reg = <0x0 0x60006000 0x0 0x1000>; |
3b86baf2 | 136 | #clock-cells = <1>; |
f71e4f03 | 137 | #reset-cells = <1>; |
ad03b1a7 JL |
138 | }; |
139 | ||
e30cb238 | 140 | gpio: gpio@0,6000d000 { |
0a9375d1 | 141 | compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; |
e30cb238 | 142 | reg = <0x0 0x6000d000 0x0 0x1000>; |
0a9375d1 SW |
143 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
144 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
145 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, | |
146 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, | |
147 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
148 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
149 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, | |
150 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; | |
151 | #gpio-cells = <2>; | |
152 | gpio-controller; | |
153 | #interrupt-cells = <2>; | |
154 | interrupt-controller; | |
155 | }; | |
156 | ||
e30cb238 | 157 | apbdma: dma@0,60020000 { |
2f5a913e | 158 | compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; |
e30cb238 | 159 | reg = <0x0 0x60020000 0x0 0x1400>; |
2f5a913e SW |
160 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
161 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
162 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
163 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
164 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
165 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
166 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
167 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
168 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
169 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
170 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
171 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
172 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
173 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
174 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
175 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, | |
176 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, | |
177 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, | |
178 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, | |
179 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
180 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, | |
181 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, | |
182 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
183 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
184 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
185 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, | |
186 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, | |
187 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, | |
188 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, | |
189 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, | |
190 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, | |
191 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
192 | clocks = <&tegra_car TEGRA124_CLK_APBDMA>; | |
193 | resets = <&tegra_car 34>; | |
194 | reset-names = "dma"; | |
195 | #dma-cells = <1>; | |
196 | }; | |
197 | ||
155dfc7b PDS |
198 | apbmisc@0,70000800 { |
199 | compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; | |
200 | reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ | |
201 | <0x0 0x7000E864 0x0 0x04>; /* Strapping options */ | |
202 | }; | |
203 | ||
e30cb238 | 204 | pinmux: pinmux@0,70000868 { |
caefe637 | 205 | compatible = "nvidia,tegra124-pinmux"; |
e30cb238 SW |
206 | reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ |
207 | <0x0 0x70003000 0x0 0x434>; /* Mux registers */ | |
caefe637 SW |
208 | }; |
209 | ||
ad03b1a7 JL |
210 | /* |
211 | * There are two serial driver i.e. 8250 based simple serial | |
212 | * driver and APB DMA based serial driver for higher baudrate | |
213 | * and performace. To enable the 8250 based driver, the compatible | |
214 | * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable | |
215 | * the APB DMA based serial driver, the comptible is | |
216 | * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". | |
217 | */ | |
e30cb238 | 218 | serial@0,70006000 { |
ad03b1a7 | 219 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
e30cb238 | 220 | reg = <0x0 0x70006000 0x0 0x40>; |
ad03b1a7 JL |
221 | reg-shift = <2>; |
222 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
3b86baf2 | 223 | clocks = <&tegra_car TEGRA124_CLK_UARTA>; |
f71e4f03 SW |
224 | resets = <&tegra_car 6>; |
225 | reset-names = "serial"; | |
2f5a913e SW |
226 | dmas = <&apbdma 8>, <&apbdma 8>; |
227 | dma-names = "rx", "tx"; | |
ad03b1a7 JL |
228 | status = "disabled"; |
229 | }; | |
230 | ||
e30cb238 | 231 | serial@0,70006040 { |
ad03b1a7 | 232 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
e30cb238 | 233 | reg = <0x0 0x70006040 0x0 0x40>; |
ad03b1a7 JL |
234 | reg-shift = <2>; |
235 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
3b86baf2 | 236 | clocks = <&tegra_car TEGRA124_CLK_UARTB>; |
f71e4f03 SW |
237 | resets = <&tegra_car 7>; |
238 | reset-names = "serial"; | |
2f5a913e SW |
239 | dmas = <&apbdma 9>, <&apbdma 9>; |
240 | dma-names = "rx", "tx"; | |
ad03b1a7 JL |
241 | status = "disabled"; |
242 | }; | |
243 | ||
e30cb238 | 244 | serial@0,70006200 { |
ad03b1a7 | 245 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
e30cb238 | 246 | reg = <0x0 0x70006200 0x0 0x40>; |
ad03b1a7 JL |
247 | reg-shift = <2>; |
248 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
3b86baf2 | 249 | clocks = <&tegra_car TEGRA124_CLK_UARTC>; |
f71e4f03 SW |
250 | resets = <&tegra_car 55>; |
251 | reset-names = "serial"; | |
2f5a913e SW |
252 | dmas = <&apbdma 10>, <&apbdma 10>; |
253 | dma-names = "rx", "tx"; | |
ad03b1a7 JL |
254 | status = "disabled"; |
255 | }; | |
256 | ||
e30cb238 | 257 | serial@0,70006300 { |
ad03b1a7 | 258 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
e30cb238 | 259 | reg = <0x0 0x70006300 0x0 0x40>; |
ad03b1a7 JL |
260 | reg-shift = <2>; |
261 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; | |
3b86baf2 | 262 | clocks = <&tegra_car TEGRA124_CLK_UARTD>; |
f71e4f03 SW |
263 | resets = <&tegra_car 65>; |
264 | reset-names = "serial"; | |
2f5a913e SW |
265 | dmas = <&apbdma 19>, <&apbdma 19>; |
266 | dma-names = "rx", "tx"; | |
ad03b1a7 JL |
267 | status = "disabled"; |
268 | }; | |
269 | ||
e30cb238 | 270 | pwm@0,7000a000 { |
111a1fc2 | 271 | compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; |
e30cb238 | 272 | reg = <0x0 0x7000a000 0x0 0x100>; |
111a1fc2 TR |
273 | #pwm-cells = <2>; |
274 | clocks = <&tegra_car TEGRA124_CLK_PWM>; | |
275 | resets = <&tegra_car 17>; | |
276 | reset-names = "pwm"; | |
277 | status = "disabled"; | |
278 | }; | |
279 | ||
e30cb238 | 280 | i2c@0,7000c000 { |
4f607460 | 281 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
e30cb238 | 282 | reg = <0x0 0x7000c000 0x0 0x100>; |
4f607460 SW |
283 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
284 | #address-cells = <1>; | |
285 | #size-cells = <0>; | |
286 | clocks = <&tegra_car TEGRA124_CLK_I2C1>; | |
287 | clock-names = "div-clk"; | |
288 | resets = <&tegra_car 12>; | |
289 | reset-names = "i2c"; | |
290 | dmas = <&apbdma 21>, <&apbdma 21>; | |
291 | dma-names = "rx", "tx"; | |
292 | status = "disabled"; | |
293 | }; | |
294 | ||
e30cb238 | 295 | i2c@0,7000c400 { |
4f607460 | 296 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
e30cb238 | 297 | reg = <0x0 0x7000c400 0x0 0x100>; |
4f607460 SW |
298 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
299 | #address-cells = <1>; | |
300 | #size-cells = <0>; | |
301 | clocks = <&tegra_car TEGRA124_CLK_I2C2>; | |
302 | clock-names = "div-clk"; | |
303 | resets = <&tegra_car 54>; | |
304 | reset-names = "i2c"; | |
305 | dmas = <&apbdma 22>, <&apbdma 22>; | |
306 | dma-names = "rx", "tx"; | |
307 | status = "disabled"; | |
308 | }; | |
309 | ||
e30cb238 | 310 | i2c@0,7000c500 { |
4f607460 | 311 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
e30cb238 | 312 | reg = <0x0 0x7000c500 0x0 0x100>; |
4f607460 SW |
313 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
314 | #address-cells = <1>; | |
315 | #size-cells = <0>; | |
316 | clocks = <&tegra_car TEGRA124_CLK_I2C3>; | |
317 | clock-names = "div-clk"; | |
318 | resets = <&tegra_car 67>; | |
319 | reset-names = "i2c"; | |
320 | dmas = <&apbdma 23>, <&apbdma 23>; | |
321 | dma-names = "rx", "tx"; | |
322 | status = "disabled"; | |
323 | }; | |
324 | ||
e30cb238 | 325 | i2c@0,7000c700 { |
4f607460 | 326 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
e30cb238 | 327 | reg = <0x0 0x7000c700 0x0 0x100>; |
4f607460 SW |
328 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
329 | #address-cells = <1>; | |
330 | #size-cells = <0>; | |
331 | clocks = <&tegra_car TEGRA124_CLK_I2C4>; | |
332 | clock-names = "div-clk"; | |
333 | resets = <&tegra_car 103>; | |
334 | reset-names = "i2c"; | |
335 | dmas = <&apbdma 26>, <&apbdma 26>; | |
336 | dma-names = "rx", "tx"; | |
337 | status = "disabled"; | |
338 | }; | |
339 | ||
e30cb238 | 340 | i2c@0,7000d000 { |
4f607460 | 341 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
e30cb238 | 342 | reg = <0x0 0x7000d000 0x0 0x100>; |
4f607460 SW |
343 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
344 | #address-cells = <1>; | |
345 | #size-cells = <0>; | |
346 | clocks = <&tegra_car TEGRA124_CLK_I2C5>; | |
347 | clock-names = "div-clk"; | |
348 | resets = <&tegra_car 47>; | |
349 | reset-names = "i2c"; | |
350 | dmas = <&apbdma 24>, <&apbdma 24>; | |
351 | dma-names = "rx", "tx"; | |
352 | status = "disabled"; | |
353 | }; | |
354 | ||
e30cb238 | 355 | i2c@0,7000d100 { |
4f607460 | 356 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
e30cb238 | 357 | reg = <0x0 0x7000d100 0x0 0x100>; |
4f607460 SW |
358 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
359 | #address-cells = <1>; | |
360 | #size-cells = <0>; | |
361 | clocks = <&tegra_car TEGRA124_CLK_I2C6>; | |
362 | clock-names = "div-clk"; | |
363 | resets = <&tegra_car 166>; | |
364 | reset-names = "i2c"; | |
365 | dmas = <&apbdma 30>, <&apbdma 30>; | |
366 | dma-names = "rx", "tx"; | |
367 | status = "disabled"; | |
368 | }; | |
369 | ||
e30cb238 | 370 | spi@0,7000d400 { |
9f1ac560 | 371 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
e30cb238 | 372 | reg = <0x0 0x7000d400 0x0 0x200>; |
9f1ac560 TR |
373 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
374 | #address-cells = <1>; | |
375 | #size-cells = <0>; | |
376 | clocks = <&tegra_car TEGRA124_CLK_SBC1>; | |
377 | clock-names = "spi"; | |
378 | resets = <&tegra_car 41>; | |
379 | reset-names = "spi"; | |
380 | dmas = <&apbdma 15>, <&apbdma 15>; | |
381 | dma-names = "rx", "tx"; | |
382 | status = "disabled"; | |
383 | }; | |
384 | ||
e30cb238 | 385 | spi@0,7000d600 { |
9f1ac560 | 386 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
e30cb238 | 387 | reg = <0x0 0x7000d600 0x0 0x200>; |
9f1ac560 TR |
388 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
389 | #address-cells = <1>; | |
390 | #size-cells = <0>; | |
391 | clocks = <&tegra_car TEGRA124_CLK_SBC2>; | |
392 | clock-names = "spi"; | |
393 | resets = <&tegra_car 44>; | |
394 | reset-names = "spi"; | |
395 | dmas = <&apbdma 16>, <&apbdma 16>; | |
396 | dma-names = "rx", "tx"; | |
397 | status = "disabled"; | |
398 | }; | |
399 | ||
e30cb238 | 400 | spi@0,7000d800 { |
9f1ac560 | 401 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
e30cb238 | 402 | reg = <0x0 0x7000d800 0x0 0x200>; |
9f1ac560 TR |
403 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
404 | #address-cells = <1>; | |
405 | #size-cells = <0>; | |
406 | clocks = <&tegra_car TEGRA124_CLK_SBC3>; | |
407 | clock-names = "spi"; | |
408 | resets = <&tegra_car 46>; | |
409 | reset-names = "spi"; | |
410 | dmas = <&apbdma 17>, <&apbdma 17>; | |
411 | dma-names = "rx", "tx"; | |
412 | status = "disabled"; | |
413 | }; | |
414 | ||
e30cb238 | 415 | spi@0,7000da00 { |
9f1ac560 | 416 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
e30cb238 | 417 | reg = <0x0 0x7000da00 0x0 0x200>; |
9f1ac560 TR |
418 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
419 | #address-cells = <1>; | |
420 | #size-cells = <0>; | |
421 | clocks = <&tegra_car TEGRA124_CLK_SBC4>; | |
422 | clock-names = "spi"; | |
423 | resets = <&tegra_car 68>; | |
424 | reset-names = "spi"; | |
425 | dmas = <&apbdma 18>, <&apbdma 18>; | |
426 | dma-names = "rx", "tx"; | |
427 | status = "disabled"; | |
428 | }; | |
429 | ||
e30cb238 | 430 | spi@0,7000dc00 { |
9f1ac560 | 431 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
e30cb238 | 432 | reg = <0x0 0x7000dc00 0x0 0x200>; |
9f1ac560 TR |
433 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
434 | #address-cells = <1>; | |
435 | #size-cells = <0>; | |
436 | clocks = <&tegra_car TEGRA124_CLK_SBC5>; | |
437 | clock-names = "spi"; | |
438 | resets = <&tegra_car 104>; | |
439 | reset-names = "spi"; | |
440 | dmas = <&apbdma 27>, <&apbdma 27>; | |
441 | dma-names = "rx", "tx"; | |
442 | status = "disabled"; | |
443 | }; | |
444 | ||
e30cb238 | 445 | spi@0,7000de00 { |
9f1ac560 | 446 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
e30cb238 | 447 | reg = <0x0 0x7000de00 0x0 0x200>; |
9f1ac560 TR |
448 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
449 | #address-cells = <1>; | |
450 | #size-cells = <0>; | |
451 | clocks = <&tegra_car TEGRA124_CLK_SBC6>; | |
452 | clock-names = "spi"; | |
453 | resets = <&tegra_car 105>; | |
454 | reset-names = "spi"; | |
455 | dmas = <&apbdma 28>, <&apbdma 28>; | |
456 | dma-names = "rx", "tx"; | |
457 | status = "disabled"; | |
458 | }; | |
459 | ||
e30cb238 | 460 | rtc@0,7000e000 { |
ad03b1a7 | 461 | compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; |
e30cb238 | 462 | reg = <0x0 0x7000e000 0x0 0x100>; |
ad03b1a7 | 463 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
3b86baf2 | 464 | clocks = <&tegra_car TEGRA124_CLK_RTC>; |
ad03b1a7 JL |
465 | }; |
466 | ||
e30cb238 | 467 | pmc@0,7000e400 { |
ad03b1a7 | 468 | compatible = "nvidia,tegra124-pmc"; |
e30cb238 | 469 | reg = <0x0 0x7000e400 0x0 0x400>; |
3b86baf2 JL |
470 | clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; |
471 | clock-names = "pclk", "clk32k_in"; | |
ad03b1a7 JL |
472 | }; |
473 | ||
155dfc7b PDS |
474 | fuse@0,7000f800 { |
475 | compatible = "nvidia,tegra124-efuse"; | |
476 | reg = <0x0 0x7000f800 0x0 0x400>; | |
477 | clocks = <&tegra_car TEGRA124_CLK_FUSE>; | |
478 | clock-names = "fuse"; | |
479 | resets = <&tegra_car 39>; | |
480 | reset-names = "fuse"; | |
481 | }; | |
482 | ||
6389cb3b DR |
483 | hda@0,70030000 { |
484 | compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; | |
485 | reg = <0x0 0x70030000 0x0 0x10000>; | |
486 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
487 | clocks = <&tegra_car TEGRA124_CLK_HDA>, | |
488 | <&tegra_car TEGRA124_CLK_HDA2HDMI>, | |
489 | <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; | |
490 | clock-names = "hda", "hda2hdmi", "hdacodec_2x"; | |
491 | resets = <&tegra_car 125>, /* hda */ | |
492 | <&tegra_car 128>, /* hda2hdmi */ | |
493 | <&tegra_car 111>; /* hda2codec_2x */ | |
494 | reset-names = "hda", "hda2hdmi", "hdacodec_2x"; | |
495 | status = "disabled"; | |
496 | }; | |
497 | ||
ce90d32d TR |
498 | padctl: padctl@0,7009f000 { |
499 | compatible = "nvidia,tegra124-xusb-padctl"; | |
500 | reg = <0x0 0x7009f000 0x0 0x1000>; | |
501 | resets = <&tegra_car 142>; | |
502 | reset-names = "padctl"; | |
503 | ||
504 | #phy-cells = <1>; | |
505 | }; | |
506 | ||
e30cb238 | 507 | sdhci@0,700b0000 { |
784c7444 | 508 | compatible = "nvidia,tegra124-sdhci"; |
e30cb238 | 509 | reg = <0x0 0x700b0000 0x0 0x200>; |
784c7444 SW |
510 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
511 | clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; | |
512 | resets = <&tegra_car 14>; | |
513 | reset-names = "sdhci"; | |
e2b6d77e | 514 | status = "disabled"; |
784c7444 SW |
515 | }; |
516 | ||
e30cb238 | 517 | sdhci@0,700b0200 { |
784c7444 | 518 | compatible = "nvidia,tegra124-sdhci"; |
e30cb238 | 519 | reg = <0x0 0x700b0200 0x0 0x200>; |
784c7444 SW |
520 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
521 | clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; | |
522 | resets = <&tegra_car 9>; | |
523 | reset-names = "sdhci"; | |
e2b6d77e | 524 | status = "disabled"; |
784c7444 SW |
525 | }; |
526 | ||
e30cb238 | 527 | sdhci@0,700b0400 { |
784c7444 | 528 | compatible = "nvidia,tegra124-sdhci"; |
e30cb238 | 529 | reg = <0x0 0x700b0400 0x0 0x200>; |
784c7444 SW |
530 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
531 | clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; | |
532 | resets = <&tegra_car 69>; | |
533 | reset-names = "sdhci"; | |
e2b6d77e | 534 | status = "disabled"; |
784c7444 SW |
535 | }; |
536 | ||
e30cb238 | 537 | sdhci@0,700b0600 { |
784c7444 | 538 | compatible = "nvidia,tegra124-sdhci"; |
e30cb238 | 539 | reg = <0x0 0x700b0600 0x0 0x200>; |
784c7444 SW |
540 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
541 | clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; | |
542 | resets = <&tegra_car 15>; | |
543 | reset-names = "sdhci"; | |
e2b6d77e | 544 | status = "disabled"; |
784c7444 SW |
545 | }; |
546 | ||
e30cb238 | 547 | ahub@0,70300000 { |
e6655578 | 548 | compatible = "nvidia,tegra124-ahub"; |
e30cb238 SW |
549 | reg = <0x0 0x70300000 0x0 0x200>, |
550 | <0x0 0x70300800 0x0 0x800>, | |
551 | <0x0 0x70300200 0x0 0x600>; | |
e6655578 SW |
552 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
553 | clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, | |
554 | <&tegra_car TEGRA124_CLK_APBIF>; | |
555 | clock-names = "d_audio", "apbif"; | |
556 | resets = <&tegra_car 106>, /* d_audio */ | |
557 | <&tegra_car 107>, /* apbif */ | |
558 | <&tegra_car 30>, /* i2s0 */ | |
559 | <&tegra_car 11>, /* i2s1 */ | |
560 | <&tegra_car 18>, /* i2s2 */ | |
561 | <&tegra_car 101>, /* i2s3 */ | |
562 | <&tegra_car 102>, /* i2s4 */ | |
563 | <&tegra_car 108>, /* dam0 */ | |
564 | <&tegra_car 109>, /* dam1 */ | |
565 | <&tegra_car 110>, /* dam2 */ | |
566 | <&tegra_car 10>, /* spdif */ | |
567 | <&tegra_car 153>, /* amx */ | |
568 | <&tegra_car 185>, /* amx1 */ | |
569 | <&tegra_car 154>, /* adx */ | |
570 | <&tegra_car 180>, /* adx1 */ | |
571 | <&tegra_car 186>, /* afc0 */ | |
572 | <&tegra_car 187>, /* afc1 */ | |
573 | <&tegra_car 188>, /* afc2 */ | |
574 | <&tegra_car 189>, /* afc3 */ | |
575 | <&tegra_car 190>, /* afc4 */ | |
576 | <&tegra_car 191>; /* afc5 */ | |
577 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", | |
578 | "i2s3", "i2s4", "dam0", "dam1", "dam2", | |
579 | "spdif", "amx", "amx1", "adx", "adx1", | |
580 | "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; | |
581 | dmas = <&apbdma 1>, <&apbdma 1>, | |
582 | <&apbdma 2>, <&apbdma 2>, | |
583 | <&apbdma 3>, <&apbdma 3>, | |
584 | <&apbdma 4>, <&apbdma 4>, | |
585 | <&apbdma 6>, <&apbdma 6>, | |
586 | <&apbdma 7>, <&apbdma 7>, | |
587 | <&apbdma 12>, <&apbdma 12>, | |
588 | <&apbdma 13>, <&apbdma 13>, | |
589 | <&apbdma 14>, <&apbdma 14>, | |
590 | <&apbdma 29>, <&apbdma 29>; | |
591 | dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", | |
592 | "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", | |
593 | "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", | |
594 | "rx9", "tx9"; | |
595 | ranges; | |
e30cb238 SW |
596 | #address-cells = <2>; |
597 | #size-cells = <2>; | |
e6655578 | 598 | |
e30cb238 | 599 | tegra_i2s0: i2s@0,70301000 { |
e6655578 | 600 | compatible = "nvidia,tegra124-i2s"; |
e30cb238 | 601 | reg = <0x0 0x70301000 0x0 0x100>; |
e6655578 SW |
602 | nvidia,ahub-cif-ids = <4 4>; |
603 | clocks = <&tegra_car TEGRA124_CLK_I2S0>; | |
604 | resets = <&tegra_car 30>; | |
605 | reset-names = "i2s"; | |
606 | status = "disabled"; | |
607 | }; | |
608 | ||
e30cb238 | 609 | tegra_i2s1: i2s@0,70301100 { |
e6655578 | 610 | compatible = "nvidia,tegra124-i2s"; |
e30cb238 | 611 | reg = <0x0 0x70301100 0x0 0x100>; |
e6655578 SW |
612 | nvidia,ahub-cif-ids = <5 5>; |
613 | clocks = <&tegra_car TEGRA124_CLK_I2S1>; | |
614 | resets = <&tegra_car 11>; | |
615 | reset-names = "i2s"; | |
616 | status = "disabled"; | |
617 | }; | |
618 | ||
e30cb238 | 619 | tegra_i2s2: i2s@0,70301200 { |
e6655578 | 620 | compatible = "nvidia,tegra124-i2s"; |
e30cb238 | 621 | reg = <0x0 0x70301200 0x0 0x100>; |
e6655578 SW |
622 | nvidia,ahub-cif-ids = <6 6>; |
623 | clocks = <&tegra_car TEGRA124_CLK_I2S2>; | |
624 | resets = <&tegra_car 18>; | |
625 | reset-names = "i2s"; | |
626 | status = "disabled"; | |
627 | }; | |
628 | ||
e30cb238 | 629 | tegra_i2s3: i2s@0,70301300 { |
e6655578 | 630 | compatible = "nvidia,tegra124-i2s"; |
e30cb238 | 631 | reg = <0x0 0x70301300 0x0 0x100>; |
e6655578 SW |
632 | nvidia,ahub-cif-ids = <7 7>; |
633 | clocks = <&tegra_car TEGRA124_CLK_I2S3>; | |
634 | resets = <&tegra_car 101>; | |
635 | reset-names = "i2s"; | |
636 | status = "disabled"; | |
637 | }; | |
638 | ||
e30cb238 | 639 | tegra_i2s4: i2s@0,70301400 { |
e6655578 | 640 | compatible = "nvidia,tegra124-i2s"; |
e30cb238 | 641 | reg = <0x0 0x70301400 0x0 0x100>; |
e6655578 SW |
642 | nvidia,ahub-cif-ids = <8 8>; |
643 | clocks = <&tegra_car TEGRA124_CLK_I2S4>; | |
644 | resets = <&tegra_car 102>; | |
645 | reset-names = "i2s"; | |
646 | status = "disabled"; | |
647 | }; | |
648 | }; | |
649 | ||
e30cb238 | 650 | usb@0,7d000000 { |
f2d50158 | 651 | compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; |
e30cb238 | 652 | reg = <0x0 0x7d000000 0x0 0x4000>; |
f2d50158 TR |
653 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
654 | phy_type = "utmi"; | |
655 | clocks = <&tegra_car TEGRA124_CLK_USBD>; | |
656 | resets = <&tegra_car 22>; | |
657 | reset-names = "usb"; | |
658 | nvidia,phy = <&phy1>; | |
659 | status = "disabled"; | |
660 | }; | |
661 | ||
e30cb238 | 662 | phy1: usb-phy@0,7d000000 { |
f2d50158 | 663 | compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; |
e30cb238 SW |
664 | reg = <0x0 0x7d000000 0x0 0x4000>, |
665 | <0x0 0x7d000000 0x0 0x4000>; | |
f2d50158 TR |
666 | phy_type = "utmi"; |
667 | clocks = <&tegra_car TEGRA124_CLK_USBD>, | |
668 | <&tegra_car TEGRA124_CLK_PLL_U>, | |
669 | <&tegra_car TEGRA124_CLK_USBD>; | |
670 | clock-names = "reg", "pll_u", "utmi-pads"; | |
308efde2 TT |
671 | resets = <&tegra_car 59>, <&tegra_car 22>; |
672 | reset-names = "usb", "utmi-pads"; | |
f2d50158 TR |
673 | nvidia,hssync-start-delay = <0>; |
674 | nvidia,idle-wait-delay = <17>; | |
675 | nvidia,elastic-limit = <16>; | |
676 | nvidia,term-range-adj = <6>; | |
677 | nvidia,xcvr-setup = <9>; | |
678 | nvidia,xcvr-lsfslew = <0>; | |
679 | nvidia,xcvr-lsrslew = <3>; | |
680 | nvidia,hssquelch-level = <2>; | |
681 | nvidia,hsdiscon-level = <5>; | |
682 | nvidia,xcvr-hsslew = <12>; | |
683 | status = "disabled"; | |
684 | }; | |
685 | ||
e30cb238 | 686 | usb@0,7d004000 { |
f2d50158 | 687 | compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; |
e30cb238 | 688 | reg = <0x0 0x7d004000 0x0 0x4000>; |
f2d50158 TR |
689 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
690 | phy_type = "utmi"; | |
691 | clocks = <&tegra_car TEGRA124_CLK_USB2>; | |
692 | resets = <&tegra_car 58>; | |
693 | reset-names = "usb"; | |
694 | nvidia,phy = <&phy2>; | |
695 | status = "disabled"; | |
696 | }; | |
697 | ||
e30cb238 | 698 | phy2: usb-phy@0,7d004000 { |
f2d50158 | 699 | compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; |
e30cb238 SW |
700 | reg = <0x0 0x7d004000 0x0 0x4000>, |
701 | <0x0 0x7d000000 0x0 0x4000>; | |
f2d50158 TR |
702 | phy_type = "utmi"; |
703 | clocks = <&tegra_car TEGRA124_CLK_USB2>, | |
704 | <&tegra_car TEGRA124_CLK_PLL_U>, | |
705 | <&tegra_car TEGRA124_CLK_USBD>; | |
706 | clock-names = "reg", "pll_u", "utmi-pads"; | |
308efde2 TT |
707 | resets = <&tegra_car 22>, <&tegra_car 22>; |
708 | reset-names = "usb", "utmi-pads"; | |
f2d50158 TR |
709 | nvidia,hssync-start-delay = <0>; |
710 | nvidia,idle-wait-delay = <17>; | |
711 | nvidia,elastic-limit = <16>; | |
712 | nvidia,term-range-adj = <6>; | |
713 | nvidia,xcvr-setup = <9>; | |
714 | nvidia,xcvr-lsfslew = <0>; | |
715 | nvidia,xcvr-lsrslew = <3>; | |
716 | nvidia,hssquelch-level = <2>; | |
717 | nvidia,hsdiscon-level = <5>; | |
718 | nvidia,xcvr-hsslew = <12>; | |
308efde2 | 719 | nvidia,has-utmi-pad-registers; |
f2d50158 TR |
720 | status = "disabled"; |
721 | }; | |
722 | ||
e30cb238 | 723 | usb@0,7d008000 { |
f2d50158 | 724 | compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; |
e30cb238 | 725 | reg = <0x0 0x7d008000 0x0 0x4000>; |
f2d50158 TR |
726 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
727 | phy_type = "utmi"; | |
728 | clocks = <&tegra_car TEGRA124_CLK_USB3>; | |
729 | resets = <&tegra_car 59>; | |
730 | reset-names = "usb"; | |
731 | nvidia,phy = <&phy3>; | |
732 | status = "disabled"; | |
733 | }; | |
734 | ||
e30cb238 | 735 | phy3: usb-phy@0,7d008000 { |
f2d50158 | 736 | compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; |
e30cb238 SW |
737 | reg = <0x0 0x7d008000 0x0 0x4000>, |
738 | <0x0 0x7d000000 0x0 0x4000>; | |
f2d50158 TR |
739 | phy_type = "utmi"; |
740 | clocks = <&tegra_car TEGRA124_CLK_USB3>, | |
741 | <&tegra_car TEGRA124_CLK_PLL_U>, | |
742 | <&tegra_car TEGRA124_CLK_USBD>; | |
743 | clock-names = "reg", "pll_u", "utmi-pads"; | |
308efde2 TT |
744 | resets = <&tegra_car 58>, <&tegra_car 22>; |
745 | reset-names = "usb", "utmi-pads"; | |
f2d50158 TR |
746 | nvidia,hssync-start-delay = <0>; |
747 | nvidia,idle-wait-delay = <17>; | |
748 | nvidia,elastic-limit = <16>; | |
749 | nvidia,term-range-adj = <6>; | |
750 | nvidia,xcvr-setup = <9>; | |
751 | nvidia,xcvr-lsfslew = <0>; | |
752 | nvidia,xcvr-lsrslew = <3>; | |
753 | nvidia,hssquelch-level = <2>; | |
754 | nvidia,hsdiscon-level = <5>; | |
755 | nvidia,xcvr-hsslew = <12>; | |
756 | status = "disabled"; | |
757 | }; | |
758 | ||
ad03b1a7 JL |
759 | cpus { |
760 | #address-cells = <1>; | |
761 | #size-cells = <0>; | |
762 | ||
763 | cpu@0 { | |
764 | device_type = "cpu"; | |
765 | compatible = "arm,cortex-a15"; | |
766 | reg = <0>; | |
767 | }; | |
768 | ||
769 | cpu@1 { | |
770 | device_type = "cpu"; | |
771 | compatible = "arm,cortex-a15"; | |
772 | reg = <1>; | |
773 | }; | |
774 | ||
775 | cpu@2 { | |
776 | device_type = "cpu"; | |
777 | compatible = "arm,cortex-a15"; | |
778 | reg = <2>; | |
779 | }; | |
780 | ||
781 | cpu@3 { | |
782 | device_type = "cpu"; | |
783 | compatible = "arm,cortex-a15"; | |
784 | reg = <3>; | |
785 | }; | |
786 | }; | |
787 | ||
788 | timer { | |
789 | compatible = "arm,armv7-timer"; | |
790 | interrupts = <GIC_PPI 13 | |
791 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
792 | <GIC_PPI 14 | |
793 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
794 | <GIC_PPI 11 | |
795 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
796 | <GIC_PPI 10 | |
797 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
798 | }; | |
799 | }; |