projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 3b86baf2 | 1 | #include <dt-bindings/clock/tegra124-car.h> |
| 0a9375d1 | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
| 5b605d44 | 3 | #include <dt-bindings/memory/tegra124-mc.h> |
| 4b20bcbe | 4 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
| ce90d32d | 5 | #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> |
| ad03b1a7 | 6 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| bf9d0267 | 7 | #include <dt-bindings/reset/tegra124-car.h> |
| 26b76f80 | 8 | #include <dt-bindings/thermal/tegra124-soctherm.h> |
| ad03b1a7 JL |
9 | |
| 10 | #include "skeleton.dtsi" | |
| 11 | ||
| 12 | / { | |
| 13 | compatible = "nvidia,tegra124"; | |
| 870c81a4 | 14 | interrupt-parent = <&lic>; |
| e30cb238 SW |
15 | #address-cells = <2>; |
| 16 | #size-cells = <2>; | |
| ad03b1a7 | 17 | |
| ee588e2a TR |
18 | pcie-controller@0,01003000 { |
| 19 | compatible = "nvidia,tegra124-pcie"; | |
| 20 | device_type = "pci"; | |
| 21 | reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ | |
| 22 | 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ | |
| 23 | 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ | |
| 24 | reg-names = "pads", "afi", "cs"; | |
| 25 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ | |
| 26 | <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ | |
| 27 | interrupt-names = "intr", "msi"; | |
| 28 | ||
| 29 | #interrupt-cells = <1>; | |
| 30 | interrupt-map-mask = <0 0 0 0>; | |
| 31 | interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
| 32 | ||
| 33 | bus-range = <0x00 0xff>; | |
| 34 | #address-cells = <3>; | |
| 35 | #size-cells = <2>; | |
| 36 | ||
| 37 | ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ | |
| 38 | 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ | |
| 39 | 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ | |
| 40 | 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ | |
| 41 | 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ | |
| 42 | ||
| 43 | clocks = <&tegra_car TEGRA124_CLK_PCIE>, | |
| 44 | <&tegra_car TEGRA124_CLK_AFI>, | |
| 45 | <&tegra_car TEGRA124_CLK_PLL_E>, | |
| 46 | <&tegra_car TEGRA124_CLK_CML0>; | |
| 47 | clock-names = "pex", "afi", "pll_e", "cml"; | |
| 48 | resets = <&tegra_car 70>, | |
| 49 | <&tegra_car 72>, | |
| 50 | <&tegra_car 74>; | |
| 51 | reset-names = "pex", "afi", "pcie_x"; | |
| 52 | status = "disabled"; | |
| 53 | ||
| 54 | phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; | |
| 55 | phy-names = "pcie"; | |
| 56 | ||
| 57 | pci@1,0 { | |
| 58 | device_type = "pci"; | |
| 59 | assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; | |
| 60 | reg = <0x000800 0 0 0 0>; | |
| 61 | status = "disabled"; | |
| 62 | ||
| 63 | #address-cells = <3>; | |
| 64 | #size-cells = <2>; | |
| 65 | ranges; | |
| 66 | ||
| 67 | nvidia,num-lanes = <2>; | |
| 68 | }; | |
| 69 | ||
| 70 | pci@2,0 { | |
| 71 | device_type = "pci"; | |
| 72 | assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; | |
| 73 | reg = <0x001000 0 0 0 0>; | |
| 74 | status = "disabled"; | |
| 75 | ||
| 76 | #address-cells = <3>; | |
| 77 | #size-cells = <2>; | |
| 78 | ranges; | |
| 79 | ||
| 80 | nvidia,num-lanes = <1>; | |
| 81 | }; | |
| 82 | }; | |
| 83 | ||
| e30cb238 | 84 | host1x@0,50000000 { |
| ad6be7d1 | 85 | compatible = "nvidia,tegra124-host1x", "simple-bus"; |
| e30cb238 | 86 | reg = <0x0 0x50000000 0x0 0x00034000>; |
| ad6be7d1 TR |
87 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
| 88 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ | |
| 89 | clocks = <&tegra_car TEGRA124_CLK_HOST1X>; | |
| 90 | resets = <&tegra_car 28>; | |
| 91 | reset-names = "host1x"; | |
| 92 | ||
| e30cb238 SW |
93 | #address-cells = <2>; |
| 94 | #size-cells = <2>; | |
| ad6be7d1 | 95 | |
| e30cb238 | 96 | ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; |
| ad6be7d1 | 97 | |
| e30cb238 | 98 | dc@0,54200000 { |
| ad6be7d1 | 99 | compatible = "nvidia,tegra124-dc"; |
| e30cb238 | 100 | reg = <0x0 0x54200000 0x0 0x00040000>; |
| ad6be7d1 TR |
101 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 102 | clocks = <&tegra_car TEGRA124_CLK_DISP1>, | |
| 103 | <&tegra_car TEGRA124_CLK_PLL_P>; | |
| 104 | clock-names = "dc", "parent"; | |
| 105 | resets = <&tegra_car 27>; | |
| 106 | reset-names = "dc"; | |
| 107 | ||
| 5b605d44 TR |
108 | iommus = <&mc TEGRA_SWGROUP_DC>; |
| 109 | ||
| ad6be7d1 TR |
110 | nvidia,head = <0>; |
| 111 | }; | |
| 112 | ||
| e30cb238 | 113 | dc@0,54240000 { |
| ad6be7d1 | 114 | compatible = "nvidia,tegra124-dc"; |
| e30cb238 | 115 | reg = <0x0 0x54240000 0x0 0x00040000>; |
| ad6be7d1 TR |
116 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 117 | clocks = <&tegra_car TEGRA124_CLK_DISP2>, | |
| 118 | <&tegra_car TEGRA124_CLK_PLL_P>; | |
| 119 | clock-names = "dc", "parent"; | |
| 120 | resets = <&tegra_car 26>; | |
| 121 | reset-names = "dc"; | |
| 122 | ||
| 5b605d44 TR |
123 | iommus = <&mc TEGRA_SWGROUP_DCB>; |
| 124 | ||
| ad6be7d1 TR |
125 | nvidia,head = <1>; |
| 126 | }; | |
| d72be031 | 127 | |
| 9dd604df TR |
128 | hdmi@0,54280000 { |
| 129 | compatible = "nvidia,tegra124-hdmi"; | |
| 130 | reg = <0x0 0x54280000 0x0 0x00040000>; | |
| 131 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
| 132 | clocks = <&tegra_car TEGRA124_CLK_HDMI>, | |
| 133 | <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; | |
| 134 | clock-names = "hdmi", "parent"; | |
| 135 | resets = <&tegra_car 51>; | |
| 136 | reset-names = "hdmi"; | |
| 137 | status = "disabled"; | |
| 138 | }; | |
| 139 | ||
| e30cb238 | 140 | sor@0,54540000 { |
| d72be031 | 141 | compatible = "nvidia,tegra124-sor"; |
| e30cb238 | 142 | reg = <0x0 0x54540000 0x0 0x00040000>; |
| d72be031 TR |
143 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 144 | clocks = <&tegra_car TEGRA124_CLK_SOR0>, | |
| 145 | <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, | |
| 146 | <&tegra_car TEGRA124_CLK_PLL_DP>, | |
| 147 | <&tegra_car TEGRA124_CLK_CLK_M>; | |
| 148 | clock-names = "sor", "parent", "dp", "safe"; | |
| 149 | resets = <&tegra_car 182>; | |
| 150 | reset-names = "sor"; | |
| 151 | status = "disabled"; | |
| 152 | }; | |
| 153 | ||
| edfbad06 | 154 | dpaux: dpaux@0,545c0000 { |
| d72be031 | 155 | compatible = "nvidia,tegra124-dpaux"; |
| e30cb238 | 156 | reg = <0x0 0x545c0000 0x0 0x00040000>; |
| d72be031 TR |
157 | interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; |
| 158 | clocks = <&tegra_car TEGRA124_CLK_DPAUX>, | |
| 159 | <&tegra_car TEGRA124_CLK_PLL_DP>; | |
| 160 | clock-names = "dpaux", "parent"; | |
| 161 | resets = <&tegra_car 181>; | |
| 162 | reset-names = "dpaux"; | |
| 163 | status = "disabled"; | |
| 164 | }; | |
| ad6be7d1 TR |
165 | }; |
| 166 | ||
| e30cb238 | 167 | gic: interrupt-controller@0,50041000 { |
| ad03b1a7 JL |
168 | compatible = "arm,cortex-a15-gic"; |
| 169 | #interrupt-cells = <3>; | |
| 170 | interrupt-controller; | |
| e30cb238 SW |
171 | reg = <0x0 0x50041000 0x0 0x1000>, |
| 172 | <0x0 0x50042000 0x0 0x1000>, | |
| 173 | <0x0 0x50044000 0x0 0x2000>, | |
| 174 | <0x0 0x50046000 0x0 0x2000>; | |
| ad03b1a7 JL |
175 | interrupts = <GIC_PPI 9 |
| 176 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
| 870c81a4 | 177 | interrupt-parent = <&gic>; |
| ad03b1a7 JL |
178 | }; |
| 179 | ||
| d86b1e8d TR |
180 | gpu@0,57000000 { |
| 181 | compatible = "nvidia,gk20a"; | |
| 182 | reg = <0x0 0x57000000 0x0 0x01000000>, | |
| 183 | <0x0 0x58000000 0x0 0x01000000>; | |
| 184 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, | |
| 185 | <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; | |
| 186 | interrupt-names = "stall", "nonstall"; | |
| 187 | clocks = <&tegra_car TEGRA124_CLK_GPU>, | |
| 188 | <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; | |
| 189 | clock-names = "gpu", "pwr"; | |
| 190 | resets = <&tegra_car 184>; | |
| 191 | reset-names = "gpu"; | |
| c96cd177 AC |
192 | |
| 193 | iommus = <&mc TEGRA_SWGROUP_GPU>; | |
| 194 | ||
| d86b1e8d TR |
195 | status = "disabled"; |
| 196 | }; | |
| 197 | ||
| 870c81a4 MZ |
198 | lic: interrupt-controller@60004000 { |
| 199 | compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; | |
| 200 | reg = <0x0 0x60004000 0x0 0x100>, | |
| 201 | <0x0 0x60004100 0x0 0x100>, | |
| 202 | <0x0 0x60004200 0x0 0x100>, | |
| 203 | <0x0 0x60004300 0x0 0x100>, | |
| 204 | <0x0 0x60004400 0x0 0x100>; | |
| 205 | interrupt-controller; | |
| 206 | #interrupt-cells = <3>; | |
| 207 | interrupt-parent = <&gic>; | |
| 208 | }; | |
| 209 | ||
| e30cb238 | 210 | timer@0,60005000 { |
| ad03b1a7 | 211 | compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; |
| e30cb238 | 212 | reg = <0x0 0x60005000 0x0 0x400>; |
| ad03b1a7 JL |
213 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 214 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
| 215 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
| 216 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
| 217 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
| 218 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; | |
| 3b86baf2 JL |
219 | clocks = <&tegra_car TEGRA124_CLK_TIMER>; |
| 220 | }; | |
| 221 | ||
| e30cb238 | 222 | tegra_car: clock@0,60006000 { |
| 3b86baf2 | 223 | compatible = "nvidia,tegra124-car"; |
| e30cb238 | 224 | reg = <0x0 0x60006000 0x0 0x1000>; |
| 3b86baf2 | 225 | #clock-cells = <1>; |
| f71e4f03 | 226 | #reset-cells = <1>; |
| b273c887 | 227 | nvidia,external-memory-controller = <&emc>; |
| ad03b1a7 JL |
228 | }; |
| 229 | ||
| b1023134 TR |
230 | flow-controller@0,60007000 { |
| 231 | compatible = "nvidia,tegra124-flowctrl"; | |
| 232 | reg = <0x0 0x60007000 0x0 0x1000>; | |
| 233 | }; | |
| 234 | ||
| c5f8e8ca TV |
235 | actmon@0,6000c800 { |
| 236 | compatible = "nvidia,tegra124-actmon"; | |
| 237 | reg = <0x0 0x6000c800 0x0 0x400>; | |
| 238 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
| 239 | clocks = <&tegra_car TEGRA124_CLK_ACTMON>, | |
| 240 | <&tegra_car TEGRA124_CLK_EMC>; | |
| 241 | clock-names = "actmon", "emc"; | |
| 242 | resets = <&tegra_car 119>; | |
| 243 | reset-names = "actmon"; | |
| 244 | }; | |
| 245 | ||
| e30cb238 | 246 | gpio: gpio@0,6000d000 { |
| 0a9375d1 | 247 | compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; |
| e30cb238 | 248 | reg = <0x0 0x6000d000 0x0 0x1000>; |
| 0a9375d1 SW |
249 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| 250 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
| 251 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, | |
| 252 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, | |
| 253 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
| 254 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
| 255 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, | |
| 256 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; | |
| 257 | #gpio-cells = <2>; | |
| 258 | gpio-controller; | |
| 259 | #interrupt-cells = <2>; | |
| 260 | interrupt-controller; | |
| 17cdddf0 | 261 | gpio-ranges = <&pinmux 0 0 251>; |
| 0a9375d1 SW |
262 | }; |
| 263 | ||
| e30cb238 | 264 | apbdma: dma@0,60020000 { |
| 2f5a913e | 265 | compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; |
| e30cb238 | 266 | reg = <0x0 0x60020000 0x0 0x1400>; |
| 2f5a913e SW |
267 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| 268 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
| 269 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
| 270 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
| 271 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
| 272 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
| 273 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
| 274 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
| 275 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
| 276 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
| 277 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
| 278 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
| 279 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
| 280 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
| 281 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
| 282 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, | |
| 283 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, | |
| 284 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, | |
| 285 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, | |
| 286 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
| 287 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, | |
| 288 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, | |
| 289 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
| 290 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
| 291 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
| 292 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, | |
| 293 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, | |
| 294 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, | |
| 295 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, | |
| 296 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, | |
| 297 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, | |
| 298 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
| 299 | clocks = <&tegra_car TEGRA124_CLK_APBDMA>; | |
| 300 | resets = <&tegra_car 34>; | |
| 301 | reset-names = "dma"; | |
| 302 | #dma-cells = <1>; | |
| 303 | }; | |
| 304 | ||
| 155dfc7b PDS |
305 | apbmisc@0,70000800 { |
| 306 | compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; | |
| 307 | reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ | |
| 5431b0fd | 308 | <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ |
| 155dfc7b PDS |
309 | }; |
| 310 | ||
| e30cb238 | 311 | pinmux: pinmux@0,70000868 { |
| caefe637 | 312 | compatible = "nvidia,tegra124-pinmux"; |
| e30cb238 | 313 | reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ |
| 49727d30 SP |
314 | <0x0 0x70003000 0x0 0x434>, /* Mux registers */ |
| 315 | <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ | |
| caefe637 SW |
316 | }; |
| 317 | ||
| ad03b1a7 JL |
318 | /* |
| 319 | * There are two serial driver i.e. 8250 based simple serial | |
| 320 | * driver and APB DMA based serial driver for higher baudrate | |
| 321 | * and performace. To enable the 8250 based driver, the compatible | |
| 322 | * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable | |
| 323 | * the APB DMA based serial driver, the comptible is | |
| 324 | * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". | |
| 325 | */ | |
| 121a2f6d | 326 | uarta: serial@0,70006000 { |
| ad03b1a7 | 327 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
| e30cb238 | 328 | reg = <0x0 0x70006000 0x0 0x40>; |
| ad03b1a7 JL |
329 | reg-shift = <2>; |
| 330 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
| 3b86baf2 | 331 | clocks = <&tegra_car TEGRA124_CLK_UARTA>; |
| f71e4f03 SW |
332 | resets = <&tegra_car 6>; |
| 333 | reset-names = "serial"; | |
| 2f5a913e SW |
334 | dmas = <&apbdma 8>, <&apbdma 8>; |
| 335 | dma-names = "rx", "tx"; | |
| ad03b1a7 JL |
336 | status = "disabled"; |
| 337 | }; | |
| 338 | ||
| 121a2f6d | 339 | uartb: serial@0,70006040 { |
| ad03b1a7 | 340 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
| e30cb238 | 341 | reg = <0x0 0x70006040 0x0 0x40>; |
| ad03b1a7 JL |
342 | reg-shift = <2>; |
| 343 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
| 3b86baf2 | 344 | clocks = <&tegra_car TEGRA124_CLK_UARTB>; |
| f71e4f03 SW |
345 | resets = <&tegra_car 7>; |
| 346 | reset-names = "serial"; | |
| 2f5a913e SW |
347 | dmas = <&apbdma 9>, <&apbdma 9>; |
| 348 | dma-names = "rx", "tx"; | |
| ad03b1a7 JL |
349 | status = "disabled"; |
| 350 | }; | |
| 351 | ||
| 121a2f6d | 352 | uartc: serial@0,70006200 { |
| ad03b1a7 | 353 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
| e30cb238 | 354 | reg = <0x0 0x70006200 0x0 0x40>; |
| ad03b1a7 JL |
355 | reg-shift = <2>; |
| 356 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
| 3b86baf2 | 357 | clocks = <&tegra_car TEGRA124_CLK_UARTC>; |
| f71e4f03 SW |
358 | resets = <&tegra_car 55>; |
| 359 | reset-names = "serial"; | |
| 2f5a913e SW |
360 | dmas = <&apbdma 10>, <&apbdma 10>; |
| 361 | dma-names = "rx", "tx"; | |
| ad03b1a7 JL |
362 | status = "disabled"; |
| 363 | }; | |
| 364 | ||
| 121a2f6d | 365 | uartd: serial@0,70006300 { |
| ad03b1a7 | 366 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
| e30cb238 | 367 | reg = <0x0 0x70006300 0x0 0x40>; |
| ad03b1a7 JL |
368 | reg-shift = <2>; |
| 369 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; | |
| 3b86baf2 | 370 | clocks = <&tegra_car TEGRA124_CLK_UARTD>; |
| f71e4f03 SW |
371 | resets = <&tegra_car 65>; |
| 372 | reset-names = "serial"; | |
| 2f5a913e SW |
373 | dmas = <&apbdma 19>, <&apbdma 19>; |
| 374 | dma-names = "rx", "tx"; | |
| ad03b1a7 JL |
375 | status = "disabled"; |
| 376 | }; | |
| 377 | ||
| edfbad06 | 378 | pwm: pwm@0,7000a000 { |
| 111a1fc2 | 379 | compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; |
| e30cb238 | 380 | reg = <0x0 0x7000a000 0x0 0x100>; |
| 111a1fc2 TR |
381 | #pwm-cells = <2>; |
| 382 | clocks = <&tegra_car TEGRA124_CLK_PWM>; | |
| 383 | resets = <&tegra_car 17>; | |
| 384 | reset-names = "pwm"; | |
| 385 | status = "disabled"; | |
| 386 | }; | |
| 387 | ||
| e30cb238 | 388 | i2c@0,7000c000 { |
| 4f607460 | 389 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
| e30cb238 | 390 | reg = <0x0 0x7000c000 0x0 0x100>; |
| 4f607460 SW |
391 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| 392 | #address-cells = <1>; | |
| 393 | #size-cells = <0>; | |
| 394 | clocks = <&tegra_car TEGRA124_CLK_I2C1>; | |
| 395 | clock-names = "div-clk"; | |
| 396 | resets = <&tegra_car 12>; | |
| 397 | reset-names = "i2c"; | |
| 398 | dmas = <&apbdma 21>, <&apbdma 21>; | |
| 399 | dma-names = "rx", "tx"; | |
| 400 | status = "disabled"; | |
| 401 | }; | |
| 402 | ||
| e30cb238 | 403 | i2c@0,7000c400 { |
| 4f607460 | 404 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
| e30cb238 | 405 | reg = <0x0 0x7000c400 0x0 0x100>; |
| 4f607460 SW |
406 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| 407 | #address-cells = <1>; | |
| 408 | #size-cells = <0>; | |
| 409 | clocks = <&tegra_car TEGRA124_CLK_I2C2>; | |
| 410 | clock-names = "div-clk"; | |
| 411 | resets = <&tegra_car 54>; | |
| 412 | reset-names = "i2c"; | |
| 413 | dmas = <&apbdma 22>, <&apbdma 22>; | |
| 414 | dma-names = "rx", "tx"; | |
| 415 | status = "disabled"; | |
| 416 | }; | |
| 417 | ||
| e30cb238 | 418 | i2c@0,7000c500 { |
| 4f607460 | 419 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
| e30cb238 | 420 | reg = <0x0 0x7000c500 0x0 0x100>; |
| 4f607460 SW |
421 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| 422 | #address-cells = <1>; | |
| 423 | #size-cells = <0>; | |
| 424 | clocks = <&tegra_car TEGRA124_CLK_I2C3>; | |
| 425 | clock-names = "div-clk"; | |
| 426 | resets = <&tegra_car 67>; | |
| 427 | reset-names = "i2c"; | |
| 428 | dmas = <&apbdma 23>, <&apbdma 23>; | |
| 429 | dma-names = "rx", "tx"; | |
| 430 | status = "disabled"; | |
| 431 | }; | |
| 432 | ||
| e30cb238 | 433 | i2c@0,7000c700 { |
| 4f607460 | 434 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
| e30cb238 | 435 | reg = <0x0 0x7000c700 0x0 0x100>; |
| 4f607460 SW |
436 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
| 437 | #address-cells = <1>; | |
| 438 | #size-cells = <0>; | |
| 439 | clocks = <&tegra_car TEGRA124_CLK_I2C4>; | |
| 440 | clock-names = "div-clk"; | |
| 441 | resets = <&tegra_car 103>; | |
| 442 | reset-names = "i2c"; | |
| 443 | dmas = <&apbdma 26>, <&apbdma 26>; | |
| 444 | dma-names = "rx", "tx"; | |
| 445 | status = "disabled"; | |
| 446 | }; | |
| 447 | ||
| e30cb238 | 448 | i2c@0,7000d000 { |
| 4f607460 | 449 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
| e30cb238 | 450 | reg = <0x0 0x7000d000 0x0 0x100>; |
| 4f607460 SW |
451 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
| 452 | #address-cells = <1>; | |
| 453 | #size-cells = <0>; | |
| 454 | clocks = <&tegra_car TEGRA124_CLK_I2C5>; | |
| 455 | clock-names = "div-clk"; | |
| 456 | resets = <&tegra_car 47>; | |
| 457 | reset-names = "i2c"; | |
| 458 | dmas = <&apbdma 24>, <&apbdma 24>; | |
| 459 | dma-names = "rx", "tx"; | |
| 460 | status = "disabled"; | |
| 461 | }; | |
| 462 | ||
| e30cb238 | 463 | i2c@0,7000d100 { |
| 4f607460 | 464 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
| e30cb238 | 465 | reg = <0x0 0x7000d100 0x0 0x100>; |
| 4f607460 SW |
466 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
| 467 | #address-cells = <1>; | |
| 468 | #size-cells = <0>; | |
| 469 | clocks = <&tegra_car TEGRA124_CLK_I2C6>; | |
| 470 | clock-names = "div-clk"; | |
| 471 | resets = <&tegra_car 166>; | |
| 472 | reset-names = "i2c"; | |
| 473 | dmas = <&apbdma 30>, <&apbdma 30>; | |
| 474 | dma-names = "rx", "tx"; | |
| 475 | status = "disabled"; | |
| 476 | }; | |
| 477 | ||
| e30cb238 | 478 | spi@0,7000d400 { |
| 9f1ac560 | 479 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
| e30cb238 | 480 | reg = <0x0 0x7000d400 0x0 0x200>; |
| 9f1ac560 TR |
481 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
| 482 | #address-cells = <1>; | |
| 483 | #size-cells = <0>; | |
| 484 | clocks = <&tegra_car TEGRA124_CLK_SBC1>; | |
| 485 | clock-names = "spi"; | |
| 486 | resets = <&tegra_car 41>; | |
| 487 | reset-names = "spi"; | |
| 488 | dmas = <&apbdma 15>, <&apbdma 15>; | |
| 489 | dma-names = "rx", "tx"; | |
| 490 | status = "disabled"; | |
| 491 | }; | |
| 492 | ||
| e30cb238 | 493 | spi@0,7000d600 { |
| 9f1ac560 | 494 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
| e30cb238 | 495 | reg = <0x0 0x7000d600 0x0 0x200>; |
| 9f1ac560 TR |
496 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| 497 | #address-cells = <1>; | |
| 498 | #size-cells = <0>; | |
| 499 | clocks = <&tegra_car TEGRA124_CLK_SBC2>; | |
| 500 | clock-names = "spi"; | |
| 501 | resets = <&tegra_car 44>; | |
| 502 | reset-names = "spi"; | |
| 503 | dmas = <&apbdma 16>, <&apbdma 16>; | |
| 504 | dma-names = "rx", "tx"; | |
| 505 | status = "disabled"; | |
| 506 | }; | |
| 507 | ||
| e30cb238 | 508 | spi@0,7000d800 { |
| 9f1ac560 | 509 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
| e30cb238 | 510 | reg = <0x0 0x7000d800 0x0 0x200>; |
| 9f1ac560 TR |
511 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| 512 | #address-cells = <1>; | |
| 513 | #size-cells = <0>; | |
| 514 | clocks = <&tegra_car TEGRA124_CLK_SBC3>; | |
| 515 | clock-names = "spi"; | |
| 516 | resets = <&tegra_car 46>; | |
| 517 | reset-names = "spi"; | |
| 518 | dmas = <&apbdma 17>, <&apbdma 17>; | |
| 519 | dma-names = "rx", "tx"; | |
| 520 | status = "disabled"; | |
| 521 | }; | |
| 522 | ||
| e30cb238 | 523 | spi@0,7000da00 { |
| 9f1ac560 | 524 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
| e30cb238 | 525 | reg = <0x0 0x7000da00 0x0 0x200>; |
| 9f1ac560 TR |
526 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| 527 | #address-cells = <1>; | |
| 528 | #size-cells = <0>; | |
| 529 | clocks = <&tegra_car TEGRA124_CLK_SBC4>; | |
| 530 | clock-names = "spi"; | |
| 531 | resets = <&tegra_car 68>; | |
| 532 | reset-names = "spi"; | |
| 533 | dmas = <&apbdma 18>, <&apbdma 18>; | |
| 534 | dma-names = "rx", "tx"; | |
| 535 | status = "disabled"; | |
| 536 | }; | |
| 537 | ||
| e30cb238 | 538 | spi@0,7000dc00 { |
| 9f1ac560 | 539 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
| e30cb238 | 540 | reg = <0x0 0x7000dc00 0x0 0x200>; |
| 9f1ac560 TR |
541 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| 542 | #address-cells = <1>; | |
| 543 | #size-cells = <0>; | |
| 544 | clocks = <&tegra_car TEGRA124_CLK_SBC5>; | |
| 545 | clock-names = "spi"; | |
| 546 | resets = <&tegra_car 104>; | |
| 547 | reset-names = "spi"; | |
| 548 | dmas = <&apbdma 27>, <&apbdma 27>; | |
| 549 | dma-names = "rx", "tx"; | |
| 550 | status = "disabled"; | |
| 551 | }; | |
| 552 | ||
| e30cb238 | 553 | spi@0,7000de00 { |
| 9f1ac560 | 554 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
| e30cb238 | 555 | reg = <0x0 0x7000de00 0x0 0x200>; |
| 9f1ac560 TR |
556 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
| 557 | #address-cells = <1>; | |
| 558 | #size-cells = <0>; | |
| 559 | clocks = <&tegra_car TEGRA124_CLK_SBC6>; | |
| 560 | clock-names = "spi"; | |
| 561 | resets = <&tegra_car 105>; | |
| 562 | reset-names = "spi"; | |
| 563 | dmas = <&apbdma 28>, <&apbdma 28>; | |
| 564 | dma-names = "rx", "tx"; | |
| 565 | status = "disabled"; | |
| 566 | }; | |
| 567 | ||
| e30cb238 | 568 | rtc@0,7000e000 { |
| ad03b1a7 | 569 | compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; |
| e30cb238 | 570 | reg = <0x0 0x7000e000 0x0 0x100>; |
| ad03b1a7 | 571 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| 3b86baf2 | 572 | clocks = <&tegra_car TEGRA124_CLK_RTC>; |
| ad03b1a7 JL |
573 | }; |
| 574 | ||
| e30cb238 | 575 | pmc@0,7000e400 { |
| ad03b1a7 | 576 | compatible = "nvidia,tegra124-pmc"; |
| e30cb238 | 577 | reg = <0x0 0x7000e400 0x0 0x400>; |
| 3b86baf2 JL |
578 | clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; |
| 579 | clock-names = "pclk", "clk32k_in"; | |
| ad03b1a7 JL |
580 | }; |
| 581 | ||
| 155dfc7b PDS |
582 | fuse@0,7000f800 { |
| 583 | compatible = "nvidia,tegra124-efuse"; | |
| 584 | reg = <0x0 0x7000f800 0x0 0x400>; | |
| 585 | clocks = <&tegra_car TEGRA124_CLK_FUSE>; | |
| 586 | clock-names = "fuse"; | |
| 587 | resets = <&tegra_car 39>; | |
| 588 | reset-names = "fuse"; | |
| 589 | }; | |
| 590 | ||
| b26ea06b TR |
591 | mc: memory-controller@0,70019000 { |
| 592 | compatible = "nvidia,tegra124-mc"; | |
| 593 | reg = <0x0 0x70019000 0x0 0x1000>; | |
| 594 | clocks = <&tegra_car TEGRA124_CLK_MC>; | |
| 595 | clock-names = "mc"; | |
| 596 | ||
| 597 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
| 598 | ||
| 599 | #iommu-cells = <1>; | |
| 600 | }; | |
| 601 | ||
| b273c887 MP |
602 | emc: emc@0,7001b000 { |
| 603 | compatible = "nvidia,tegra124-emc"; | |
| 604 | reg = <0x0 0x7001b000 0x0 0x1000>; | |
| 605 | ||
| 606 | nvidia,memory-controller = <&mc>; | |
| 607 | }; | |
| 608 | ||
| fdd69096 MP |
609 | sata@0,70020000 { |
| 610 | compatible = "nvidia,tegra124-ahci"; | |
| 611 | ||
| 612 | reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ | |
| 613 | <0x0 0x70020000 0x0 0x7000>; /* SATA */ | |
| 614 | ||
| 615 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
| 616 | ||
| 617 | clocks = <&tegra_car TEGRA124_CLK_SATA>, | |
| 618 | <&tegra_car TEGRA124_CLK_SATA_OOB>, | |
| 619 | <&tegra_car TEGRA124_CLK_CML1>, | |
| 620 | <&tegra_car TEGRA124_CLK_PLL_E>; | |
| 621 | clock-names = "sata", "sata-oob", "cml1", "pll_e"; | |
| 622 | ||
| 623 | resets = <&tegra_car 124>, | |
| 624 | <&tegra_car 123>, | |
| 625 | <&tegra_car 129>; | |
| 626 | reset-names = "sata", "sata-oob", "sata-cold"; | |
| 627 | ||
| 628 | phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; | |
| 629 | phy-names = "sata-phy"; | |
| 630 | ||
| 631 | status = "disabled"; | |
| 632 | }; | |
| 633 | ||
| 6389cb3b DR |
634 | hda@0,70030000 { |
| 635 | compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; | |
| 636 | reg = <0x0 0x70030000 0x0 0x10000>; | |
| 637 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
| 638 | clocks = <&tegra_car TEGRA124_CLK_HDA>, | |
| 639 | <&tegra_car TEGRA124_CLK_HDA2HDMI>, | |
| 640 | <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; | |
| 869bd180 | 641 | clock-names = "hda", "hda2hdmi", "hda2codec_2x"; |
| 6389cb3b DR |
642 | resets = <&tegra_car 125>, /* hda */ |
| 643 | <&tegra_car 128>, /* hda2hdmi */ | |
| 644 | <&tegra_car 111>; /* hda2codec_2x */ | |
| 869bd180 | 645 | reset-names = "hda", "hda2hdmi", "hda2codec_2x"; |
| 6389cb3b DR |
646 | status = "disabled"; |
| 647 | }; | |
| 648 | ||
| ce90d32d TR |
649 | padctl: padctl@0,7009f000 { |
| 650 | compatible = "nvidia,tegra124-xusb-padctl"; | |
| 651 | reg = <0x0 0x7009f000 0x0 0x1000>; | |
| 652 | resets = <&tegra_car 142>; | |
| 653 | reset-names = "padctl"; | |
| 654 | ||
| 655 | #phy-cells = <1>; | |
| 656 | }; | |
| 657 | ||
| e30cb238 | 658 | sdhci@0,700b0000 { |
| 784c7444 | 659 | compatible = "nvidia,tegra124-sdhci"; |
| e30cb238 | 660 | reg = <0x0 0x700b0000 0x0 0x200>; |
| 784c7444 SW |
661 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| 662 | clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; | |
| 663 | resets = <&tegra_car 14>; | |
| 664 | reset-names = "sdhci"; | |
| e2b6d77e | 665 | status = "disabled"; |
| 784c7444 SW |
666 | }; |
| 667 | ||
| e30cb238 | 668 | sdhci@0,700b0200 { |
| 784c7444 | 669 | compatible = "nvidia,tegra124-sdhci"; |
| e30cb238 | 670 | reg = <0x0 0x700b0200 0x0 0x200>; |
| 784c7444 SW |
671 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 672 | clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; | |
| 673 | resets = <&tegra_car 9>; | |
| 674 | reset-names = "sdhci"; | |
| e2b6d77e | 675 | status = "disabled"; |
| 784c7444 SW |
676 | }; |
| 677 | ||
| e30cb238 | 678 | sdhci@0,700b0400 { |
| 784c7444 | 679 | compatible = "nvidia,tegra124-sdhci"; |
| e30cb238 | 680 | reg = <0x0 0x700b0400 0x0 0x200>; |
| 784c7444 SW |
681 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| 682 | clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; | |
| 683 | resets = <&tegra_car 69>; | |
| 684 | reset-names = "sdhci"; | |
| e2b6d77e | 685 | status = "disabled"; |
| 784c7444 SW |
686 | }; |
| 687 | ||
| e30cb238 | 688 | sdhci@0,700b0600 { |
| 784c7444 | 689 | compatible = "nvidia,tegra124-sdhci"; |
| e30cb238 | 690 | reg = <0x0 0x700b0600 0x0 0x200>; |
| 784c7444 SW |
691 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| 692 | clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; | |
| 693 | resets = <&tegra_car 15>; | |
| 694 | reset-names = "sdhci"; | |
| e2b6d77e | 695 | status = "disabled"; |
| 784c7444 SW |
696 | }; |
| 697 | ||
| 26b76f80 MP |
698 | soctherm: thermal-sensor@0,700e2000 { |
| 699 | compatible = "nvidia,tegra124-soctherm"; | |
| 700 | reg = <0x0 0x700e2000 0x0 0x1000>; | |
| 701 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; | |
| 702 | clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, | |
| 703 | <&tegra_car TEGRA124_CLK_SOC_THERM>; | |
| 704 | clock-names = "tsensor", "soctherm"; | |
| 705 | resets = <&tegra_car 78>; | |
| 706 | reset-names = "soctherm"; | |
| 707 | #thermal-sensor-cells = <1>; | |
| 708 | }; | |
| 709 | ||
| bf9d0267 TT |
710 | dfll: clock@0,70110000 { |
| 711 | compatible = "nvidia,tegra124-dfll"; | |
| 712 | reg = <0 0x70110000 0 0x100>, /* DFLL control */ | |
| 713 | <0 0x70110000 0 0x100>, /* I2C output control */ | |
| 714 | <0 0x70110100 0 0x100>, /* Integrated I2C controller */ | |
| 715 | <0 0x70110200 0 0x100>; /* Look-up table RAM */ | |
| 716 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
| 717 | clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, | |
| 718 | <&tegra_car TEGRA124_CLK_DFLL_REF>, | |
| 719 | <&tegra_car TEGRA124_CLK_I2C5>; | |
| 720 | clock-names = "soc", "ref", "i2c"; | |
| 721 | resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; | |
| 722 | reset-names = "dvco"; | |
| 723 | #clock-cells = <0>; | |
| 724 | clock-output-names = "dfllCPU_out"; | |
| 725 | nvidia,sample-rate = <12500>; | |
| 726 | nvidia,droop-ctrl = <0x00000f00>; | |
| 727 | nvidia,force-mode = <1>; | |
| 728 | nvidia,cf = <10>; | |
| 729 | nvidia,ci = <0>; | |
| 730 | nvidia,cg = <2>; | |
| 731 | status = "disabled"; | |
| 732 | }; | |
| 733 | ||
| e30cb238 | 734 | ahub@0,70300000 { |
| e6655578 | 735 | compatible = "nvidia,tegra124-ahub"; |
| e30cb238 SW |
736 | reg = <0x0 0x70300000 0x0 0x200>, |
| 737 | <0x0 0x70300800 0x0 0x800>, | |
| 738 | <0x0 0x70300200 0x0 0x600>; | |
| e6655578 SW |
739 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| 740 | clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, | |
| 741 | <&tegra_car TEGRA124_CLK_APBIF>; | |
| 742 | clock-names = "d_audio", "apbif"; | |
| 743 | resets = <&tegra_car 106>, /* d_audio */ | |
| 744 | <&tegra_car 107>, /* apbif */ | |
| 745 | <&tegra_car 30>, /* i2s0 */ | |
| 746 | <&tegra_car 11>, /* i2s1 */ | |
| 747 | <&tegra_car 18>, /* i2s2 */ | |
| 748 | <&tegra_car 101>, /* i2s3 */ | |
| 749 | <&tegra_car 102>, /* i2s4 */ | |
| 750 | <&tegra_car 108>, /* dam0 */ | |
| 751 | <&tegra_car 109>, /* dam1 */ | |
| 752 | <&tegra_car 110>, /* dam2 */ | |
| 753 | <&tegra_car 10>, /* spdif */ | |
| 754 | <&tegra_car 153>, /* amx */ | |
| 755 | <&tegra_car 185>, /* amx1 */ | |
| 756 | <&tegra_car 154>, /* adx */ | |
| 757 | <&tegra_car 180>, /* adx1 */ | |
| 758 | <&tegra_car 186>, /* afc0 */ | |
| 759 | <&tegra_car 187>, /* afc1 */ | |
| 760 | <&tegra_car 188>, /* afc2 */ | |
| 761 | <&tegra_car 189>, /* afc3 */ | |
| 762 | <&tegra_car 190>, /* afc4 */ | |
| 763 | <&tegra_car 191>; /* afc5 */ | |
| 764 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", | |
| 765 | "i2s3", "i2s4", "dam0", "dam1", "dam2", | |
| 766 | "spdif", "amx", "amx1", "adx", "adx1", | |
| 767 | "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; | |
| 768 | dmas = <&apbdma 1>, <&apbdma 1>, | |
| 769 | <&apbdma 2>, <&apbdma 2>, | |
| 770 | <&apbdma 3>, <&apbdma 3>, | |
| 771 | <&apbdma 4>, <&apbdma 4>, | |
| 772 | <&apbdma 6>, <&apbdma 6>, | |
| 773 | <&apbdma 7>, <&apbdma 7>, | |
| 774 | <&apbdma 12>, <&apbdma 12>, | |
| 775 | <&apbdma 13>, <&apbdma 13>, | |
| 776 | <&apbdma 14>, <&apbdma 14>, | |
| 777 | <&apbdma 29>, <&apbdma 29>; | |
| 778 | dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", | |
| 779 | "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", | |
| 780 | "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", | |
| 781 | "rx9", "tx9"; | |
| 782 | ranges; | |
| e30cb238 SW |
783 | #address-cells = <2>; |
| 784 | #size-cells = <2>; | |
| e6655578 | 785 | |
| e30cb238 | 786 | tegra_i2s0: i2s@0,70301000 { |
| e6655578 | 787 | compatible = "nvidia,tegra124-i2s"; |
| e30cb238 | 788 | reg = <0x0 0x70301000 0x0 0x100>; |
| e6655578 SW |
789 | nvidia,ahub-cif-ids = <4 4>; |
| 790 | clocks = <&tegra_car TEGRA124_CLK_I2S0>; | |
| 791 | resets = <&tegra_car 30>; | |
| 792 | reset-names = "i2s"; | |
| 793 | status = "disabled"; | |
| 794 | }; | |
| 795 | ||
| e30cb238 | 796 | tegra_i2s1: i2s@0,70301100 { |
| e6655578 | 797 | compatible = "nvidia,tegra124-i2s"; |
| e30cb238 | 798 | reg = <0x0 0x70301100 0x0 0x100>; |
| e6655578 SW |
799 | nvidia,ahub-cif-ids = <5 5>; |
| 800 | clocks = <&tegra_car TEGRA124_CLK_I2S1>; | |
| 801 | resets = <&tegra_car 11>; | |
| 802 | reset-names = "i2s"; | |
| 803 | status = "disabled"; | |
| 804 | }; | |
| 805 | ||
| e30cb238 | 806 | tegra_i2s2: i2s@0,70301200 { |
| e6655578 | 807 | compatible = "nvidia,tegra124-i2s"; |
| e30cb238 | 808 | reg = <0x0 0x70301200 0x0 0x100>; |
| e6655578 SW |
809 | nvidia,ahub-cif-ids = <6 6>; |
| 810 | clocks = <&tegra_car TEGRA124_CLK_I2S2>; | |
| 811 | resets = <&tegra_car 18>; | |
| 812 | reset-names = "i2s"; | |
| 813 | status = "disabled"; | |
| 814 | }; | |
| 815 | ||
| e30cb238 | 816 | tegra_i2s3: i2s@0,70301300 { |
| e6655578 | 817 | compatible = "nvidia,tegra124-i2s"; |
| e30cb238 | 818 | reg = <0x0 0x70301300 0x0 0x100>; |
| e6655578 SW |
819 | nvidia,ahub-cif-ids = <7 7>; |
| 820 | clocks = <&tegra_car TEGRA124_CLK_I2S3>; | |
| 821 | resets = <&tegra_car 101>; | |
| 822 | reset-names = "i2s"; | |
| 823 | status = "disabled"; | |
| 824 | }; | |
| 825 | ||
| e30cb238 | 826 | tegra_i2s4: i2s@0,70301400 { |
| e6655578 | 827 | compatible = "nvidia,tegra124-i2s"; |
| e30cb238 | 828 | reg = <0x0 0x70301400 0x0 0x100>; |
| e6655578 SW |
829 | nvidia,ahub-cif-ids = <8 8>; |
| 830 | clocks = <&tegra_car TEGRA124_CLK_I2S4>; | |
| 831 | resets = <&tegra_car 102>; | |
| 832 | reset-names = "i2s"; | |
| 833 | status = "disabled"; | |
| 834 | }; | |
| 835 | }; | |
| 836 | ||
| e30cb238 | 837 | usb@0,7d000000 { |
| f2d50158 | 838 | compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; |
| e30cb238 | 839 | reg = <0x0 0x7d000000 0x0 0x4000>; |
| f2d50158 TR |
840 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 841 | phy_type = "utmi"; | |
| 842 | clocks = <&tegra_car TEGRA124_CLK_USBD>; | |
| 843 | resets = <&tegra_car 22>; | |
| 844 | reset-names = "usb"; | |
| 845 | nvidia,phy = <&phy1>; | |
| 846 | status = "disabled"; | |
| 847 | }; | |
| 848 | ||
| e30cb238 | 849 | phy1: usb-phy@0,7d000000 { |
| f2d50158 | 850 | compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; |
| e30cb238 SW |
851 | reg = <0x0 0x7d000000 0x0 0x4000>, |
| 852 | <0x0 0x7d000000 0x0 0x4000>; | |
| f2d50158 TR |
853 | phy_type = "utmi"; |
| 854 | clocks = <&tegra_car TEGRA124_CLK_USBD>, | |
| 855 | <&tegra_car TEGRA124_CLK_PLL_U>, | |
| 856 | <&tegra_car TEGRA124_CLK_USBD>; | |
| 857 | clock-names = "reg", "pll_u", "utmi-pads"; | |
| a4b6916c | 858 | resets = <&tegra_car 22>, <&tegra_car 22>; |
| 308efde2 | 859 | reset-names = "usb", "utmi-pads"; |
| f2d50158 TR |
860 | nvidia,hssync-start-delay = <0>; |
| 861 | nvidia,idle-wait-delay = <17>; | |
| 862 | nvidia,elastic-limit = <16>; | |
| 863 | nvidia,term-range-adj = <6>; | |
| 864 | nvidia,xcvr-setup = <9>; | |
| 865 | nvidia,xcvr-lsfslew = <0>; | |
| 866 | nvidia,xcvr-lsrslew = <3>; | |
| 867 | nvidia,hssquelch-level = <2>; | |
| 868 | nvidia,hsdiscon-level = <5>; | |
| 869 | nvidia,xcvr-hsslew = <12>; | |
| a4b6916c | 870 | nvidia,has-utmi-pad-registers; |
| f2d50158 TR |
871 | status = "disabled"; |
| 872 | }; | |
| 873 | ||
| e30cb238 | 874 | usb@0,7d004000 { |
| f2d50158 | 875 | compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; |
| e30cb238 | 876 | reg = <0x0 0x7d004000 0x0 0x4000>; |
| f2d50158 TR |
877 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| 878 | phy_type = "utmi"; | |
| 879 | clocks = <&tegra_car TEGRA124_CLK_USB2>; | |
| 880 | resets = <&tegra_car 58>; | |
| 881 | reset-names = "usb"; | |
| 882 | nvidia,phy = <&phy2>; | |
| 883 | status = "disabled"; | |
| 884 | }; | |
| 885 | ||
| e30cb238 | 886 | phy2: usb-phy@0,7d004000 { |
| f2d50158 | 887 | compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; |
| e30cb238 SW |
888 | reg = <0x0 0x7d004000 0x0 0x4000>, |
| 889 | <0x0 0x7d000000 0x0 0x4000>; | |
| f2d50158 TR |
890 | phy_type = "utmi"; |
| 891 | clocks = <&tegra_car TEGRA124_CLK_USB2>, | |
| 892 | <&tegra_car TEGRA124_CLK_PLL_U>, | |
| 893 | <&tegra_car TEGRA124_CLK_USBD>; | |
| 894 | clock-names = "reg", "pll_u", "utmi-pads"; | |
| a4b6916c | 895 | resets = <&tegra_car 58>, <&tegra_car 22>; |
| 308efde2 | 896 | reset-names = "usb", "utmi-pads"; |
| f2d50158 TR |
897 | nvidia,hssync-start-delay = <0>; |
| 898 | nvidia,idle-wait-delay = <17>; | |
| 899 | nvidia,elastic-limit = <16>; | |
| 900 | nvidia,term-range-adj = <6>; | |
| 901 | nvidia,xcvr-setup = <9>; | |
| 902 | nvidia,xcvr-lsfslew = <0>; | |
| 903 | nvidia,xcvr-lsrslew = <3>; | |
| 904 | nvidia,hssquelch-level = <2>; | |
| 905 | nvidia,hsdiscon-level = <5>; | |
| 906 | nvidia,xcvr-hsslew = <12>; | |
| 907 | status = "disabled"; | |
| 908 | }; | |
| 909 | ||
| e30cb238 | 910 | usb@0,7d008000 { |
| f2d50158 | 911 | compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; |
| e30cb238 | 912 | reg = <0x0 0x7d008000 0x0 0x4000>; |
| f2d50158 TR |
913 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| 914 | phy_type = "utmi"; | |
| 915 | clocks = <&tegra_car TEGRA124_CLK_USB3>; | |
| 916 | resets = <&tegra_car 59>; | |
| 917 | reset-names = "usb"; | |
| 918 | nvidia,phy = <&phy3>; | |
| 919 | status = "disabled"; | |
| 920 | }; | |
| 921 | ||
| e30cb238 | 922 | phy3: usb-phy@0,7d008000 { |
| f2d50158 | 923 | compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; |
| e30cb238 SW |
924 | reg = <0x0 0x7d008000 0x0 0x4000>, |
| 925 | <0x0 0x7d000000 0x0 0x4000>; | |
| f2d50158 TR |
926 | phy_type = "utmi"; |
| 927 | clocks = <&tegra_car TEGRA124_CLK_USB3>, | |
| 928 | <&tegra_car TEGRA124_CLK_PLL_U>, | |
| 929 | <&tegra_car TEGRA124_CLK_USBD>; | |
| 930 | clock-names = "reg", "pll_u", "utmi-pads"; | |
| a4b6916c | 931 | resets = <&tegra_car 59>, <&tegra_car 22>; |
| 308efde2 | 932 | reset-names = "usb", "utmi-pads"; |
| f2d50158 TR |
933 | nvidia,hssync-start-delay = <0>; |
| 934 | nvidia,idle-wait-delay = <17>; | |
| 935 | nvidia,elastic-limit = <16>; | |
| 936 | nvidia,term-range-adj = <6>; | |
| 937 | nvidia,xcvr-setup = <9>; | |
| 938 | nvidia,xcvr-lsfslew = <0>; | |
| 939 | nvidia,xcvr-lsrslew = <3>; | |
| 940 | nvidia,hssquelch-level = <2>; | |
| 941 | nvidia,hsdiscon-level = <5>; | |
| 942 | nvidia,xcvr-hsslew = <12>; | |
| 943 | status = "disabled"; | |
| 944 | }; | |
| 945 | ||
| ad03b1a7 JL |
946 | cpus { |
| 947 | #address-cells = <1>; | |
| 948 | #size-cells = <0>; | |
| 949 | ||
| 950 | cpu@0 { | |
| 951 | device_type = "cpu"; | |
| 952 | compatible = "arm,cortex-a15"; | |
| 953 | reg = <0>; | |
| 0de088cc TT |
954 | |
| 955 | clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, | |
| 956 | <&tegra_car TEGRA124_CLK_CCLK_LP>, | |
| 957 | <&tegra_car TEGRA124_CLK_PLL_X>, | |
| 958 | <&tegra_car TEGRA124_CLK_PLL_P>, | |
| 959 | <&dfll>; | |
| 960 | clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; | |
| 961 | /* FIXME: what's the actual transition time? */ | |
| 962 | clock-latency = <300000>; | |
| ad03b1a7 JL |
963 | }; |
| 964 | ||
| 965 | cpu@1 { | |
| 966 | device_type = "cpu"; | |
| 967 | compatible = "arm,cortex-a15"; | |
| 968 | reg = <1>; | |
| 969 | }; | |
| 970 | ||
| 971 | cpu@2 { | |
| 972 | device_type = "cpu"; | |
| 973 | compatible = "arm,cortex-a15"; | |
| 974 | reg = <2>; | |
| 975 | }; | |
| 976 | ||
| 977 | cpu@3 { | |
| 978 | device_type = "cpu"; | |
| 979 | compatible = "arm,cortex-a15"; | |
| 980 | reg = <3>; | |
| 981 | }; | |
| 982 | }; | |
| 983 | ||
| 82fe42f5 KH |
984 | pmu { |
| 985 | compatible = "arm,cortex-a15-pmu"; | |
| 986 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, | |
| 987 | <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, | |
| 988 | <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, | |
| 989 | <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; | |
| 990 | interrupt-affinity = <&{/cpus/cpu@0}>, | |
| 991 | <&{/cpus/cpu@1}>, | |
| 992 | <&{/cpus/cpu@2}>, | |
| 993 | <&{/cpus/cpu@3}>; | |
| 994 | }; | |
| 995 | ||
| 26b76f80 MP |
996 | thermal-zones { |
| 997 | cpu { | |
| 998 | polling-delay-passive = <1000>; | |
| 999 | polling-delay = <1000>; | |
| 1000 | ||
| 1001 | thermal-sensors = | |
| 1002 | <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; | |
| 1003 | }; | |
| 1004 | ||
| 1005 | mem { | |
| 1006 | polling-delay-passive = <1000>; | |
| 1007 | polling-delay = <1000>; | |
| 1008 | ||
| 1009 | thermal-sensors = | |
| 1010 | <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; | |
| 1011 | }; | |
| 1012 | ||
| 1013 | gpu { | |
| 1014 | polling-delay-passive = <1000>; | |
| 1015 | polling-delay = <1000>; | |
| 1016 | ||
| 1017 | thermal-sensors = | |
| 1018 | <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; | |
| 1019 | }; | |
| 1020 | ||
| 1021 | pllx { | |
| 1022 | polling-delay-passive = <1000>; | |
| 1023 | polling-delay = <1000>; | |
| 1024 | ||
| 1025 | thermal-sensors = | |
| 1026 | <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; | |
| 1027 | }; | |
| 1028 | }; | |
| 1029 | ||
| ad03b1a7 JL |
1030 | timer { |
| 1031 | compatible = "arm,armv7-timer"; | |
| 1032 | interrupts = <GIC_PPI 13 | |
| 1033 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 1034 | <GIC_PPI 14 | |
| 1035 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 1036 | <GIC_PPI 11 | |
| 1037 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 1038 | <GIC_PPI 10 | |
| 1039 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
| 870c81a4 | 1040 | interrupt-parent = <&gic>; |
| ad03b1a7 JL |
1041 | }; |
| 1042 | }; |