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Merge tag 'omap-for-v5.1/dt-cpsw-phy' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / tegra20-colibri.dtsi
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
1bd0bd49 2#include "tegra20.dtsi"
fc9c713a 3
6a4a865d
MZ		 4/*
5 * Toradex Colibri T20 Module Device Tree
6 * Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A;
7 * Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A;
8 * Colibri T20 512MB IT V1.2A
9 */
fc9c713a 10/ {
48299769 11 memory@0 {
8ab11f80
KK		 12 /*
13 * Set memory to 256 MB to be safe as this could be used on
14 * 256 or 512 MB module. It is expected from bootloader
15 * to fix this up for 512 MB version.
16 */
17 reg = <0x00000000 0x10000000>;
fc9c713a
LS		 18 };
19
58ecb23f
SW		 20 host1x@50000000 {
21 hdmi@54280000 {
82e7cecc 22 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
e6800c21
MZ		 23 nvidia,hpd-gpio =
24 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
3647c7b8
MZ		 25 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
26 vdd-supply = <&reg_3v3_avdd_hdmi>;
fc9c713a
LS		 27 };
28 };
29
58ecb23f 30 pinmux@70000014 {
fc9c713a
LS		 31 pinctrl-names = "default";
32 pinctrl-0 = <&state_default>;
33
34 state_default: pinmux {
a2cb59be
MZ		 35 /* Analogue Audio AC97 to WM9712 (On-module) */
36 audio-refclk {
fc9c713a
LS		 37 nvidia,pins = "cdev1";
38 nvidia,function = "plla_out";
ba4104e7
LD		 39 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
40 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a 41 };
fc9c713a
LS		 42 dap3 {
43 nvidia,pins = "dap3";
44 nvidia,function = "dap3";
ba4104e7
LD		 45 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
46 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a 47 };
a2cb59be
MZ		 48
49 /*
50 * AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ
51 * (All on-module), SODIMM Pin 45 Wakeup
52 */
53 gpio-uac {
54 nvidia,pins = "uac";
55 nvidia,function = "rsvd2";
ba4104e7
LD		 56 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
57 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a 58 };
a2cb59be
MZ		 59
60 /*
61 * Buffer Enables for nPWE and RDnWR (On-module,
62 * see GPIO hogging further down below)
63 */
64 gpio-pta {
fc9c713a
LS		 65 nvidia,pins = "pta";
66 nvidia,function = "rsvd4";
ba4104e7
LD		 67 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
68 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a 69 };
a2cb59be
MZ		 70
71 /*
72 * CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N,
73 * SYS_CLK_REQ (All on-module)
74 */
75 pmc {
76 nvidia,pins = "pmc";
77 nvidia,function = "pwr_on";
ba4104e7 78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a 79 };
a2cb59be 80
992cf09b
MZ		 81 /*
82 * Colibri Address/Data Bus (GMI)
83 * Note: spid and spie optionally used for SPI1
84 */
85 gmi {
86 nvidia,pins = "atc", "atd", "ate", "dap1",
87 "dap2", "dap4", "gmd", "gpu",
88 "irrx", "irtx", "spia", "spib",
89 "spic", "spid", "spie", "uca",
90 "ucb";
a2cb59be
MZ		 91 nvidia,function = "gmi";
92 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
992cf09b
MZ		 93 nvidia,tristate = <TEGRA_PIN_ENABLE>;
94 };
95 /* Further pins may be used as GPIOs */
96 gmi-gpio1 {
97 nvidia,pins = "lpw0", "lsc1", "lsck", "lsda";
98 nvidia,function = "hdmi";
99 nvidia,tristate = <TEGRA_PIN_ENABLE>;
100 };
101 gmi-gpio2 {
102 nvidia,pins = "lcsn", "ldc", "lm0", "lsdi";
103 nvidia,function = "rsvd4";
104 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a 105 };
a2cb59be
MZ		 106
107 /* Colibri BL_ON */
108 bl-on {
109 nvidia,pins = "dta";
992cf09b 110 nvidia,function = "rsvd1";
ba4104e7
LD		 111 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
112 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a 113 };
a2cb59be
MZ		 114
115 /* Colibri Backlight PWM<A>, PWM<B> */
116 pwm-a-b {
117 nvidia,pins = "sdc";
118 nvidia,function = "pwm";
ba4104e7 119 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a 120 };
a2cb59be
MZ		 121
122 /* Colibri DDC */
123 ddc {
fc9c713a
LS		 124 nvidia,pins = "ddc";
125 nvidia,function = "i2c2";
ba4104e7
LD		 126 nvidia,pull = <TEGRA_PIN_PULL_UP>;
127 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a 128 };
a2cb59be
MZ		 129
130 /*
131 * Colibri EXT_IO*
132 * Note: dtf optionally used for I2C3
133 */
134 ext-io {
992cf09b
MZ		 135 nvidia,pins = "dtf", "spdi";
136 nvidia,function = "rsvd2";
ba4104e7 137 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
a2cb59be 138 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a 139 };
a2cb59be
MZ		 140
141 /*
142 * Colibri Ethernet (On-module)
143 * ULPI EHCI instance 1 USB2_DP/N -> AX88772B
144 */
145 ulpi {
146 nvidia,pins = "uaa", "uab", "uda";
147 nvidia,function = "ulpi";
ba4104e7 148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
a2cb59be 149 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a 150 };
a2cb59be
MZ		 151 ulpi-refclk {
152 nvidia,pins = "cdev2";
153 nvidia,function = "pllp_out4";
ba4104e7
LD		 154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155 nvidia,tristate = <TEGRA_PIN_DISABLE>;
fc9c713a 156 };
a2cb59be
MZ		 157
158 /* Colibri HOTPLUG_DETECT (HDMI) */
159 hotplug-detect {
160 nvidia,pins = "hdint";
161 nvidia,function = "hdmi";
162 nvidia,tristate = <TEGRA_PIN_ENABLE>;
163 };
164
165 /* Colibri I2C */
166 i2c {
167 nvidia,pins = "rm";
168 nvidia,function = "i2c1";
ba4104e7
LD		 169 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
170 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a 171 };
a2cb59be 172
992cf09b
MZ		 173 /*
174 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
175 * today's display need DE, disable LCD_M1
176 */
177 lm1 {
178 nvidia,pins = "lm1";
179 nvidia,function = "rsvd3";
180 nvidia,tristate = <TEGRA_PIN_ENABLE>;
181 };
182
a2cb59be
MZ		 183 /* Colibri LCD (L_* resp. LDD<*>) */
184 lcd {
185 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
186 "ld4", "ld5", "ld6", "ld7",
187 "ld8", "ld9", "ld10", "ld11",
188 "ld12", "ld13", "ld14", "ld15",
992cf09b
MZ		 189 "ld16", "ld17", "lhs", "lsc0",
190 "lspi", "lvs";
191 nvidia,function = "displaya";
192 nvidia,tristate = <TEGRA_PIN_ENABLE>;
193 };
194 /* Colibri LCD (Optional 24 BPP Support) */
195 lcd-24 {
196 nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2",
197 "lpp", "lvp1";
a2cb59be
MZ		 198 nvidia,function = "displaya";
199 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a 200 };
a2cb59be
MZ		 201
202 /* Colibri MMC */
203 mmc {
204 nvidia,pins = "atb", "gma";
205 nvidia,function = "sdio4";
206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 207 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a 208 };
a2cb59be 209
992cf09b
MZ		 210 /* Colibri MMCCD */
211 mmccd {
212 nvidia,pins = "gmb";
213 nvidia,function = "gmi_int";
214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
215 nvidia,tristate = <TEGRA_PIN_ENABLE>;
216 };
217
a2cb59be
MZ		 218 /* Colibri MMC (Optional 8-bit) */
219 mmc-8bit {
220 nvidia,pins = "gme";
fc9c713a 221 nvidia,function = "sdio4";
ba4104e7
LD		 222 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
223 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a 224 };
a2cb59be
MZ		 225
226 /*
227 * Colibri Parallel Camera (Optional)
228 * pins multiplexed with others and therefore disabled
229 * Note: dta used for BL_ON by default
230 */
231 cif-mclk {
232 nvidia,pins = "csus";
233 nvidia,function = "vi_sensor_clk";
234 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
235 nvidia,tristate = <TEGRA_PIN_ENABLE>;
236 };
237 cif {
238 nvidia,pins = "dtb", "dtc", "dtd";
239 nvidia,function = "vi";
ba4104e7
LD		 240 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
241 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a 242 };
a2cb59be
MZ		 243
244 /* Colibri PWM<C>, PWM<D> */
245 pwm-c-d {
246 nvidia,pins = "sdb", "sdd";
247 nvidia,function = "pwm";
248 nvidia,tristate = <TEGRA_PIN_ENABLE>;
249 };
250
251 /* Colibri SSP */
252 ssp {
fc9c713a
LS		 253 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
254 nvidia,function = "spi4";
ba4104e7
LD		 255 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
256 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a 257 };
a2cb59be
MZ		 258
259 /* Colibri UART-A */
260 uart-a {
fc9c713a
LS		 261 nvidia,pins = "sdio1";
262 nvidia,function = "uarta";
ba4104e7
LD		 263 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
264 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a 265 };
992cf09b
MZ		 266 uart-a-dsr {
267 nvidia,pins = "lpw1";
268 nvidia,function = "rsvd3";
269 nvidia,tristate = <TEGRA_PIN_ENABLE>;
270 };
271 uart-a-dcd {
272 nvidia,pins = "lpw2";
273 nvidia,function = "hdmi";
274 nvidia,tristate = <TEGRA_PIN_ENABLE>;
275 };
a2cb59be
MZ		 276
277 /* Colibri UART-B */
278 uart-b {
fc9c713a
LS		 279 nvidia,pins = "gmc";
280 nvidia,function = "uartd";
ba4104e7
LD		 281 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
282 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a 283 };
a2cb59be
MZ		 284
285 /* Colibri UART-C */
286 uart-c {
287 nvidia,pins = "uad";
288 nvidia,function = "irda";
ba4104e7 289 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
a2cb59be 290 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a 291 };
a2cb59be 292
992cf09b
MZ		 293 /* Colibri USB_CDET */
294 usb-cdet {
295 nvidia,pins = "spdo";
296 nvidia,function = "rsvd2";
297 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
298 nvidia,tristate = <TEGRA_PIN_ENABLE>;
299 };
300
a2cb59be
MZ		 301 /* Colibri USBH_OC */
302 usbh-oc {
303 nvidia,pins = "spih";
304 nvidia,function = "spi2_alt";
ba4104e7 305 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
992cf09b 306 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a 307 };
a2cb59be
MZ		 308
309 /* Colibri USBH_PEN */
310 usbh-pen {
311 nvidia,pins = "spig";
fc9c713a 312 nvidia,function = "spi2_alt";
ba4104e7 313 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
992cf09b 314 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a 315 };
a2cb59be
MZ		 316
317 /* Colibri VGA not supported */
318 vga {
319 nvidia,pins = "crtp";
320 nvidia,function = "crt";
ba4104e7
LD		 321 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
322 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a 323 };
a2cb59be 324
992cf09b
MZ		 325 /* I2C3 (Optional) */
326 i2c3 {
327 nvidia,pins = "dtf";
328 nvidia,function = "i2c3";
329 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
330 nvidia,tristate = <TEGRA_PIN_ENABLE>;
331 };
332
333 /* JTAG_RTCK */
334 jtag-rtck {
335 nvidia,pins = "gpu7";
336 nvidia,function = "rtck";
337 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
338 nvidia,tristate = <TEGRA_PIN_ENABLE>;
339 };
340
341 /*
342 * LAN_RESET, LAN_EXT_WAKEUP and LAN_PME
343 * (All On-module)
344 */
345 gpio-gpv {
346 nvidia,pins = "gpv";
347 nvidia,function = "rsvd2";
348 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
349 nvidia,tristate = <TEGRA_PIN_DISABLE>;
350 };
351
a2cb59be
MZ		 352 /*
353 * LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN
354 * (All On-module); Colibri CAN_INT
355 */
356 gpio-dte {
357 nvidia,pins = "dte";
358 nvidia,function = "rsvd1";
359 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
360 nvidia,tristate = <TEGRA_PIN_DISABLE>;
361 };
362
363 /* NAND (On-module) */
364 nand {
992cf09b 365 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
a2cb59be
MZ		 366 "kbce", "kbcf";
367 nvidia,function = "nand";
368 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
369 nvidia,tristate = <TEGRA_PIN_DISABLE>;
370 };
371
372 /* Onewire (Optional) */
373 owr {
374 nvidia,pins = "owc";
375 nvidia,function = "owr";
376 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
377 nvidia,tristate = <TEGRA_PIN_ENABLE>;
378 };
379
380 /* Power I2C (On-module) */
381 i2cp {
382 nvidia,pins = "i2cp";
383 nvidia,function = "i2cp";
384 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
385 nvidia,tristate = <TEGRA_PIN_DISABLE>;
386 };
387
992cf09b
MZ		 388 /* RESET_OUT */
389 reset-out {
390 nvidia,pins = "ata";
391 nvidia,function = "gmi";
392 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
393 nvidia,tristate = <TEGRA_PIN_DISABLE>;
394 };
395
a2cb59be
MZ		 396 /*
397 * SPI1 (Optional)
398 * Note: spid and spie used for Colibri Address/Data
399 * Bus (GMI)
400 */
401 spi1 {
402 nvidia,pins = "spid", "spie", "spif";
403 nvidia,function = "spi1";
ba4104e7
LD		 404 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
405 nvidia,tristate = <TEGRA_PIN_ENABLE>;
fc9c713a 406 };
992cf09b
MZ		 407
408 /*
409 * THERMD_ALERT# (On-module), unlatched I2C address pin
410 * of LM95245 temperature sensor therefore requires
411 * disabling for now
412 */
413 lvp0 {
414 nvidia,pins = "lvp0";
415 nvidia,function = "rsvd3";
416 nvidia,tristate = <TEGRA_PIN_ENABLE>;
417 };
fc9c713a
LS		 418 };
419 };
420
5373f802 421 tegra_ac97: ac97@70002000 {
57899053 422 status = "okay";
035ae62d
MZ		 423 nvidia,codec-reset-gpio =
424 <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
425 nvidia,codec-sync-gpio =
426 <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
57899053
SW		 427 };
428
9ad510b3
MZ		 429 serial@70006040 {
430 compatible = "nvidia,tegra20-hsuart";
431 };
432
433 serial@70006300 {
434 compatible = "nvidia,tegra20-hsuart";
435 };
436
5def854e
SA		 437 nand-controller@70008000 {
438 status = "okay";
439
440 nand@0 {
441 reg = <0>;
442 #address-cells = <1>;
443 #size-cells = <1>;
444 nand-bus-width = <8>;
445 nand-on-flash-bbt;
446 nand-ecc-algo = "bch";
447 nand-is-boot-medium;
448 nand-ecc-maximize;
449 wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
450 };
451 };
452
1c3389e6
MZ		 453 /*
454 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
455 * board)
456 */
fc9c713a
LS		 457 i2c@7000c000 {
458 clock-frequency = <400000>;
459 };
460
1c3389e6 461 /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
82e7cecc 462 hdmi_ddc: i2c@7000c400 {
1c3389e6 463 clock-frequency = <10000>;
fc9c713a
LS		 464 };
465
1c3389e6 466 /* GEN2_I2C: unused */
fc9c713a 467
1c3389e6
MZ		 468 /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */
469
470 /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */
fc9c713a
LS		 471 i2c@7000d000 {
472 status = "okay";
1c3389e6 473 clock-frequency = <100000>;
fc9c713a 474
8f4a8e09 475 pmic@34 {
fc9c713a
LS		 476 compatible = "ti,tps6586x";
477 reg = <0x34>;
6cecf916 478 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
fc9c713a 479 ti,system-power-controller;
fc9c713a
LS		 480 #gpio-cells = <2>;
481 gpio-controller;
3647c7b8
MZ		 482 sys-supply = <&reg_module_3v3>;
483 vin-sm0-supply = <&reg_3v3_vsys>;
484 vin-sm1-supply = <&reg_3v3_vsys>;
485 vin-sm2-supply = <&reg_3v3_vsys>;
486 vinldo01-supply = <&reg_1v8_vdd_ddr2>;
487 vinldo23-supply = <&reg_module_3v3>;
488 vinldo4-supply = <&reg_module_3v3>;
489 vinldo678-supply = <&reg_module_3v3>;
490 vinldo9-supply = <&reg_module_3v3>;
fc9c713a
LS		 491
492 regulators {
3647c7b8
MZ		 493 reg_3v3_vsys: sys {
494 regulator-name = "VSYS_3.3V";
fc9c713a
LS		 495 regulator-always-on;
496 };
497
3647c7b8
MZ		 498 sm0 {
499 regulator-name = "VDD_CORE_1.2V";
c7ac2b7b
SA		 500 regulator-min-microvolt = <1200000>;
501 regulator-max-microvolt = <1200000>;
fc9c713a
LS		 502 regulator-always-on;
503 };
504
3647c7b8
MZ		 505 sm1 {
506 regulator-name = "VDD_CPU_1.0V";
c7ac2b7b
SA		 507 regulator-min-microvolt = <1000000>;
508 regulator-max-microvolt = <1000000>;
fc9c713a
LS		 509 regulator-always-on;
510 };
511
3647c7b8
MZ		 512 reg_1v8_vdd_ddr2: sm2 {
513 regulator-name = "VDD_DDR2_1.8V";
844a4f0d
SA		 514 regulator-min-microvolt = <1800000>;
515 regulator-max-microvolt = <1800000>;
fc9c713a
LS		 516 regulator-always-on;
517 };
518
519 /* LDO0 is not connected to anything */
520
3647c7b8
MZ		 521 /*
522 * +3.3V_ENABLE_N switching via FET:
523 * AVDD_AUDIO_S and +3.3V
524 * see also +3.3V fixed supply
525 */
526 ldo1 {
527 regulator-name = "AVDD_PLL_1.1V";
fc9c713a
LS		 528 regulator-min-microvolt = <1100000>;
529 regulator-max-microvolt = <1100000>;
530 regulator-always-on;
531 };
532
3647c7b8
MZ		 533 ldo2 {
534 regulator-name = "VDD_RTC_1.2V";
fc9c713a
LS		 535 regulator-min-microvolt = <1200000>;
536 regulator-max-microvolt = <1200000>;
537 };
538
539 /* LDO3 is not connected to anything */
540
3647c7b8
MZ		 541 ldo4 {
542 regulator-name = "VDDIO_SYS_1.8V";
fc9c713a
LS		 543 regulator-min-microvolt = <1800000>;
544 regulator-max-microvolt = <1800000>;
545 regulator-always-on;
546 };
547
3647c7b8
MZ		 548 /* Switched via FET from regular +3.3V */
549 ldo5 {
550 regulator-name = "+3.3V_USB";
fc9c713a
LS		 551 regulator-min-microvolt = <3300000>;
552 regulator-max-microvolt = <3300000>;
553 regulator-always-on;
554 };
555
3647c7b8
MZ		 556 ldo6 {
557 regulator-name = "AVDD_VDAC_2.85V";
c7ac2b7b
SA		 558 regulator-min-microvolt = <2850000>;
559 regulator-max-microvolt = <2850000>;
fc9c713a
LS		 560 };
561
3647c7b8
MZ		 562 reg_3v3_avdd_hdmi: ldo7 {
563 regulator-name = "AVDD_HDMI_3.3V";
fc9c713a
LS		 564 regulator-min-microvolt = <3300000>;
565 regulator-max-microvolt = <3300000>;
566 };
567
3647c7b8
MZ		 568 reg_1v8_avdd_hdmi_pll: ldo8 {
569 regulator-name = "AVDD_HDMI_PLL_1.8V";
fc9c713a
LS		 570 regulator-min-microvolt = <1800000>;
571 regulator-max-microvolt = <1800000>;
572 };
573
3647c7b8
MZ		 574 ldo9 {
575 regulator-name = "VDDIO_RX_DDR_2.85V";
fc9c713a
LS		 576 regulator-min-microvolt = <2850000>;
577 regulator-max-microvolt = <2850000>;
578 regulator-always-on;
579 };
580
3647c7b8
MZ		 581 ldo_rtc {
582 regulator-name = "VCC_BATT";
fc9c713a
LS		 583 regulator-min-microvolt = <3300000>;
584 regulator-max-microvolt = <3300000>;
585 regulator-always-on;
586 };
587 };
588 };
589
df2be1ae
MZ		 590 /* LM95245 temperature sensor */
591 temp-sensor@4c {
fc9c713a
LS		 592 compatible = "national,lm95245";
593 reg = <0x4c>;
594 };
595 };
596
58ecb23f 597 pmc@7000e400 {
47d2d63b 598 nvidia,suspend-mode = <1>;
a44a019d
JL		 599 nvidia,cpu-pwr-good-time = <5000>;
600 nvidia,cpu-pwr-off-time = <5000>;
601 nvidia,core-pwr-good-time = <3845 3845>;
602 nvidia,core-pwr-off-time = <3875>;
603 nvidia,sys-clock-req-active-high;
d5178bb6
MZ		 604
605 /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */
606 i2c-thermtrip {
607 nvidia,i2c-controller-id = <3>;
608 nvidia,bus-addr = <0x34>;
609 nvidia,reg-addr = <0x14>;
610 nvidia,reg-data = <0x8>;
611 };
a44a019d
JL		 612 };
613
fc9c713a
LS		 614 memory-controller@7000f400 {
615 emc-table@83250 {
616 reg = <83250>;
617 compatible = "nvidia,tegra20-emc-table";
618 clock-frequency = <83250>;
619 nvidia,emc-registers = <0x00000005 0x00000011
620 0x00000004 0x00000002 0x00000004 0x00000004
621 0x00000001 0x0000000a 0x00000002 0x00000002
622 0x00000001 0x00000001 0x00000003 0x00000004
623 0x00000003 0x00000009 0x0000000c 0x0000025f
624 0x00000000 0x00000003 0x00000003 0x00000002
625 0x00000002 0x00000001 0x00000008 0x000000c8
626 0x00000003 0x00000005 0x00000003 0x0000000c
627 0x00000002 0x00000000 0x00000000 0x00000002
628 0x00000000 0x00000000 0x00000083 0x00520006
629 0x00000010 0x00000008 0x00000000 0x00000000
630 0x00000000 0x00000000 0x00000000 0x00000000>;
631 };
632 emc-table@133200 {
633 reg = <133200>;
634 compatible = "nvidia,tegra20-emc-table";
635 clock-frequency = <133200>;
636 nvidia,emc-registers = <0x00000008 0x00000019
637 0x00000006 0x00000002 0x00000004 0x00000004
638 0x00000001 0x0000000a 0x00000002 0x00000002
639 0x00000002 0x00000001 0x00000003 0x00000004
640 0x00000003 0x00000009 0x0000000c 0x0000039f
641 0x00000000 0x00000003 0x00000003 0x00000002
642 0x00000002 0x00000001 0x00000008 0x000000c8
643 0x00000003 0x00000007 0x00000003 0x0000000c
644 0x00000002 0x00000000 0x00000000 0x00000002
645 0x00000000 0x00000000 0x00000083 0x00510006
646 0x00000010 0x00000008 0x00000000 0x00000000
647 0x00000000 0x00000000 0x00000000 0x00000000>;
648 };
649 emc-table@166500 {
650 reg = <166500>;
651 compatible = "nvidia,tegra20-emc-table";
652 clock-frequency = <166500>;
653 nvidia,emc-registers = <0x0000000a 0x00000021
654 0x00000008 0x00000003 0x00000004 0x00000004
655 0x00000002 0x0000000a 0x00000003 0x00000003
656 0x00000002 0x00000001 0x00000003 0x00000004
657 0x00000003 0x00000009 0x0000000c 0x000004df
658 0x00000000 0x00000003 0x00000003 0x00000003
659 0x00000003 0x00000001 0x00000009 0x000000c8
660 0x00000003 0x00000009 0x00000004 0x0000000c
661 0x00000002 0x00000000 0x00000000 0x00000002
662 0x00000000 0x00000000 0x00000083 0x004f0006
663 0x00000010 0x00000008 0x00000000 0x00000000
664 0x00000000 0x00000000 0x00000000 0x00000000>;
665 };
666 emc-table@333000 {
667 reg = <333000>;
668 compatible = "nvidia,tegra20-emc-table";
669 clock-frequency = <333000>;
670 nvidia,emc-registers = <0x00000014 0x00000041
671 0x0000000f 0x00000005 0x00000004 0x00000005
672 0x00000003 0x0000000a 0x00000005 0x00000005
673 0x00000004 0x00000001 0x00000003 0x00000004
674 0x00000003 0x00000009 0x0000000c 0x000009ff
675 0x00000000 0x00000003 0x00000003 0x00000005
676 0x00000005 0x00000001 0x0000000e 0x000000c8
677 0x00000003 0x00000011 0x00000006 0x0000000c
678 0x00000002 0x00000000 0x00000000 0x00000002
679 0x00000000 0x00000000 0x00000083 0x00380006
680 0x00000010 0x00000008 0x00000000 0x00000000
681 0x00000000 0x00000000 0x00000000 0x00000000>;
682 };
683 };
684
2287ef76 685 /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */
fc9c713a
LS		 686 usb@c5004000 {
687 status = "okay";
364ba104
MZ		 688 #address-cells = <1>;
689 #size-cells = <0>;
690
691 asix@1 {
692 reg = <1>;
693 local-mac-address = [00 00 00 00 00 00];
694 };
9dffe3be
VB		 695 };
696
697 usb-phy@c5004000 {
a1632ad3 698 status = "okay";
035ae62d
MZ		 699 nvidia,phy-reset-gpio =
700 <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
18e6ccef 701 vbus-supply = <&reg_lan_v_bus>;
fc9c713a
LS		 702 };
703
cafed755
MZ		 704 clk32k_in: xtal3 {
705 compatible = "fixed-clock";
706 #clock-cells = <0>;
707 clock-frequency = <32768>;
7021d122
JL		 708 };
709
3647c7b8
MZ		 710 reg_lan_v_bus: regulator-lan-v-bus {
711 compatible = "regulator-fixed";
712 regulator-name = "LAN_V_BUS";
713 regulator-min-microvolt = <5000000>;
714 regulator-max-microvolt = <5000000>;
715 enable-active-high;
716 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
717 };
fc9c713a 718
3647c7b8
MZ		 719 reg_module_3v3: regulator-module-3v3 {
720 compatible = "regulator-fixed";
721 regulator-name = "+V3.3";
722 regulator-min-microvolt = <3300000>;
723 regulator-max-microvolt = <3300000>;
724 regulator-always-on;
fc9c713a 725 };
57899053
SW		 726
727 sound {
728 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
035ae62d 729 "nvidia,tegra-audio-wm9712";
ea60afb8 730 nvidia,model = "Toradex Colibri T20";
57899053
SW		 731 nvidia,audio-routing =
732 "Headphone", "HPOUTL",
733 "Headphone", "HPOUTR",
734 "LineIn", "LINEINL",
735 "LineIn", "LINEINR",
736 "Mic", "MIC1";
5373f802 737 nvidia,ac97-controller = <&tegra_ac97>;
57899053
SW		 738 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
739 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
740 <&tegra_car TEGRA20_CLK_CDEV1>;
741 clock-names = "pll_a", "pll_a_out0", "mclk";
742 };
fc9c713a 743};
0b51e73b
MZ		 744
745&gpio {
746 lan-reset-n {
747 gpio-hog;
748 gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>;
749 output-high;
750 line-name = "LAN_RESET#";
751 };
351c72c8
MZ		 752
753 /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */
754 npwe {
755 gpio-hog;
756 gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
757 output-high;
758 line-name = "Tri-state nPWE";
759 };
760
761 /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */
762 rdnwr {
763 gpio-hog;
764 gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
765 output-low;
766 line-name = "Not tri-state RDnWR";
767 };
0b51e73b 768};
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