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Commit | Line | Data |
---|---|---|
8e267f3d GL |
1 | /dts-v1/; |
2 | ||
6bccbd5e | 3 | #include <dt-bindings/input/input.h> |
1bd0bd49 | 4 | #include "tegra20.dtsi" |
8e267f3d GL |
5 | |
6 | / { | |
8fef5dff | 7 | model = "NVIDIA Tegra20 Harmony evaluation board"; |
8e267f3d GL |
8 | compatible = "nvidia,harmony", "nvidia,tegra20"; |
9 | ||
553c0a20 SW |
10 | aliases { |
11 | rtc0 = "/i2c@7000d000/tps6586x@34"; | |
12 | rtc1 = "/rtc@7000e000"; | |
13 | }; | |
14 | ||
f9eb26a4 | 15 | memory { |
95decf84 | 16 | reg = <0x00000000 0x40000000>; |
8e267f3d GL |
17 | }; |
18 | ||
58ecb23f | 19 | host1x@50000000 { |
1d4e0689 TR |
20 | dc@54200000 { |
21 | rgb { | |
22 | status = "okay"; | |
23 | ||
24 | nvidia,panel = <&panel>; | |
25 | }; | |
26 | }; | |
27 | ||
58ecb23f | 28 | hdmi@54280000 { |
20ffbd7d SW |
29 | status = "okay"; |
30 | ||
ad0acf78 | 31 | hdmi-supply = <&vdd_5v0_hdmi>; |
20ffbd7d SW |
32 | vdd-supply = <&hdmi_vdd_reg>; |
33 | pll-supply = <&hdmi_pll_reg>; | |
34 | ||
35 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
3325f1bc SW |
36 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
37 | GPIO_ACTIVE_HIGH>; | |
20ffbd7d SW |
38 | }; |
39 | }; | |
40 | ||
58ecb23f | 41 | pinmux@70000014 { |
ecc295bb SW |
42 | pinctrl-names = "default"; |
43 | pinctrl-0 = <&state_default>; | |
44 | ||
45 | state_default: pinmux { | |
46 | ata { | |
47 | nvidia,pins = "ata"; | |
48 | nvidia,function = "ide"; | |
49 | }; | |
50 | atb { | |
51 | nvidia,pins = "atb", "gma", "gme"; | |
52 | nvidia,function = "sdio4"; | |
53 | }; | |
54 | atc { | |
55 | nvidia,pins = "atc"; | |
56 | nvidia,function = "nand"; | |
57 | }; | |
58 | atd { | |
59 | nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", | |
60 | "spia", "spib", "spic"; | |
61 | nvidia,function = "gmi"; | |
62 | }; | |
63 | cdev1 { | |
64 | nvidia,pins = "cdev1"; | |
65 | nvidia,function = "plla_out"; | |
66 | }; | |
67 | cdev2 { | |
68 | nvidia,pins = "cdev2"; | |
69 | nvidia,function = "pllp_out4"; | |
70 | }; | |
71 | crtp { | |
72 | nvidia,pins = "crtp"; | |
73 | nvidia,function = "crt"; | |
74 | }; | |
75 | csus { | |
76 | nvidia,pins = "csus"; | |
77 | nvidia,function = "vi_sensor_clk"; | |
78 | }; | |
79 | dap1 { | |
80 | nvidia,pins = "dap1"; | |
81 | nvidia,function = "dap1"; | |
82 | }; | |
83 | dap2 { | |
84 | nvidia,pins = "dap2"; | |
85 | nvidia,function = "dap2"; | |
86 | }; | |
87 | dap3 { | |
88 | nvidia,pins = "dap3"; | |
89 | nvidia,function = "dap3"; | |
90 | }; | |
91 | dap4 { | |
92 | nvidia,pins = "dap4"; | |
93 | nvidia,function = "dap4"; | |
94 | }; | |
95 | ddc { | |
96 | nvidia,pins = "ddc"; | |
97 | nvidia,function = "i2c2"; | |
98 | }; | |
99 | dta { | |
100 | nvidia,pins = "dta", "dtd"; | |
101 | nvidia,function = "sdio2"; | |
102 | }; | |
103 | dtb { | |
104 | nvidia,pins = "dtb", "dtc", "dte"; | |
105 | nvidia,function = "rsvd1"; | |
106 | }; | |
107 | dtf { | |
108 | nvidia,pins = "dtf"; | |
109 | nvidia,function = "i2c3"; | |
110 | }; | |
111 | gmc { | |
112 | nvidia,pins = "gmc"; | |
113 | nvidia,function = "uartd"; | |
114 | }; | |
115 | gpu7 { | |
116 | nvidia,pins = "gpu7"; | |
117 | nvidia,function = "rtck"; | |
118 | }; | |
119 | gpv { | |
120 | nvidia,pins = "gpv", "slxa", "slxk"; | |
121 | nvidia,function = "pcie"; | |
122 | }; | |
123 | hdint { | |
124 | nvidia,pins = "hdint", "pta"; | |
125 | nvidia,function = "hdmi"; | |
126 | }; | |
127 | i2cp { | |
128 | nvidia,pins = "i2cp"; | |
129 | nvidia,function = "i2cp"; | |
130 | }; | |
131 | irrx { | |
132 | nvidia,pins = "irrx", "irtx"; | |
133 | nvidia,function = "uarta"; | |
134 | }; | |
135 | kbca { | |
136 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", | |
137 | "kbce", "kbcf"; | |
138 | nvidia,function = "kbc"; | |
139 | }; | |
140 | lcsn { | |
141 | nvidia,pins = "lcsn", "ld0", "ld1", "ld2", | |
142 | "ld3", "ld4", "ld5", "ld6", "ld7", | |
143 | "ld8", "ld9", "ld10", "ld11", "ld12", | |
144 | "ld13", "ld14", "ld15", "ld16", "ld17", | |
145 | "ldc", "ldi", "lhp0", "lhp1", "lhp2", | |
146 | "lhs", "lm0", "lm1", "lpp", "lpw0", | |
147 | "lpw1", "lpw2", "lsc0", "lsc1", "lsck", | |
148 | "lsda", "lsdi", "lspi", "lvp0", "lvp1", | |
149 | "lvs"; | |
150 | nvidia,function = "displaya"; | |
151 | }; | |
152 | owc { | |
153 | nvidia,pins = "owc", "spdi", "spdo", "uac"; | |
154 | nvidia,function = "rsvd2"; | |
155 | }; | |
156 | pmc { | |
157 | nvidia,pins = "pmc"; | |
158 | nvidia,function = "pwr_on"; | |
159 | }; | |
160 | rm { | |
161 | nvidia,pins = "rm"; | |
162 | nvidia,function = "i2c1"; | |
163 | }; | |
164 | sdb { | |
165 | nvidia,pins = "sdb", "sdc", "sdd"; | |
166 | nvidia,function = "pwm"; | |
167 | }; | |
168 | sdio1 { | |
169 | nvidia,pins = "sdio1"; | |
170 | nvidia,function = "sdio1"; | |
171 | }; | |
172 | slxc { | |
173 | nvidia,pins = "slxc", "slxd"; | |
174 | nvidia,function = "spdif"; | |
175 | }; | |
176 | spid { | |
177 | nvidia,pins = "spid", "spie", "spif"; | |
178 | nvidia,function = "spi1"; | |
179 | }; | |
180 | spig { | |
181 | nvidia,pins = "spig", "spih"; | |
182 | nvidia,function = "spi2_alt"; | |
183 | }; | |
184 | uaa { | |
185 | nvidia,pins = "uaa", "uab", "uda"; | |
186 | nvidia,function = "ulpi"; | |
187 | }; | |
188 | uad { | |
189 | nvidia,pins = "uad"; | |
190 | nvidia,function = "irda"; | |
191 | }; | |
192 | uca { | |
193 | nvidia,pins = "uca", "ucb"; | |
194 | nvidia,function = "uartc"; | |
195 | }; | |
196 | conf_ata { | |
197 | nvidia,pins = "ata", "atb", "atc", "atd", "ate", | |
563da21b SW |
198 | "cdev1", "cdev2", "dap1", "dtb", "gma", |
199 | "gmb", "gmc", "gmd", "gme", "gpu7", | |
200 | "gpv", "i2cp", "pta", "rm", "slxa", | |
201 | "slxk", "spia", "spib", "uac"; | |
ba4104e7 LD |
202 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
203 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
ecc295bb | 204 | }; |
ecc295bb SW |
205 | conf_ck32 { |
206 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", | |
207 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; | |
ba4104e7 | 208 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
ecc295bb | 209 | }; |
563da21b SW |
210 | conf_csus { |
211 | nvidia,pins = "csus", "spid", "spif"; | |
ba4104e7 LD |
212 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
213 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
563da21b | 214 | }; |
ecc295bb SW |
215 | conf_crtp { |
216 | nvidia,pins = "crtp", "dap2", "dap3", "dap4", | |
217 | "dtc", "dte", "dtf", "gpu", "sdio1", | |
218 | "slxc", "slxd", "spdi", "spdo", "spig", | |
563da21b | 219 | "uda"; |
ba4104e7 LD |
220 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
221 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
ecc295bb SW |
222 | }; |
223 | conf_ddc { | |
224 | nvidia,pins = "ddc", "dta", "dtd", "kbca", | |
225 | "kbcb", "kbcc", "kbcd", "kbce", "kbcf", | |
226 | "sdc"; | |
ba4104e7 LD |
227 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
228 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
ecc295bb SW |
229 | }; |
230 | conf_hdint { | |
231 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", | |
232 | "lpw1", "lsc1", "lsck", "lsda", "lsdi", | |
233 | "lvp0", "owc", "sdb"; | |
ba4104e7 | 234 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
ecc295bb SW |
235 | }; |
236 | conf_irrx { | |
237 | nvidia,pins = "irrx", "irtx", "sdd", "spic", | |
238 | "spie", "spih", "uaa", "uab", "uad", | |
239 | "uca", "ucb"; | |
ba4104e7 LD |
240 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
241 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
ecc295bb SW |
242 | }; |
243 | conf_lc { | |
244 | nvidia,pins = "lc", "ls"; | |
ba4104e7 | 245 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
ecc295bb SW |
246 | }; |
247 | conf_ld0 { | |
248 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | |
249 | "ld5", "ld6", "ld7", "ld8", "ld9", | |
250 | "ld10", "ld11", "ld12", "ld13", "ld14", | |
251 | "ld15", "ld16", "ld17", "ldi", "lhp0", | |
252 | "lhp1", "lhp2", "lhs", "lm0", "lpp", | |
253 | "lpw0", "lpw2", "lsc0", "lspi", "lvp1", | |
254 | "lvs", "pmc"; | |
ba4104e7 | 255 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
ecc295bb SW |
256 | }; |
257 | conf_ld17_0 { | |
258 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | |
259 | "ld23_22"; | |
ba4104e7 | 260 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
ecc295bb SW |
261 | }; |
262 | }; | |
263 | }; | |
264 | ||
2a5fdc9a SW |
265 | i2s@70002800 { |
266 | status = "okay"; | |
c04abb3a SW |
267 | }; |
268 | ||
269 | serial@70006300 { | |
2a5fdc9a | 270 | status = "okay"; |
c04abb3a SW |
271 | }; |
272 | ||
1d4e0689 TR |
273 | pwm: pwm@7000a000 { |
274 | status = "okay"; | |
275 | }; | |
276 | ||
8e267f3d | 277 | i2c@7000c000 { |
2a5fdc9a | 278 | status = "okay"; |
8e267f3d GL |
279 | clock-frequency = <400000>; |
280 | ||
797acf70 | 281 | wm8903: wm8903@1a { |
8e267f3d GL |
282 | compatible = "wlf,wm8903"; |
283 | reg = <0x1a>; | |
797acf70 | 284 | interrupt-parent = <&gpio>; |
6cecf916 | 285 | interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; |
8e267f3d GL |
286 | |
287 | gpio-controller; | |
288 | #gpio-cells = <2>; | |
289 | ||
797acf70 SW |
290 | micdet-cfg = <0>; |
291 | micdet-delay = <100>; | |
95decf84 | 292 | gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; |
8e267f3d GL |
293 | }; |
294 | }; | |
295 | ||
20ffbd7d | 296 | hdmi_ddc: i2c@7000c400 { |
2a5fdc9a | 297 | status = "okay"; |
20ffbd7d | 298 | clock-frequency = <100000>; |
8e267f3d GL |
299 | }; |
300 | ||
301 | i2c@7000c500 { | |
2a5fdc9a | 302 | status = "okay"; |
8e267f3d GL |
303 | clock-frequency = <400000>; |
304 | }; | |
305 | ||
306 | i2c@7000d000 { | |
2a5fdc9a | 307 | status = "okay"; |
8e267f3d | 308 | clock-frequency = <400000>; |
3cc404de LD |
309 | |
310 | pmic: tps6586x@34 { | |
311 | compatible = "ti,tps6586x"; | |
312 | reg = <0x34>; | |
6cecf916 | 313 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
3cc404de | 314 | |
be972c32 SW |
315 | ti,system-power-controller; |
316 | ||
3cc404de LD |
317 | #gpio-cells = <2>; |
318 | gpio-controller; | |
319 | ||
320 | sys-supply = <&vdd_5v0_reg>; | |
321 | vin-sm0-supply = <&sys_reg>; | |
322 | vin-sm1-supply = <&sys_reg>; | |
323 | vin-sm2-supply = <&sys_reg>; | |
324 | vinldo01-supply = <&sm2_reg>; | |
325 | vinldo23-supply = <&sm2_reg>; | |
326 | vinldo4-supply = <&sm2_reg>; | |
327 | vinldo678-supply = <&sm2_reg>; | |
328 | vinldo9-supply = <&sm2_reg>; | |
329 | ||
330 | regulators { | |
b9c665d7 | 331 | sys_reg: sys { |
3cc404de LD |
332 | regulator-name = "vdd_sys"; |
333 | regulator-always-on; | |
334 | }; | |
335 | ||
b9c665d7 | 336 | sm0 { |
3cc404de LD |
337 | regulator-name = "vdd_sm0,vdd_core"; |
338 | regulator-min-microvolt = <1200000>; | |
339 | regulator-max-microvolt = <1200000>; | |
340 | regulator-always-on; | |
341 | }; | |
342 | ||
b9c665d7 | 343 | sm1 { |
3cc404de LD |
344 | regulator-name = "vdd_sm1,vdd_cpu"; |
345 | regulator-min-microvolt = <1000000>; | |
346 | regulator-max-microvolt = <1000000>; | |
347 | regulator-always-on; | |
348 | }; | |
349 | ||
b9c665d7 | 350 | sm2_reg: sm2 { |
3cc404de LD |
351 | regulator-name = "vdd_sm2,vin_ldo*"; |
352 | regulator-min-microvolt = <3700000>; | |
353 | regulator-max-microvolt = <3700000>; | |
354 | regulator-always-on; | |
355 | }; | |
356 | ||
722afc17 | 357 | pci_clk_reg: ldo0 { |
3cc404de LD |
358 | regulator-name = "vdd_ldo0,vddio_pex_clk"; |
359 | regulator-min-microvolt = <3300000>; | |
360 | regulator-max-microvolt = <3300000>; | |
361 | }; | |
362 | ||
b9c665d7 | 363 | ldo1 { |
3cc404de LD |
364 | regulator-name = "vdd_ldo1,avdd_pll*"; |
365 | regulator-min-microvolt = <1100000>; | |
366 | regulator-max-microvolt = <1100000>; | |
367 | regulator-always-on; | |
368 | }; | |
369 | ||
b9c665d7 | 370 | ldo2 { |
3cc404de LD |
371 | regulator-name = "vdd_ldo2,vdd_rtc"; |
372 | regulator-min-microvolt = <1200000>; | |
373 | regulator-max-microvolt = <1200000>; | |
374 | }; | |
375 | ||
b9c665d7 | 376 | ldo3 { |
3cc404de LD |
377 | regulator-name = "vdd_ldo3,avdd_usb*"; |
378 | regulator-min-microvolt = <3300000>; | |
379 | regulator-max-microvolt = <3300000>; | |
380 | regulator-always-on; | |
381 | }; | |
382 | ||
b9c665d7 | 383 | ldo4 { |
3cc404de LD |
384 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; |
385 | regulator-min-microvolt = <1800000>; | |
386 | regulator-max-microvolt = <1800000>; | |
387 | regulator-always-on; | |
388 | }; | |
389 | ||
b9c665d7 | 390 | ldo5 { |
3cc404de LD |
391 | regulator-name = "vdd_ldo5,vcore_mmc"; |
392 | regulator-min-microvolt = <2850000>; | |
393 | regulator-max-microvolt = <2850000>; | |
394 | regulator-always-on; | |
395 | }; | |
396 | ||
b9c665d7 | 397 | ldo6 { |
3cc404de LD |
398 | regulator-name = "vdd_ldo6,avdd_vdac"; |
399 | regulator-min-microvolt = <1800000>; | |
400 | regulator-max-microvolt = <1800000>; | |
401 | }; | |
402 | ||
20ffbd7d | 403 | hdmi_vdd_reg: ldo7 { |
740418ef | 404 | regulator-name = "vdd_ldo7,avdd_hdmi"; |
3cc404de LD |
405 | regulator-min-microvolt = <3300000>; |
406 | regulator-max-microvolt = <3300000>; | |
407 | }; | |
408 | ||
20ffbd7d | 409 | hdmi_pll_reg: ldo8 { |
3cc404de LD |
410 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; |
411 | regulator-min-microvolt = <1800000>; | |
412 | regulator-max-microvolt = <1800000>; | |
413 | }; | |
414 | ||
b9c665d7 | 415 | ldo9 { |
3cc404de LD |
416 | regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; |
417 | regulator-min-microvolt = <2850000>; | |
418 | regulator-max-microvolt = <2850000>; | |
419 | regulator-always-on; | |
420 | }; | |
421 | ||
b9c665d7 | 422 | ldo_rtc { |
3cc404de LD |
423 | regulator-name = "vdd_rtc_out,vdd_cell"; |
424 | regulator-min-microvolt = <3300000>; | |
425 | regulator-max-microvolt = <3300000>; | |
426 | regulator-always-on; | |
427 | }; | |
428 | }; | |
429 | }; | |
42d2534a TR |
430 | |
431 | temperature-sensor@4c { | |
432 | compatible = "adi,adt7461"; | |
433 | reg = <0x4c>; | |
434 | }; | |
8e267f3d GL |
435 | }; |
436 | ||
58ecb23f | 437 | kbc@7000e200 { |
c0967ce0 LD |
438 | status = "okay"; |
439 | nvidia,debounce-delay-ms = <2>; | |
440 | nvidia,repeat-delay-ms = <160>; | |
441 | nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; | |
442 | nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; | |
6bccbd5e LD |
443 | linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W) |
444 | MATRIX_KEY(0x00, 0x03, KEY_S) | |
445 | MATRIX_KEY(0x00, 0x04, KEY_A) | |
446 | MATRIX_KEY(0x00, 0x05, KEY_Z) | |
447 | MATRIX_KEY(0x00, 0x07, KEY_FN) | |
448 | MATRIX_KEY(0x01, 0x07, KEY_MENU) | |
449 | MATRIX_KEY(0x02, 0x06, KEY_LEFTALT) | |
450 | MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT) | |
451 | MATRIX_KEY(0x03, 0x00, KEY_5) | |
452 | MATRIX_KEY(0x03, 0x01, KEY_4) | |
453 | MATRIX_KEY(0x03, 0x02, KEY_R) | |
454 | MATRIX_KEY(0x03, 0x03, KEY_E) | |
455 | MATRIX_KEY(0x03, 0x04, KEY_F) | |
456 | MATRIX_KEY(0x03, 0x05, KEY_D) | |
457 | MATRIX_KEY(0x03, 0x06, KEY_X) | |
458 | MATRIX_KEY(0x04, 0x00, KEY_7) | |
459 | MATRIX_KEY(0x04, 0x01, KEY_6) | |
460 | MATRIX_KEY(0x04, 0x02, KEY_T) | |
461 | MATRIX_KEY(0x04, 0x03, KEY_H) | |
462 | MATRIX_KEY(0x04, 0x04, KEY_G) | |
463 | MATRIX_KEY(0x04, 0x05, KEY_V) | |
464 | MATRIX_KEY(0x04, 0x06, KEY_C) | |
465 | MATRIX_KEY(0x04, 0x07, KEY_SPACE) | |
466 | MATRIX_KEY(0x05, 0x00, KEY_9) | |
467 | MATRIX_KEY(0x05, 0x01, KEY_8) | |
468 | MATRIX_KEY(0x05, 0x02, KEY_U) | |
469 | MATRIX_KEY(0x05, 0x03, KEY_Y) | |
470 | MATRIX_KEY(0x05, 0x04, KEY_J) | |
471 | MATRIX_KEY(0x05, 0x05, KEY_N) | |
472 | MATRIX_KEY(0x05, 0x06, KEY_B) | |
473 | MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH) | |
474 | MATRIX_KEY(0x06, 0x00, KEY_MINUS) | |
475 | MATRIX_KEY(0x06, 0x01, KEY_0) | |
476 | MATRIX_KEY(0x06, 0x02, KEY_O) | |
477 | MATRIX_KEY(0x06, 0x03, KEY_I) | |
478 | MATRIX_KEY(0x06, 0x04, KEY_L) | |
479 | MATRIX_KEY(0x06, 0x05, KEY_K) | |
480 | MATRIX_KEY(0x06, 0x06, KEY_COMMA) | |
481 | MATRIX_KEY(0x06, 0x07, KEY_M) | |
482 | MATRIX_KEY(0x07, 0x01, KEY_EQUAL) | |
483 | MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE) | |
484 | MATRIX_KEY(0x07, 0x03, KEY_ENTER) | |
485 | MATRIX_KEY(0x07, 0x07, KEY_MENU) | |
486 | MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT) | |
487 | MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT) | |
488 | MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL) | |
489 | MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL) | |
490 | MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE) | |
491 | MATRIX_KEY(0x0B, 0x01, KEY_P) | |
492 | MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE) | |
493 | MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON) | |
494 | MATRIX_KEY(0x0B, 0x04, KEY_SLASH) | |
495 | MATRIX_KEY(0x0B, 0x05, KEY_DOT) | |
496 | MATRIX_KEY(0x0C, 0x00, KEY_F10) | |
497 | MATRIX_KEY(0x0C, 0x01, KEY_F9) | |
498 | MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE) | |
499 | MATRIX_KEY(0x0C, 0x03, KEY_3) | |
500 | MATRIX_KEY(0x0C, 0x04, KEY_2) | |
501 | MATRIX_KEY(0x0C, 0x05, KEY_UP) | |
502 | MATRIX_KEY(0x0C, 0x06, KEY_PRINT) | |
503 | MATRIX_KEY(0x0C, 0x07, KEY_PAUSE) | |
504 | MATRIX_KEY(0x0D, 0x00, KEY_INSERT) | |
505 | MATRIX_KEY(0x0D, 0x01, KEY_DELETE) | |
506 | MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP ) | |
507 | MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN) | |
508 | MATRIX_KEY(0x0D, 0x05, KEY_RIGHT) | |
509 | MATRIX_KEY(0x0D, 0x06, KEY_DOWN) | |
510 | MATRIX_KEY(0x0D, 0x07, KEY_LEFT) | |
511 | MATRIX_KEY(0x0E, 0x00, KEY_F11) | |
512 | MATRIX_KEY(0x0E, 0x01, KEY_F12) | |
513 | MATRIX_KEY(0x0E, 0x02, KEY_F8) | |
514 | MATRIX_KEY(0x0E, 0x03, KEY_Q) | |
515 | MATRIX_KEY(0x0E, 0x04, KEY_F4) | |
516 | MATRIX_KEY(0x0E, 0x05, KEY_F3) | |
517 | MATRIX_KEY(0x0E, 0x06, KEY_1) | |
518 | MATRIX_KEY(0x0E, 0x07, KEY_F7) | |
519 | MATRIX_KEY(0x0F, 0x00, KEY_ESC) | |
520 | MATRIX_KEY(0x0F, 0x01, KEY_GRAVE) | |
521 | MATRIX_KEY(0x0F, 0x02, KEY_F5) | |
522 | MATRIX_KEY(0x0F, 0x03, KEY_TAB) | |
523 | MATRIX_KEY(0x0F, 0x04, KEY_F1) | |
524 | MATRIX_KEY(0x0F, 0x05, KEY_F2) | |
525 | MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK) | |
526 | MATRIX_KEY(0x0F, 0x07, KEY_F6) | |
527 | MATRIX_KEY(0x14, 0x00, KEY_KP7) | |
528 | MATRIX_KEY(0x15, 0x00, KEY_KP9) | |
529 | MATRIX_KEY(0x15, 0x01, KEY_KP8) | |
530 | MATRIX_KEY(0x15, 0x02, KEY_KP4) | |
531 | MATRIX_KEY(0x15, 0x04, KEY_KP1) | |
532 | MATRIX_KEY(0x16, 0x01, KEY_KPSLASH) | |
533 | MATRIX_KEY(0x16, 0x02, KEY_KP6) | |
534 | MATRIX_KEY(0x16, 0x03, KEY_KP5) | |
535 | MATRIX_KEY(0x16, 0x04, KEY_KP3) | |
536 | MATRIX_KEY(0x16, 0x05, KEY_KP2) | |
537 | MATRIX_KEY(0x16, 0x07, KEY_KP0) | |
538 | MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK) | |
539 | MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS) | |
540 | MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS) | |
541 | MATRIX_KEY(0x1B, 0x05, KEY_KPDOT) | |
542 | MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP) | |
543 | MATRIX_KEY(0x1D, 0x03, KEY_HOME) | |
544 | MATRIX_KEY(0x1D, 0x04, KEY_END) | |
545 | MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP) | |
546 | MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN) | |
547 | MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN) | |
548 | MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK) | |
549 | MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK) | |
550 | MATRIX_KEY(0x1E, 0x02, KEY_MUTE) | |
551 | MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>; | |
c0967ce0 LD |
552 | }; |
553 | ||
57899053 SW |
554 | pmc@7000e400 { |
555 | nvidia,invert-interrupt; | |
556 | nvidia,suspend-mode = <1>; | |
557 | nvidia,cpu-pwr-good-time = <5000>; | |
558 | nvidia,cpu-pwr-off-time = <5000>; | |
559 | nvidia,core-pwr-good-time = <3845 3845>; | |
560 | nvidia,core-pwr-off-time = <3875>; | |
561 | nvidia,sys-clock-req-active-high; | |
562 | }; | |
563 | ||
564 | pcie-controller@80003000 { | |
cca8614d TR |
565 | status = "okay"; |
566 | ||
567 | avdd-pex-supply = <&pci_vdd_reg>; | |
568 | vdd-pex-supply = <&pci_vdd_reg>; | |
569 | avdd-pex-pll-supply = <&pci_vdd_reg>; | |
570 | avdd-plle-supply = <&pci_vdd_reg>; | |
571 | vddio-pex-clk-supply = <&pci_clk_reg>; | |
572 | ||
57899053 SW |
573 | pci@1,0 { |
574 | status = "okay"; | |
575 | }; | |
576 | ||
577 | pci@2,0 { | |
578 | status = "okay"; | |
579 | }; | |
580 | }; | |
581 | ||
582 | usb@c5000000 { | |
583 | status = "okay"; | |
584 | }; | |
585 | ||
586 | usb-phy@c5000000 { | |
587 | status = "okay"; | |
588 | }; | |
589 | ||
590 | usb@c5004000 { | |
591 | status = "okay"; | |
592 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) | |
593 | GPIO_ACTIVE_LOW>; | |
594 | }; | |
595 | ||
596 | usb-phy@c5004000 { | |
597 | status = "okay"; | |
598 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) | |
599 | GPIO_ACTIVE_LOW>; | |
600 | }; | |
601 | ||
602 | usb@c5008000 { | |
603 | status = "okay"; | |
604 | }; | |
605 | ||
606 | usb-phy@c5008000 { | |
607 | status = "okay"; | |
608 | }; | |
609 | ||
610 | sdhci@c8000200 { | |
611 | status = "okay"; | |
612 | cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; | |
613 | wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; | |
614 | power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; | |
615 | bus-width = <4>; | |
616 | }; | |
617 | ||
618 | sdhci@c8000600 { | |
619 | status = "okay"; | |
620 | cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; | |
621 | wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; | |
622 | power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; | |
623 | bus-width = <8>; | |
624 | }; | |
625 | ||
1d4e0689 TR |
626 | backlight: backlight { |
627 | compatible = "pwm-backlight"; | |
628 | ||
629 | enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>; | |
630 | power-supply = <&vdd_bl_reg>; | |
631 | pwms = <&pwm 0 5000000>; | |
632 | ||
633 | brightness-levels = <0 4 8 16 32 64 128 255>; | |
634 | default-brightness-level = <6>; | |
635 | }; | |
636 | ||
57899053 SW |
637 | clocks { |
638 | compatible = "simple-bus"; | |
639 | #address-cells = <1>; | |
640 | #size-cells = <0>; | |
641 | ||
642 | clk32k_in: clock@0 { | |
643 | compatible = "fixed-clock"; | |
644 | reg=<0>; | |
645 | #clock-cells = <0>; | |
646 | clock-frequency = <32768>; | |
647 | }; | |
648 | }; | |
649 | ||
650 | gpio-keys { | |
651 | compatible = "gpio-keys"; | |
652 | ||
653 | power { | |
654 | label = "Power"; | |
655 | gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; | |
6bccbd5e | 656 | linux,code = <KEY_POWER>; |
57899053 SW |
657 | gpio-key,wakeup; |
658 | }; | |
659 | }; | |
660 | ||
1d4e0689 TR |
661 | panel: panel { |
662 | compatible = "auo,b101aw03", "simple-panel"; | |
663 | ||
664 | power-supply = <&vdd_pnl_reg>; | |
665 | enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; | |
666 | ||
667 | backlight = <&backlight>; | |
668 | }; | |
669 | ||
3cc404de LD |
670 | regulators { |
671 | compatible = "simple-bus"; | |
672 | #address-cells = <1>; | |
673 | #size-cells = <0>; | |
674 | ||
675 | vdd_5v0_reg: regulator@0 { | |
676 | compatible = "regulator-fixed"; | |
677 | reg = <0>; | |
678 | regulator-name = "vdd_5v0"; | |
679 | regulator-min-microvolt = <5000000>; | |
680 | regulator-max-microvolt = <5000000>; | |
681 | regulator-always-on; | |
682 | }; | |
683 | ||
684 | regulator@1 { | |
685 | compatible = "regulator-fixed"; | |
686 | reg = <1>; | |
687 | regulator-name = "vdd_1v5"; | |
688 | regulator-min-microvolt = <1500000>; | |
689 | regulator-max-microvolt = <1500000>; | |
3325f1bc | 690 | gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; |
3cc404de LD |
691 | }; |
692 | ||
693 | regulator@2 { | |
694 | compatible = "regulator-fixed"; | |
695 | reg = <2>; | |
696 | regulator-name = "vdd_1v2"; | |
697 | regulator-min-microvolt = <1200000>; | |
698 | regulator-max-microvolt = <1200000>; | |
3325f1bc | 699 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; |
3cc404de LD |
700 | enable-active-high; |
701 | }; | |
702 | ||
722afc17 | 703 | pci_vdd_reg: regulator@3 { |
3cc404de LD |
704 | compatible = "regulator-fixed"; |
705 | reg = <3>; | |
706 | regulator-name = "vdd_1v05"; | |
707 | regulator-min-microvolt = <1050000>; | |
708 | regulator-max-microvolt = <1050000>; | |
3325f1bc | 709 | gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; |
3cc404de | 710 | enable-active-high; |
3cc404de LD |
711 | }; |
712 | ||
1d4e0689 | 713 | vdd_pnl_reg: regulator@4 { |
3cc404de LD |
714 | compatible = "regulator-fixed"; |
715 | reg = <4>; | |
716 | regulator-name = "vdd_pnl"; | |
717 | regulator-min-microvolt = <2800000>; | |
718 | regulator-max-microvolt = <2800000>; | |
3325f1bc | 719 | gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; |
3cc404de LD |
720 | enable-active-high; |
721 | }; | |
722 | ||
1d4e0689 | 723 | vdd_bl_reg: regulator@5 { |
3cc404de LD |
724 | compatible = "regulator-fixed"; |
725 | reg = <5>; | |
726 | regulator-name = "vdd_bl"; | |
727 | regulator-min-microvolt = <2800000>; | |
728 | regulator-max-microvolt = <2800000>; | |
3325f1bc | 729 | gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; |
3cc404de LD |
730 | enable-active-high; |
731 | }; | |
ad0acf78 TR |
732 | |
733 | vdd_5v0_hdmi: regulator@6 { | |
734 | compatible = "regulator-fixed"; | |
735 | reg = <6>; | |
736 | regulator-name = "VDDIO_HDMI"; | |
737 | regulator-min-microvolt = <5000000>; | |
738 | regulator-max-microvolt = <5000000>; | |
739 | gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>; | |
740 | enable-active-high; | |
741 | vin-supply = <&vdd_5v0_reg>; | |
742 | }; | |
3cc404de LD |
743 | }; |
744 | ||
c04abb3a SW |
745 | sound { |
746 | compatible = "nvidia,tegra-audio-wm8903-harmony", | |
747 | "nvidia,tegra-audio-wm8903"; | |
748 | nvidia,model = "NVIDIA Tegra Harmony"; | |
749 | ||
750 | nvidia,audio-routing = | |
751 | "Headphone Jack", "HPOUTR", | |
752 | "Headphone Jack", "HPOUTL", | |
753 | "Int Spk", "ROP", | |
754 | "Int Spk", "RON", | |
755 | "Int Spk", "LOP", | |
756 | "Int Spk", "LON", | |
757 | "Mic Jack", "MICBIAS", | |
758 | "IN1L", "Mic Jack"; | |
759 | ||
760 | nvidia,i2s-controller = <&tegra_i2s1>; | |
761 | nvidia,audio-codec = <&wm8903>; | |
762 | ||
3325f1bc SW |
763 | nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
764 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) | |
765 | GPIO_ACTIVE_HIGH>; | |
766 | nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) | |
767 | GPIO_ACTIVE_HIGH>; | |
768 | nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) | |
769 | GPIO_ACTIVE_HIGH>; | |
f9cd2b3b | 770 | |
885a8cfa HD |
771 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
772 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | |
773 | <&tegra_car TEGRA20_CLK_CDEV1>; | |
f9cd2b3b | 774 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
aa607ebf | 775 | }; |
8e267f3d | 776 | }; |