]>
Commit | Line | Data |
---|---|---|
1bd0bd49 | 1 | #include "tegra20.dtsi" |
307e28ee TR |
2 | |
3 | / { | |
4 | model = "Avionic Design Tamonten SOM"; | |
5 | compatible = "ad,tamonten", "nvidia,tegra20"; | |
6 | ||
553c0a20 SW |
7 | aliases { |
8 | rtc0 = "/i2c@7000d000/tps6586x@34"; | |
9 | rtc1 = "/rtc@7000e000"; | |
10 | }; | |
11 | ||
307e28ee TR |
12 | memory { |
13 | reg = <0x00000000 0x20000000>; | |
14 | }; | |
15 | ||
58ecb23f SW |
16 | host1x@50000000 { |
17 | hdmi@54280000 { | |
e6f09796 TR |
18 | vdd-supply = <&hdmi_vdd_reg>; |
19 | pll-supply = <&hdmi_pll_reg>; | |
20 | ||
21 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
3325f1bc SW |
22 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
23 | GPIO_ACTIVE_HIGH>; | |
e6f09796 TR |
24 | }; |
25 | }; | |
26 | ||
58ecb23f | 27 | pinmux@70000014 { |
307e28ee TR |
28 | pinctrl-names = "default"; |
29 | pinctrl-0 = <&state_default>; | |
30 | ||
31 | state_default: pinmux { | |
32 | ata { | |
33 | nvidia,pins = "ata"; | |
34 | nvidia,function = "ide"; | |
35 | }; | |
36 | atb { | |
37 | nvidia,pins = "atb", "gma", "gme"; | |
38 | nvidia,function = "sdio4"; | |
39 | }; | |
40 | atc { | |
41 | nvidia,pins = "atc"; | |
42 | nvidia,function = "nand"; | |
43 | }; | |
44 | atd { | |
45 | nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", | |
46 | "spia", "spib", "spic"; | |
47 | nvidia,function = "gmi"; | |
48 | }; | |
49 | cdev1 { | |
50 | nvidia,pins = "cdev1"; | |
51 | nvidia,function = "plla_out"; | |
52 | }; | |
53 | cdev2 { | |
54 | nvidia,pins = "cdev2"; | |
55 | nvidia,function = "pllp_out4"; | |
56 | }; | |
57 | crtp { | |
58 | nvidia,pins = "crtp"; | |
59 | nvidia,function = "crt"; | |
60 | }; | |
61 | csus { | |
62 | nvidia,pins = "csus"; | |
63 | nvidia,function = "vi_sensor_clk"; | |
64 | }; | |
65 | dap1 { | |
66 | nvidia,pins = "dap1"; | |
67 | nvidia,function = "dap1"; | |
68 | }; | |
69 | dap2 { | |
70 | nvidia,pins = "dap2"; | |
71 | nvidia,function = "dap2"; | |
72 | }; | |
73 | dap3 { | |
74 | nvidia,pins = "dap3"; | |
75 | nvidia,function = "dap3"; | |
76 | }; | |
77 | dap4 { | |
78 | nvidia,pins = "dap4"; | |
79 | nvidia,function = "dap4"; | |
80 | }; | |
307e28ee TR |
81 | dta { |
82 | nvidia,pins = "dta", "dtd"; | |
83 | nvidia,function = "sdio2"; | |
84 | }; | |
85 | dtb { | |
86 | nvidia,pins = "dtb", "dtc", "dte"; | |
87 | nvidia,function = "rsvd1"; | |
88 | }; | |
89 | dtf { | |
90 | nvidia,pins = "dtf"; | |
91 | nvidia,function = "i2c3"; | |
92 | }; | |
93 | gmc { | |
94 | nvidia,pins = "gmc"; | |
95 | nvidia,function = "uartd"; | |
96 | }; | |
97 | gpu7 { | |
98 | nvidia,pins = "gpu7"; | |
99 | nvidia,function = "rtck"; | |
100 | }; | |
101 | gpv { | |
102 | nvidia,pins = "gpv", "slxa", "slxk"; | |
103 | nvidia,function = "pcie"; | |
104 | }; | |
105 | hdint { | |
ec319903 | 106 | nvidia,pins = "hdint"; |
307e28ee TR |
107 | nvidia,function = "hdmi"; |
108 | }; | |
109 | i2cp { | |
110 | nvidia,pins = "i2cp"; | |
111 | nvidia,function = "i2cp"; | |
112 | }; | |
113 | irrx { | |
114 | nvidia,pins = "irrx", "irtx"; | |
115 | nvidia,function = "uarta"; | |
116 | }; | |
117 | kbca { | |
118 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", | |
119 | "kbce", "kbcf"; | |
120 | nvidia,function = "kbc"; | |
121 | }; | |
122 | lcsn { | |
123 | nvidia,pins = "lcsn", "ld0", "ld1", "ld2", | |
124 | "ld3", "ld4", "ld5", "ld6", "ld7", | |
125 | "ld8", "ld9", "ld10", "ld11", "ld12", | |
126 | "ld13", "ld14", "ld15", "ld16", "ld17", | |
127 | "ldc", "ldi", "lhp0", "lhp1", "lhp2", | |
128 | "lhs", "lm0", "lm1", "lpp", "lpw0", | |
129 | "lpw1", "lpw2", "lsc0", "lsc1", "lsck", | |
130 | "lsda", "lsdi", "lspi", "lvp0", "lvp1", | |
131 | "lvs"; | |
132 | nvidia,function = "displaya"; | |
133 | }; | |
134 | owc { | |
135 | nvidia,pins = "owc", "spdi", "spdo", "uac"; | |
136 | nvidia,function = "rsvd2"; | |
137 | }; | |
138 | pmc { | |
139 | nvidia,pins = "pmc"; | |
140 | nvidia,function = "pwr_on"; | |
141 | }; | |
142 | rm { | |
143 | nvidia,pins = "rm"; | |
144 | nvidia,function = "i2c1"; | |
145 | }; | |
146 | sdb { | |
147 | nvidia,pins = "sdb", "sdc", "sdd"; | |
148 | nvidia,function = "pwm"; | |
149 | }; | |
150 | sdio1 { | |
151 | nvidia,pins = "sdio1"; | |
152 | nvidia,function = "sdio1"; | |
153 | }; | |
154 | slxc { | |
155 | nvidia,pins = "slxc", "slxd"; | |
156 | nvidia,function = "spdif"; | |
157 | }; | |
158 | spid { | |
159 | nvidia,pins = "spid", "spie", "spif"; | |
160 | nvidia,function = "spi1"; | |
161 | }; | |
162 | spig { | |
163 | nvidia,pins = "spig", "spih"; | |
164 | nvidia,function = "spi2_alt"; | |
165 | }; | |
166 | uaa { | |
167 | nvidia,pins = "uaa", "uab", "uda"; | |
168 | nvidia,function = "ulpi"; | |
169 | }; | |
170 | uad { | |
171 | nvidia,pins = "uad"; | |
172 | nvidia,function = "irda"; | |
173 | }; | |
174 | uca { | |
175 | nvidia,pins = "uca", "ucb"; | |
176 | nvidia,function = "uartc"; | |
177 | }; | |
178 | conf_ata { | |
179 | nvidia,pins = "ata", "atb", "atc", "atd", "ate", | |
180 | "cdev1", "cdev2", "dap1", "dtb", "gma", | |
181 | "gmb", "gmc", "gmd", "gme", "gpu7", | |
182 | "gpv", "i2cp", "pta", "rm", "slxa", | |
183 | "slxk", "spia", "spib", "uac"; | |
ba4104e7 LD |
184 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
185 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
307e28ee TR |
186 | }; |
187 | conf_ck32 { | |
188 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", | |
189 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; | |
ba4104e7 | 190 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
307e28ee TR |
191 | }; |
192 | conf_csus { | |
193 | nvidia,pins = "csus", "spid", "spif"; | |
ba4104e7 LD |
194 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
195 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
307e28ee TR |
196 | }; |
197 | conf_crtp { | |
198 | nvidia,pins = "crtp", "dap2", "dap3", "dap4", | |
199 | "dtc", "dte", "dtf", "gpu", "sdio1", | |
200 | "slxc", "slxd", "spdi", "spdo", "spig", | |
201 | "uda"; | |
ba4104e7 LD |
202 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
203 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
307e28ee TR |
204 | }; |
205 | conf_ddc { | |
206 | nvidia,pins = "ddc", "dta", "dtd", "kbca", | |
207 | "kbcb", "kbcc", "kbcd", "kbce", "kbcf", | |
208 | "sdc"; | |
ba4104e7 LD |
209 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
210 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
307e28ee TR |
211 | }; |
212 | conf_hdint { | |
213 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", | |
214 | "lpw1", "lsc1", "lsck", "lsda", "lsdi", | |
215 | "lvp0", "owc", "sdb"; | |
ba4104e7 | 216 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
307e28ee TR |
217 | }; |
218 | conf_irrx { | |
219 | nvidia,pins = "irrx", "irtx", "sdd", "spic", | |
220 | "spie", "spih", "uaa", "uab", "uad", | |
221 | "uca", "ucb"; | |
ba4104e7 LD |
222 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
223 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
307e28ee TR |
224 | }; |
225 | conf_lc { | |
226 | nvidia,pins = "lc", "ls"; | |
ba4104e7 | 227 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
307e28ee TR |
228 | }; |
229 | conf_ld0 { | |
230 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | |
231 | "ld5", "ld6", "ld7", "ld8", "ld9", | |
232 | "ld10", "ld11", "ld12", "ld13", "ld14", | |
233 | "ld15", "ld16", "ld17", "ldi", "lhp0", | |
234 | "lhp1", "lhp2", "lhs", "lm0", "lpp", | |
235 | "lpw0", "lpw2", "lsc0", "lspi", "lvp1", | |
236 | "lvs", "pmc"; | |
ba4104e7 | 237 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
307e28ee TR |
238 | }; |
239 | conf_ld17_0 { | |
240 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | |
241 | "ld23_22"; | |
ba4104e7 | 242 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
307e28ee TR |
243 | }; |
244 | }; | |
ec319903 TR |
245 | |
246 | state_i2cmux_ddc: pinmux_i2cmux_ddc { | |
247 | ddc { | |
248 | nvidia,pins = "ddc"; | |
249 | nvidia,function = "i2c2"; | |
250 | }; | |
251 | pta { | |
252 | nvidia,pins = "pta"; | |
253 | nvidia,function = "rsvd4"; | |
254 | }; | |
255 | }; | |
256 | ||
257 | state_i2cmux_pta: pinmux_i2cmux_pta { | |
258 | ddc { | |
259 | nvidia,pins = "ddc"; | |
260 | nvidia,function = "rsvd4"; | |
261 | }; | |
262 | pta { | |
263 | nvidia,pins = "pta"; | |
264 | nvidia,function = "i2c2"; | |
265 | }; | |
266 | }; | |
267 | ||
268 | state_i2cmux_idle: pinmux_i2cmux_idle { | |
269 | ddc { | |
270 | nvidia,pins = "ddc"; | |
271 | nvidia,function = "rsvd4"; | |
272 | }; | |
273 | pta { | |
274 | nvidia,pins = "pta"; | |
275 | nvidia,function = "rsvd4"; | |
276 | }; | |
277 | }; | |
307e28ee TR |
278 | }; |
279 | ||
280 | i2s@70002800 { | |
281 | status = "okay"; | |
282 | }; | |
283 | ||
284 | serial@70006300 { | |
307e28ee TR |
285 | status = "okay"; |
286 | }; | |
287 | ||
288 | i2c@7000c000 { | |
289 | clock-frequency = <400000>; | |
290 | status = "okay"; | |
291 | }; | |
292 | ||
ec319903 TR |
293 | i2c@7000c400 { |
294 | clock-frequency = <100000>; | |
295 | status = "okay"; | |
296 | }; | |
297 | ||
298 | i2cmux { | |
299 | compatible = "i2c-mux-pinctrl"; | |
300 | #address-cells = <1>; | |
301 | #size-cells = <0>; | |
302 | ||
303 | i2c-parent = <&{/i2c@7000c400}>; | |
304 | ||
305 | pinctrl-names = "ddc", "pta", "idle"; | |
306 | pinctrl-0 = <&state_i2cmux_ddc>; | |
307 | pinctrl-1 = <&state_i2cmux_pta>; | |
308 | pinctrl-2 = <&state_i2cmux_idle>; | |
309 | ||
e6f09796 | 310 | hdmi_ddc: i2c@0 { |
ec319903 TR |
311 | reg = <0>; |
312 | #address-cells = <1>; | |
313 | #size-cells = <0>; | |
314 | }; | |
315 | ||
316 | i2c@1 { | |
317 | reg = <1>; | |
318 | #address-cells = <1>; | |
319 | #size-cells = <0>; | |
320 | }; | |
321 | }; | |
322 | ||
307e28ee TR |
323 | i2c@7000d000 { |
324 | clock-frequency = <400000>; | |
325 | status = "okay"; | |
326 | ||
327 | pmic: tps6586x@34 { | |
328 | compatible = "ti,tps6586x"; | |
329 | reg = <0x34>; | |
6cecf916 | 330 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
307e28ee TR |
331 | |
332 | ti,system-power-controller; | |
333 | ||
334 | #gpio-cells = <2>; | |
335 | gpio-controller; | |
336 | ||
337 | sys-supply = <&vdd_5v0_reg>; | |
338 | vin-sm0-supply = <&sys_reg>; | |
339 | vin-sm1-supply = <&sys_reg>; | |
340 | vin-sm2-supply = <&sys_reg>; | |
341 | vinldo01-supply = <&sm2_reg>; | |
342 | vinldo23-supply = <&sm2_reg>; | |
343 | vinldo4-supply = <&sm2_reg>; | |
344 | vinldo678-supply = <&sm2_reg>; | |
345 | vinldo9-supply = <&sm2_reg>; | |
346 | ||
347 | regulators { | |
b9c665d7 | 348 | sys_reg: sys { |
307e28ee TR |
349 | regulator-name = "vdd_sys"; |
350 | regulator-always-on; | |
351 | }; | |
352 | ||
b9c665d7 | 353 | sm0 { |
307e28ee TR |
354 | regulator-name = "vdd_sys_sm0,vdd_core"; |
355 | regulator-min-microvolt = <1200000>; | |
356 | regulator-max-microvolt = <1200000>; | |
357 | regulator-always-on; | |
358 | }; | |
359 | ||
b9c665d7 | 360 | sm1 { |
307e28ee TR |
361 | regulator-name = "vdd_sys_sm1,vdd_cpu"; |
362 | regulator-min-microvolt = <1000000>; | |
363 | regulator-max-microvolt = <1000000>; | |
364 | regulator-always-on; | |
365 | }; | |
366 | ||
b9c665d7 | 367 | sm2_reg: sm2 { |
307e28ee TR |
368 | regulator-name = "vdd_sys_sm2,vin_ldo*"; |
369 | regulator-min-microvolt = <3700000>; | |
370 | regulator-max-microvolt = <3700000>; | |
371 | regulator-always-on; | |
372 | }; | |
373 | ||
1b2d6b84 | 374 | pci_clk_reg: ldo0 { |
307e28ee TR |
375 | regulator-name = "vdd_ldo0,vddio_pex_clk"; |
376 | regulator-min-microvolt = <3300000>; | |
377 | regulator-max-microvolt = <3300000>; | |
378 | }; | |
379 | ||
b9c665d7 | 380 | ldo1 { |
307e28ee TR |
381 | regulator-name = "vdd_ldo1,avdd_pll*"; |
382 | regulator-min-microvolt = <1100000>; | |
383 | regulator-max-microvolt = <1100000>; | |
384 | regulator-always-on; | |
385 | }; | |
386 | ||
b9c665d7 | 387 | ldo2 { |
307e28ee TR |
388 | regulator-name = "vdd_ldo2,vdd_rtc"; |
389 | regulator-min-microvolt = <1200000>; | |
390 | regulator-max-microvolt = <1200000>; | |
391 | }; | |
392 | ||
b9c665d7 | 393 | ldo3 { |
307e28ee TR |
394 | regulator-name = "vdd_ldo3,avdd_usb*"; |
395 | regulator-min-microvolt = <3300000>; | |
396 | regulator-max-microvolt = <3300000>; | |
397 | regulator-always-on; | |
398 | }; | |
399 | ||
b9c665d7 | 400 | ldo4 { |
307e28ee TR |
401 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; |
402 | regulator-min-microvolt = <1800000>; | |
403 | regulator-max-microvolt = <1800000>; | |
404 | regulator-always-on; | |
405 | }; | |
406 | ||
b9c665d7 | 407 | ldo5 { |
307e28ee TR |
408 | regulator-name = "vdd_ldo5,vcore_mmc"; |
409 | regulator-min-microvolt = <2850000>; | |
410 | regulator-max-microvolt = <2850000>; | |
411 | }; | |
412 | ||
b9c665d7 | 413 | ldo6 { |
307e28ee TR |
414 | regulator-name = "vdd_ldo6,avdd_vdac"; |
415 | /* | |
416 | * According to the Tegra 2 Automotive | |
417 | * DataSheet, a typical value for this | |
418 | * would be 2.8V, but the PMIC only | |
419 | * supports 2.85V. | |
420 | */ | |
421 | regulator-min-microvolt = <2850000>; | |
422 | regulator-max-microvolt = <2850000>; | |
423 | }; | |
424 | ||
e6f09796 | 425 | hdmi_vdd_reg: ldo7 { |
307e28ee TR |
426 | regulator-name = "vdd_ldo7,avdd_hdmi"; |
427 | regulator-min-microvolt = <3300000>; | |
428 | regulator-max-microvolt = <3300000>; | |
429 | }; | |
430 | ||
e6f09796 | 431 | hdmi_pll_reg: ldo8 { |
307e28ee TR |
432 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; |
433 | regulator-min-microvolt = <1800000>; | |
434 | regulator-max-microvolt = <1800000>; | |
435 | }; | |
436 | ||
b9c665d7 | 437 | ldo9 { |
307e28ee TR |
438 | regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; |
439 | /* | |
440 | * According to the Tegra 2 Automotive | |
441 | * DataSheet, a typical value for this | |
442 | * would be 2.8V, but the PMIC only | |
443 | * supports 2.85V. | |
444 | */ | |
445 | regulator-min-microvolt = <2850000>; | |
446 | regulator-max-microvolt = <2850000>; | |
447 | regulator-always-on; | |
448 | }; | |
449 | ||
b9c665d7 | 450 | ldo_rtc { |
307e28ee TR |
451 | regulator-name = "vdd_rtc_out"; |
452 | regulator-min-microvolt = <3300000>; | |
453 | regulator-max-microvolt = <3300000>; | |
454 | regulator-always-on; | |
455 | }; | |
456 | }; | |
457 | }; | |
840a4080 TR |
458 | |
459 | temperature-sensor@4c { | |
460 | compatible = "onnn,nct1008"; | |
461 | reg = <0x4c>; | |
462 | }; | |
307e28ee TR |
463 | }; |
464 | ||
58ecb23f | 465 | pmc@7000e400 { |
307e28ee | 466 | nvidia,invert-interrupt; |
47d2d63b | 467 | nvidia,suspend-mode = <1>; |
a44a019d JL |
468 | nvidia,cpu-pwr-good-time = <5000>; |
469 | nvidia,cpu-pwr-off-time = <5000>; | |
470 | nvidia,core-pwr-good-time = <3845 3845>; | |
471 | nvidia,core-pwr-off-time = <3875>; | |
472 | nvidia,sys-clock-req-active-high; | |
307e28ee TR |
473 | }; |
474 | ||
58ecb23f | 475 | pcie-controller@80003000 { |
1b2d6b84 TR |
476 | pex-clk-supply = <&pci_clk_reg>; |
477 | vdd-supply = <&pci_vdd_reg>; | |
478 | }; | |
479 | ||
307e28ee TR |
480 | usb@c5008000 { |
481 | status = "okay"; | |
482 | }; | |
483 | ||
4c94c8b5 VB |
484 | usb-phy@c5008000 { |
485 | status = "okay"; | |
486 | }; | |
487 | ||
307e28ee | 488 | sdhci@c8000600 { |
3325f1bc SW |
489 | cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; |
490 | wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; | |
307e28ee TR |
491 | bus-width = <4>; |
492 | status = "okay"; | |
493 | }; | |
494 | ||
7021d122 JL |
495 | clocks { |
496 | compatible = "simple-bus"; | |
497 | #address-cells = <1>; | |
498 | #size-cells = <0>; | |
499 | ||
58ecb23f | 500 | clk32k_in: clock@0 { |
7021d122 JL |
501 | compatible = "fixed-clock"; |
502 | reg=<0>; | |
503 | #clock-cells = <0>; | |
504 | clock-frequency = <32768>; | |
505 | }; | |
506 | }; | |
507 | ||
307e28ee TR |
508 | regulators { |
509 | compatible = "simple-bus"; | |
510 | ||
511 | #address-cells = <1>; | |
512 | #size-cells = <0>; | |
513 | ||
514 | vdd_5v0_reg: regulator@0 { | |
515 | compatible = "regulator-fixed"; | |
516 | reg = <0>; | |
517 | regulator-name = "vdd_5v0"; | |
518 | regulator-min-microvolt = <5000000>; | |
519 | regulator-max-microvolt = <5000000>; | |
520 | regulator-always-on; | |
521 | }; | |
1b2d6b84 TR |
522 | |
523 | pci_vdd_reg: regulator@1 { | |
524 | compatible = "regulator-fixed"; | |
525 | reg = <1>; | |
526 | regulator-name = "vdd_1v05"; | |
527 | regulator-min-microvolt = <1050000>; | |
528 | regulator-max-microvolt = <1050000>; | |
529 | gpio = <&pmic 2 0>; | |
530 | enable-active-high; | |
531 | }; | |
307e28ee TR |
532 | }; |
533 | }; |