]>
Commit | Line | Data |
---|---|---|
add29e61 PDS |
1 | /dts-v1/; |
2 | ||
6bccbd5e | 3 | #include <dt-bindings/input/input.h> |
1bd0bd49 | 4 | #include "tegra20.dtsi" |
add29e61 PDS |
5 | |
6 | / { | |
8fef5dff | 7 | model = "NVIDIA Tegra20 Ventana evaluation board"; |
add29e61 PDS |
8 | compatible = "nvidia,ventana", "nvidia,tegra20"; |
9 | ||
553c0a20 SW |
10 | aliases { |
11 | rtc0 = "/i2c@7000d000/tps6586x@34"; | |
12 | rtc1 = "/rtc@7000e000"; | |
13 | }; | |
14 | ||
add29e61 | 15 | memory { |
95decf84 | 16 | reg = <0x00000000 0x40000000>; |
add29e61 PDS |
17 | }; |
18 | ||
58ecb23f | 19 | host1x@50000000 { |
1771a254 SW |
20 | dc@54200000 { |
21 | rgb { | |
22 | status = "okay"; | |
23 | ||
24 | nvidia,panel = <&panel>; | |
25 | }; | |
26 | }; | |
27 | ||
58ecb23f | 28 | hdmi@54280000 { |
97d5520f SW |
29 | status = "okay"; |
30 | ||
31 | vdd-supply = <&hdmi_vdd_reg>; | |
32 | pll-supply = <&hdmi_pll_reg>; | |
33 | ||
34 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
3325f1bc SW |
35 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
36 | GPIO_ACTIVE_HIGH>; | |
97d5520f SW |
37 | }; |
38 | }; | |
39 | ||
58ecb23f | 40 | pinmux@70000014 { |
ecc295bb SW |
41 | pinctrl-names = "default"; |
42 | pinctrl-0 = <&state_default>; | |
43 | ||
44 | state_default: pinmux { | |
45 | ata { | |
46 | nvidia,pins = "ata"; | |
47 | nvidia,function = "ide"; | |
48 | }; | |
49 | atb { | |
50 | nvidia,pins = "atb", "gma", "gme"; | |
51 | nvidia,function = "sdio4"; | |
52 | }; | |
53 | atc { | |
54 | nvidia,pins = "atc"; | |
55 | nvidia,function = "nand"; | |
56 | }; | |
57 | atd { | |
58 | nvidia,pins = "atd", "ate", "gmb", "spia", | |
59 | "spib", "spic"; | |
60 | nvidia,function = "gmi"; | |
61 | }; | |
62 | cdev1 { | |
63 | nvidia,pins = "cdev1"; | |
64 | nvidia,function = "plla_out"; | |
65 | }; | |
66 | cdev2 { | |
67 | nvidia,pins = "cdev2"; | |
68 | nvidia,function = "pllp_out4"; | |
69 | }; | |
70 | crtp { | |
71 | nvidia,pins = "crtp", "lm1"; | |
72 | nvidia,function = "crt"; | |
73 | }; | |
74 | csus { | |
75 | nvidia,pins = "csus"; | |
76 | nvidia,function = "vi_sensor_clk"; | |
77 | }; | |
78 | dap1 { | |
79 | nvidia,pins = "dap1"; | |
80 | nvidia,function = "dap1"; | |
81 | }; | |
82 | dap2 { | |
83 | nvidia,pins = "dap2"; | |
84 | nvidia,function = "dap2"; | |
85 | }; | |
86 | dap3 { | |
87 | nvidia,pins = "dap3"; | |
88 | nvidia,function = "dap3"; | |
89 | }; | |
90 | dap4 { | |
91 | nvidia,pins = "dap4"; | |
92 | nvidia,function = "dap4"; | |
93 | }; | |
ecc295bb SW |
94 | dta { |
95 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; | |
96 | nvidia,function = "vi"; | |
97 | }; | |
98 | dtf { | |
99 | nvidia,pins = "dtf"; | |
100 | nvidia,function = "i2c3"; | |
101 | }; | |
102 | gmc { | |
103 | nvidia,pins = "gmc"; | |
104 | nvidia,function = "uartd"; | |
105 | }; | |
106 | gmd { | |
107 | nvidia,pins = "gmd"; | |
108 | nvidia,function = "sflash"; | |
109 | }; | |
110 | gpu { | |
111 | nvidia,pins = "gpu"; | |
112 | nvidia,function = "pwm"; | |
113 | }; | |
114 | gpu7 { | |
115 | nvidia,pins = "gpu7"; | |
116 | nvidia,function = "rtck"; | |
117 | }; | |
118 | gpv { | |
119 | nvidia,pins = "gpv", "slxa", "slxk"; | |
120 | nvidia,function = "pcie"; | |
121 | }; | |
122 | hdint { | |
cf633464 | 123 | nvidia,pins = "hdint"; |
ecc295bb SW |
124 | nvidia,function = "hdmi"; |
125 | }; | |
126 | i2cp { | |
127 | nvidia,pins = "i2cp"; | |
128 | nvidia,function = "i2cp"; | |
129 | }; | |
130 | irrx { | |
131 | nvidia,pins = "irrx", "irtx"; | |
132 | nvidia,function = "uartb"; | |
133 | }; | |
134 | kbca { | |
135 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", | |
136 | "kbce", "kbcf"; | |
137 | nvidia,function = "kbc"; | |
138 | }; | |
139 | lcsn { | |
140 | nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", | |
141 | "lsdi", "lvp0"; | |
142 | nvidia,function = "rsvd4"; | |
143 | }; | |
144 | ld0 { | |
145 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | |
146 | "ld5", "ld6", "ld7", "ld8", "ld9", | |
147 | "ld10", "ld11", "ld12", "ld13", "ld14", | |
148 | "ld15", "ld16", "ld17", "ldi", "lhp0", | |
149 | "lhp1", "lhp2", "lhs", "lpp", "lpw0", | |
150 | "lpw2", "lsc0", "lsc1", "lsck", "lsda", | |
151 | "lspi", "lvp1", "lvs"; | |
152 | nvidia,function = "displaya"; | |
153 | }; | |
cf633464 MZ |
154 | owc { |
155 | nvidia,pins = "owc", "spdi", "spdo", "uac"; | |
156 | nvidia,function = "rsvd2"; | |
157 | }; | |
ecc295bb SW |
158 | pmc { |
159 | nvidia,pins = "pmc"; | |
160 | nvidia,function = "pwr_on"; | |
161 | }; | |
162 | rm { | |
163 | nvidia,pins = "rm"; | |
164 | nvidia,function = "i2c1"; | |
165 | }; | |
166 | sdb { | |
167 | nvidia,pins = "sdb", "sdc", "sdd", "slxc"; | |
168 | nvidia,function = "sdio3"; | |
169 | }; | |
170 | sdio1 { | |
171 | nvidia,pins = "sdio1"; | |
172 | nvidia,function = "sdio1"; | |
173 | }; | |
174 | slxd { | |
175 | nvidia,pins = "slxd"; | |
176 | nvidia,function = "spdif"; | |
177 | }; | |
178 | spid { | |
179 | nvidia,pins = "spid", "spie", "spif"; | |
180 | nvidia,function = "spi1"; | |
181 | }; | |
182 | spig { | |
183 | nvidia,pins = "spig", "spih"; | |
184 | nvidia,function = "spi2_alt"; | |
185 | }; | |
186 | uaa { | |
187 | nvidia,pins = "uaa", "uab", "uda"; | |
188 | nvidia,function = "ulpi"; | |
189 | }; | |
190 | uad { | |
191 | nvidia,pins = "uad"; | |
192 | nvidia,function = "irda"; | |
193 | }; | |
194 | uca { | |
195 | nvidia,pins = "uca", "ucb"; | |
196 | nvidia,function = "uartc"; | |
197 | }; | |
198 | conf_ata { | |
199 | nvidia,pins = "ata", "atb", "atc", "atd", | |
200 | "cdev1", "cdev2", "dap1", "dap2", | |
201 | "dap4", "ddc", "dtf", "gma", "gmc", | |
202 | "gme", "gpu", "gpu7", "i2cp", "irrx", | |
203 | "irtx", "pta", "rm", "sdc", "sdd", | |
204 | "slxc", "slxd", "slxk", "spdi", "spdo", | |
205 | "uac", "uad", "uca", "ucb", "uda"; | |
ba4104e7 LD |
206 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
207 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
ecc295bb SW |
208 | }; |
209 | conf_ate { | |
210 | nvidia,pins = "ate", "csus", "dap3", "gmd", | |
211 | "gpv", "owc", "spia", "spib", "spic", | |
212 | "spid", "spie", "spig"; | |
ba4104e7 LD |
213 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
214 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
ecc295bb SW |
215 | }; |
216 | conf_ck32 { | |
217 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", | |
218 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; | |
ba4104e7 | 219 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
ecc295bb SW |
220 | }; |
221 | conf_crtp { | |
222 | nvidia,pins = "crtp", "gmb", "slxa", "spih"; | |
ba4104e7 LD |
223 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
224 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
ecc295bb SW |
225 | }; |
226 | conf_dta { | |
227 | nvidia,pins = "dta", "dtb", "dtc", "dtd"; | |
ba4104e7 LD |
228 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
229 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
ecc295bb SW |
230 | }; |
231 | conf_dte { | |
232 | nvidia,pins = "dte", "spif"; | |
ba4104e7 LD |
233 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
234 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
ecc295bb SW |
235 | }; |
236 | conf_hdint { | |
237 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", | |
238 | "lpw1", "lsck", "lsda", "lsdi", "lvp0"; | |
ba4104e7 | 239 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
ecc295bb SW |
240 | }; |
241 | conf_kbca { | |
242 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", | |
243 | "kbce", "kbcf", "sdio1", "uaa", "uab"; | |
ba4104e7 LD |
244 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
245 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
ecc295bb SW |
246 | }; |
247 | conf_lc { | |
248 | nvidia,pins = "lc", "ls"; | |
ba4104e7 | 249 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
ecc295bb SW |
250 | }; |
251 | conf_ld0 { | |
252 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | |
253 | "ld5", "ld6", "ld7", "ld8", "ld9", | |
254 | "ld10", "ld11", "ld12", "ld13", "ld14", | |
255 | "ld15", "ld16", "ld17", "ldi", "lhp0", | |
256 | "lhp1", "lhp2", "lhs", "lm0", "lpp", | |
257 | "lpw0", "lpw2", "lsc0", "lsc1", "lspi", | |
258 | "lvp1", "lvs", "pmc", "sdb"; | |
ba4104e7 | 259 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
ecc295bb SW |
260 | }; |
261 | conf_ld17_0 { | |
262 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | |
263 | "ld23_22"; | |
ba4104e7 | 264 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
ecc295bb | 265 | }; |
c729429e WN |
266 | drive_sdio1 { |
267 | nvidia,pins = "drive_sdio1"; | |
ba4104e7 LD |
268 | nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; |
269 | nvidia,schmitt = <TEGRA_PIN_ENABLE>; | |
270 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; | |
c729429e WN |
271 | nvidia,pull-down-strength = <31>; |
272 | nvidia,pull-up-strength = <31>; | |
ba4104e7 LD |
273 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
274 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; | |
c729429e | 275 | }; |
ecc295bb | 276 | }; |
cf633464 MZ |
277 | |
278 | state_i2cmux_ddc: pinmux_i2cmux_ddc { | |
279 | ddc { | |
280 | nvidia,pins = "ddc"; | |
281 | nvidia,function = "i2c2"; | |
282 | }; | |
283 | pta { | |
284 | nvidia,pins = "pta"; | |
285 | nvidia,function = "rsvd4"; | |
286 | }; | |
287 | }; | |
288 | ||
289 | state_i2cmux_pta: pinmux_i2cmux_pta { | |
290 | ddc { | |
291 | nvidia,pins = "ddc"; | |
292 | nvidia,function = "rsvd4"; | |
293 | }; | |
294 | pta { | |
295 | nvidia,pins = "pta"; | |
296 | nvidia,function = "i2c2"; | |
297 | }; | |
298 | }; | |
299 | ||
300 | state_i2cmux_idle: pinmux_i2cmux_idle { | |
301 | ddc { | |
302 | nvidia,pins = "ddc"; | |
303 | nvidia,function = "rsvd4"; | |
304 | }; | |
305 | pta { | |
306 | nvidia,pins = "pta"; | |
307 | nvidia,function = "rsvd4"; | |
308 | }; | |
309 | }; | |
ecc295bb SW |
310 | }; |
311 | ||
2a5fdc9a SW |
312 | i2s@70002800 { |
313 | status = "okay"; | |
c04abb3a SW |
314 | }; |
315 | ||
316 | serial@70006300 { | |
2a5fdc9a | 317 | status = "okay"; |
c04abb3a SW |
318 | }; |
319 | ||
1771a254 SW |
320 | pwm: pwm@7000a000 { |
321 | status = "okay"; | |
322 | }; | |
323 | ||
88950f3b | 324 | i2c@7000c000 { |
2a5fdc9a | 325 | status = "okay"; |
88950f3b | 326 | clock-frequency = <400000>; |
797acf70 SW |
327 | |
328 | wm8903: wm8903@1a { | |
329 | compatible = "wlf,wm8903"; | |
330 | reg = <0x1a>; | |
331 | interrupt-parent = <&gpio>; | |
6cecf916 | 332 | interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; |
797acf70 SW |
333 | |
334 | gpio-controller; | |
335 | #gpio-cells = <2>; | |
336 | ||
337 | micdet-cfg = <0>; | |
338 | micdet-delay = <100>; | |
95decf84 | 339 | gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; |
797acf70 | 340 | }; |
b46b0b54 LD |
341 | |
342 | /* ALS and proximity sensor */ | |
343 | isl29018@44 { | |
344 | compatible = "isil,isl29018"; | |
345 | reg = <0x44>; | |
346 | interrupt-parent = <&gpio>; | |
6cecf916 | 347 | interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; |
b46b0b54 | 348 | }; |
88950f3b SW |
349 | }; |
350 | ||
351 | i2c@7000c400 { | |
2a5fdc9a | 352 | status = "okay"; |
97d5520f | 353 | clock-frequency = <100000>; |
88950f3b SW |
354 | }; |
355 | ||
cf633464 MZ |
356 | i2cmux { |
357 | compatible = "i2c-mux-pinctrl"; | |
358 | #address-cells = <1>; | |
359 | #size-cells = <0>; | |
360 | ||
361 | i2c-parent = <&{/i2c@7000c400}>; | |
362 | ||
363 | pinctrl-names = "ddc", "pta", "idle"; | |
364 | pinctrl-0 = <&state_i2cmux_ddc>; | |
365 | pinctrl-1 = <&state_i2cmux_pta>; | |
366 | pinctrl-2 = <&state_i2cmux_idle>; | |
367 | ||
97d5520f | 368 | hdmi_ddc: i2c@0 { |
cf633464 MZ |
369 | reg = <0>; |
370 | #address-cells = <1>; | |
371 | #size-cells = <0>; | |
372 | }; | |
373 | ||
1771a254 | 374 | lvds_ddc: i2c@1 { |
cf633464 MZ |
375 | reg = <1>; |
376 | #address-cells = <1>; | |
377 | #size-cells = <0>; | |
378 | }; | |
379 | }; | |
380 | ||
88950f3b | 381 | i2c@7000c500 { |
2a5fdc9a | 382 | status = "okay"; |
88950f3b SW |
383 | clock-frequency = <400000>; |
384 | }; | |
385 | ||
386 | i2c@7000d000 { | |
2a5fdc9a | 387 | status = "okay"; |
88950f3b | 388 | clock-frequency = <400000>; |
017a0104 SW |
389 | |
390 | pmic: tps6586x@34 { | |
391 | compatible = "ti,tps6586x"; | |
392 | reg = <0x34>; | |
6cecf916 | 393 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
017a0104 | 394 | |
44b12ef7 SW |
395 | ti,system-power-controller; |
396 | ||
017a0104 SW |
397 | #gpio-cells = <2>; |
398 | gpio-controller; | |
399 | ||
400 | sys-supply = <&vdd_5v0_reg>; | |
401 | vin-sm0-supply = <&sys_reg>; | |
402 | vin-sm1-supply = <&sys_reg>; | |
403 | vin-sm2-supply = <&sys_reg>; | |
404 | vinldo01-supply = <&sm2_reg>; | |
405 | vinldo23-supply = <&sm2_reg>; | |
406 | vinldo4-supply = <&sm2_reg>; | |
407 | vinldo678-supply = <&sm2_reg>; | |
408 | vinldo9-supply = <&sm2_reg>; | |
409 | ||
410 | regulators { | |
b9c665d7 | 411 | sys_reg: sys { |
017a0104 SW |
412 | regulator-name = "vdd_sys"; |
413 | regulator-always-on; | |
414 | }; | |
415 | ||
b9c665d7 | 416 | sm0 { |
017a0104 SW |
417 | regulator-name = "vdd_sm0,vdd_core"; |
418 | regulator-min-microvolt = <1200000>; | |
419 | regulator-max-microvolt = <1200000>; | |
420 | regulator-always-on; | |
421 | }; | |
422 | ||
b9c665d7 | 423 | sm1 { |
017a0104 SW |
424 | regulator-name = "vdd_sm1,vdd_cpu"; |
425 | regulator-min-microvolt = <1000000>; | |
426 | regulator-max-microvolt = <1000000>; | |
427 | regulator-always-on; | |
428 | }; | |
429 | ||
b9c665d7 | 430 | sm2_reg: sm2 { |
017a0104 SW |
431 | regulator-name = "vdd_sm2,vin_ldo*"; |
432 | regulator-min-microvolt = <3700000>; | |
433 | regulator-max-microvolt = <3700000>; | |
434 | regulator-always-on; | |
435 | }; | |
436 | ||
437 | /* LDO0 is not connected to anything */ | |
438 | ||
b9c665d7 | 439 | ldo1 { |
017a0104 SW |
440 | regulator-name = "vdd_ldo1,avdd_pll*"; |
441 | regulator-min-microvolt = <1100000>; | |
442 | regulator-max-microvolt = <1100000>; | |
443 | regulator-always-on; | |
444 | }; | |
445 | ||
b9c665d7 | 446 | ldo2 { |
017a0104 SW |
447 | regulator-name = "vdd_ldo2,vdd_rtc"; |
448 | regulator-min-microvolt = <1200000>; | |
449 | regulator-max-microvolt = <1200000>; | |
450 | }; | |
451 | ||
b9c665d7 | 452 | ldo3 { |
017a0104 SW |
453 | regulator-name = "vdd_ldo3,avdd_usb*"; |
454 | regulator-min-microvolt = <3300000>; | |
455 | regulator-max-microvolt = <3300000>; | |
456 | regulator-always-on; | |
457 | }; | |
458 | ||
b9c665d7 | 459 | ldo4 { |
017a0104 SW |
460 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; |
461 | regulator-min-microvolt = <1800000>; | |
462 | regulator-max-microvolt = <1800000>; | |
463 | regulator-always-on; | |
464 | }; | |
465 | ||
b9c665d7 | 466 | ldo5 { |
017a0104 SW |
467 | regulator-name = "vdd_ldo5,vcore_mmc"; |
468 | regulator-min-microvolt = <2850000>; | |
469 | regulator-max-microvolt = <2850000>; | |
470 | regulator-always-on; | |
471 | }; | |
472 | ||
b9c665d7 | 473 | ldo6 { |
017a0104 SW |
474 | regulator-name = "vdd_ldo6,avdd_vdac"; |
475 | regulator-min-microvolt = <1800000>; | |
476 | regulator-max-microvolt = <1800000>; | |
477 | }; | |
478 | ||
97d5520f | 479 | hdmi_vdd_reg: ldo7 { |
017a0104 SW |
480 | regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; |
481 | regulator-min-microvolt = <3300000>; | |
482 | regulator-max-microvolt = <3300000>; | |
483 | }; | |
484 | ||
97d5520f | 485 | hdmi_pll_reg: ldo8 { |
017a0104 SW |
486 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; |
487 | regulator-min-microvolt = <1800000>; | |
488 | regulator-max-microvolt = <1800000>; | |
489 | }; | |
490 | ||
b9c665d7 | 491 | ldo9 { |
017a0104 SW |
492 | regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; |
493 | regulator-min-microvolt = <2850000>; | |
494 | regulator-max-microvolt = <2850000>; | |
495 | regulator-always-on; | |
496 | }; | |
497 | ||
b9c665d7 | 498 | ldo_rtc { |
017a0104 SW |
499 | regulator-name = "vdd_rtc_out,vdd_cell"; |
500 | regulator-min-microvolt = <3300000>; | |
501 | regulator-max-microvolt = <3300000>; | |
502 | regulator-always-on; | |
503 | }; | |
504 | }; | |
505 | }; | |
ee9f7260 TR |
506 | |
507 | temperature-sensor@4c { | |
508 | compatible = "onnn,nct1008"; | |
509 | reg = <0x4c>; | |
510 | }; | |
017a0104 SW |
511 | }; |
512 | ||
58ecb23f | 513 | pmc@7000e400 { |
017a0104 | 514 | nvidia,invert-interrupt; |
47d2d63b | 515 | nvidia,suspend-mode = <1>; |
a44a019d JL |
516 | nvidia,cpu-pwr-good-time = <2000>; |
517 | nvidia,cpu-pwr-off-time = <100>; | |
518 | nvidia,core-pwr-good-time = <3845 3845>; | |
519 | nvidia,core-pwr-off-time = <458>; | |
520 | nvidia,sys-clock-req-active-high; | |
88950f3b SW |
521 | }; |
522 | ||
2a5fdc9a SW |
523 | usb@c5000000 { |
524 | status = "okay"; | |
c04abb3a SW |
525 | }; |
526 | ||
4c94c8b5 VB |
527 | usb-phy@c5000000 { |
528 | status = "okay"; | |
529 | }; | |
530 | ||
2a5fdc9a SW |
531 | usb@c5004000 { |
532 | status = "okay"; | |
3325f1bc SW |
533 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
534 | GPIO_ACTIVE_LOW>; | |
797acf70 SW |
535 | }; |
536 | ||
9dffe3be | 537 | usb-phy@c5004000 { |
4c94c8b5 | 538 | status = "okay"; |
3325f1bc SW |
539 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
540 | GPIO_ACTIVE_LOW>; | |
c04abb3a SW |
541 | }; |
542 | ||
9dffe3be VB |
543 | usb@c5008000 { |
544 | status = "okay"; | |
40e8b3a6 VB |
545 | }; |
546 | ||
4c94c8b5 VB |
547 | usb-phy@c5008000 { |
548 | status = "okay"; | |
549 | }; | |
550 | ||
c729429e WN |
551 | sdhci@c8000000 { |
552 | status = "okay"; | |
3325f1bc | 553 | power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; |
c729429e | 554 | bus-width = <4>; |
7a2617a6 | 555 | keep-power-in-suspend; |
c729429e WN |
556 | }; |
557 | ||
c04abb3a | 558 | sdhci@c8000400 { |
2a5fdc9a | 559 | status = "okay"; |
3325f1bc SW |
560 | cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; |
561 | wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; | |
562 | power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; | |
deb88cc3 | 563 | bus-width = <4>; |
c04abb3a SW |
564 | }; |
565 | ||
566 | sdhci@c8000600 { | |
2a5fdc9a | 567 | status = "okay"; |
deb88cc3 | 568 | bus-width = <8>; |
7a2617a6 | 569 | non-removable; |
c04abb3a SW |
570 | }; |
571 | ||
1771a254 SW |
572 | backlight: backlight { |
573 | compatible = "pwm-backlight"; | |
574 | ||
575 | enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; | |
576 | power-supply = <&vdd_bl_reg>; | |
577 | pwms = <&pwm 2 5000000>; | |
578 | ||
579 | brightness-levels = <0 4 8 16 32 64 128 255>; | |
580 | default-brightness-level = <6>; | |
581 | }; | |
582 | ||
7021d122 JL |
583 | clocks { |
584 | compatible = "simple-bus"; | |
585 | #address-cells = <1>; | |
586 | #size-cells = <0>; | |
587 | ||
58ecb23f | 588 | clk32k_in: clock@0 { |
7021d122 JL |
589 | compatible = "fixed-clock"; |
590 | reg=<0>; | |
591 | #clock-cells = <0>; | |
592 | clock-frequency = <32768>; | |
593 | }; | |
594 | }; | |
595 | ||
5741a256 JL |
596 | gpio-keys { |
597 | compatible = "gpio-keys"; | |
598 | ||
599 | power { | |
600 | label = "Power"; | |
3325f1bc | 601 | gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
6bccbd5e | 602 | linux,code = <KEY_POWER>; |
5741a256 JL |
603 | gpio-key,wakeup; |
604 | }; | |
605 | }; | |
606 | ||
1771a254 SW |
607 | panel: panel { |
608 | compatible = "chunghwa,claa101wa01a", "simple-panel"; | |
609 | ||
610 | power-supply = <&vdd_pnl_reg>; | |
611 | enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; | |
612 | ||
613 | backlight = <&backlight>; | |
614 | ddc-i2c-bus = <&lvds_ddc>; | |
615 | }; | |
616 | ||
017a0104 SW |
617 | regulators { |
618 | compatible = "simple-bus"; | |
619 | #address-cells = <1>; | |
620 | #size-cells = <0>; | |
621 | ||
622 | vdd_5v0_reg: regulator@0 { | |
623 | compatible = "regulator-fixed"; | |
624 | reg = <0>; | |
625 | regulator-name = "vdd_5v0"; | |
626 | regulator-min-microvolt = <5000000>; | |
627 | regulator-max-microvolt = <5000000>; | |
628 | regulator-always-on; | |
629 | }; | |
630 | ||
631 | regulator@1 { | |
632 | compatible = "regulator-fixed"; | |
633 | reg = <1>; | |
634 | regulator-name = "vdd_1v5"; | |
635 | regulator-min-microvolt = <1500000>; | |
636 | regulator-max-microvolt = <1500000>; | |
3325f1bc | 637 | gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; |
017a0104 SW |
638 | }; |
639 | ||
640 | regulator@2 { | |
641 | compatible = "regulator-fixed"; | |
642 | reg = <2>; | |
643 | regulator-name = "vdd_1v2"; | |
644 | regulator-min-microvolt = <1200000>; | |
645 | regulator-max-microvolt = <1200000>; | |
3325f1bc | 646 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; |
017a0104 SW |
647 | enable-active-high; |
648 | }; | |
649 | ||
1771a254 | 650 | vdd_pnl_reg: regulator@3 { |
017a0104 SW |
651 | compatible = "regulator-fixed"; |
652 | reg = <3>; | |
653 | regulator-name = "vdd_pnl"; | |
654 | regulator-min-microvolt = <2800000>; | |
655 | regulator-max-microvolt = <2800000>; | |
3325f1bc | 656 | gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; |
017a0104 SW |
657 | enable-active-high; |
658 | }; | |
659 | ||
1771a254 | 660 | vdd_bl_reg: regulator@4 { |
017a0104 SW |
661 | compatible = "regulator-fixed"; |
662 | reg = <4>; | |
663 | regulator-name = "vdd_bl"; | |
664 | regulator-min-microvolt = <2800000>; | |
665 | regulator-max-microvolt = <2800000>; | |
3325f1bc | 666 | gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; |
017a0104 SW |
667 | enable-active-high; |
668 | }; | |
669 | }; | |
670 | ||
797acf70 SW |
671 | sound { |
672 | compatible = "nvidia,tegra-audio-wm8903-ventana", | |
673 | "nvidia,tegra-audio-wm8903"; | |
674 | nvidia,model = "NVIDIA Tegra Ventana"; | |
675 | ||
676 | nvidia,audio-routing = | |
677 | "Headphone Jack", "HPOUTR", | |
678 | "Headphone Jack", "HPOUTL", | |
679 | "Int Spk", "ROP", | |
680 | "Int Spk", "RON", | |
681 | "Int Spk", "LOP", | |
682 | "Int Spk", "LON", | |
683 | "Mic Jack", "MICBIAS", | |
684 | "IN1L", "Mic Jack"; | |
685 | ||
686 | nvidia,i2s-controller = <&tegra_i2s1>; | |
687 | nvidia,audio-codec = <&wm8903>; | |
688 | ||
3325f1bc SW |
689 | nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
690 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; | |
691 | nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) | |
692 | GPIO_ACTIVE_HIGH>; | |
693 | nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) | |
694 | GPIO_ACTIVE_HIGH>; | |
f9cd2b3b | 695 | |
885a8cfa HD |
696 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
697 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | |
698 | <&tegra_car TEGRA20_CLK_CDEV1>; | |
f9cd2b3b | 699 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
797acf70 | 700 | }; |
add29e61 | 701 | }; |