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ARM: tegra: Add SPI controller nodes for Tegra124
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / tegra20-whistler.dts
CommitLineData
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1/dts-v1/;
2
6bccbd5e 3#include <dt-bindings/input/input.h>
1bd0bd49 4#include "tegra20.dtsi"
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5
6/ {
8fef5dff 7 model = "NVIDIA Tegra20 Whistler evaluation board";
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8 compatible = "nvidia,whistler", "nvidia,tegra20";
9
10 memory {
11 reg = <0x00000000 0x20000000>;
12 };
13
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14 host1x@50000000 {
15 hdmi@54280000 {
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16 status = "okay";
17
18 vdd-supply = <&hdmi_vdd_reg>;
19 pll-supply = <&hdmi_pll_reg>;
20
21 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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22 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
23 GPIO_ACTIVE_HIGH>;
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24 };
25 };
26
58ecb23f 27 pinmux@70000014 {
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28 pinctrl-names = "default";
29 pinctrl-0 = <&state_default>;
30
31 state_default: pinmux {
32 ata {
33 nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
34 "gmc", "gmd", "gpu";
35 nvidia,function = "gmi";
36 };
37 atc {
38 nvidia,pins = "atc", "atd";
39 nvidia,function = "sdio4";
40 };
41 cdev1 {
42 nvidia,pins = "cdev1";
43 nvidia,function = "plla_out";
44 };
45 cdev2 {
46 nvidia,pins = "cdev2";
47 nvidia,function = "osc";
48 };
49 crtp {
50 nvidia,pins = "crtp";
51 nvidia,function = "crt";
52 };
53 csus {
54 nvidia,pins = "csus";
55 nvidia,function = "vi_sensor_clk";
56 };
57 dap1 {
58 nvidia,pins = "dap1";
59 nvidia,function = "dap1";
60 };
61 dap2 {
62 nvidia,pins = "dap2";
63 nvidia,function = "dap2";
64 };
65 dap3 {
66 nvidia,pins = "dap3";
67 nvidia,function = "dap3";
68 };
69 dap4 {
70 nvidia,pins = "dap4";
71 nvidia,function = "dap4";
72 };
73 ddc {
74 nvidia,pins = "ddc";
75 nvidia,function = "i2c2";
76 };
77 dta {
78 nvidia,pins = "dta", "dtb", "dtc", "dtd";
79 nvidia,function = "vi";
80 };
81 dte {
82 nvidia,pins = "dte";
83 nvidia,function = "rsvd1";
84 };
85 dtf {
86 nvidia,pins = "dtf";
87 nvidia,function = "i2c3";
88 };
89 gme {
90 nvidia,pins = "gme";
91 nvidia,function = "dap5";
92 };
93 gpu7 {
94 nvidia,pins = "gpu7";
95 nvidia,function = "rtck";
96 };
97 gpv {
98 nvidia,pins = "gpv";
99 nvidia,function = "pcie";
100 };
101 hdint {
102 nvidia,pins = "hdint", "pta";
103 nvidia,function = "hdmi";
104 };
105 i2cp {
106 nvidia,pins = "i2cp";
107 nvidia,function = "i2cp";
108 };
109 irrx {
110 nvidia,pins = "irrx", "irtx";
111 nvidia,function = "uartb";
112 };
113 kbca {
114 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
115 nvidia,function = "kbc";
116 };
117 kbcb {
118 nvidia,pins = "kbcb", "kbcd";
119 nvidia,function = "sdio2";
120 };
121 lcsn {
122 nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
123 "spia", "spib", "spic";
124 nvidia,function = "spi3";
125 };
126 ld0 {
127 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
128 "ld5", "ld6", "ld7", "ld8", "ld9",
129 "ld10", "ld11", "ld12", "ld13", "ld14",
130 "ld15", "ld16", "ld17", "ldc", "ldi",
131 "lhp0", "lhp1", "lhp2", "lhs", "lm0",
132 "lm1", "lpp", "lpw0", "lpw1", "lpw2",
133 "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
134 "lvs";
135 nvidia,function = "displaya";
136 };
137 owc {
138 nvidia,pins = "owc", "uac";
139 nvidia,function = "owr";
140 };
141 pmc {
142 nvidia,pins = "pmc";
143 nvidia,function = "pwr_on";
144 };
145 rm {
146 nvidia,pins = "rm";
147 nvidia,function = "i2c1";
148 };
149 sdb {
150 nvidia,pins = "sdb", "sdc", "sdd", "slxa",
151 "slxc", "slxd", "slxk";
152 nvidia,function = "sdio3";
153 };
154 sdio1 {
155 nvidia,pins = "sdio1";
156 nvidia,function = "sdio1";
157 };
158 spdi {
159 nvidia,pins = "spdi", "spdo";
160 nvidia,function = "rsvd2";
161 };
162 spid {
163 nvidia,pins = "spid", "spie", "spig", "spih";
164 nvidia,function = "spi2_alt";
165 };
166 spif {
167 nvidia,pins = "spif";
168 nvidia,function = "spi2";
169 };
170 uaa {
171 nvidia,pins = "uaa", "uab";
172 nvidia,function = "uarta";
173 };
174 uad {
175 nvidia,pins = "uad";
176 nvidia,function = "irda";
177 };
178 uca {
179 nvidia,pins = "uca", "ucb";
180 nvidia,function = "uartc";
181 };
182 uda {
183 nvidia,pins = "uda";
184 nvidia,function = "spi1";
185 };
186 conf_ata {
187 nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
188 "gmb", "gmc", "gmd", "irrx", "irtx",
189 "kbca", "kbcb", "kbcc", "kbcd", "kbce",
190 "kbcf", "sdc", "sdd", "spie", "spig",
191 "spih", "uaa", "uab", "uad", "uca",
192 "ucb";
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193 nvidia,pull = <TEGRA_PIN_PULL_UP>;
194 nvidia,tristate = <TEGRA_PIN_DISABLE>;
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195 };
196 conf_atd {
197 nvidia,pins = "atd", "ate", "cdev1", "csus",
198 "dap1", "dap2", "dap3", "dap4", "dte",
199 "dtf", "gpu", "gpu7", "gpv", "i2cp",
200 "rm", "sdio1", "slxa", "slxc", "slxd",
201 "slxk", "spdi", "spdo", "uac", "uda";
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202 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
203 nvidia,tristate = <TEGRA_PIN_DISABLE>;
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204 };
205 conf_cdev2 {
206 nvidia,pins = "cdev2", "spia", "spib";
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207 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
208 nvidia,tristate = <TEGRA_PIN_ENABLE>;
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209 };
210 conf_ck32 {
211 nvidia,pins = "ck32", "ddrc", "lc", "pmca",
212 "pmcb", "pmcc", "pmcd", "xm2c",
213 "xm2d";
ba4104e7 214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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215 };
216 conf_crtp {
217 nvidia,pins = "crtp";
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218 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
219 nvidia,tristate = <TEGRA_PIN_ENABLE>;
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220 };
221 conf_dta {
222 nvidia,pins = "dta", "dtb", "dtc", "dtd",
223 "spid", "spif";
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224 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
225 nvidia,tristate = <TEGRA_PIN_DISABLE>;
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226 };
227 conf_gme {
228 nvidia,pins = "gme", "owc", "pta", "spic";
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229 nvidia,pull = <TEGRA_PIN_PULL_UP>;
230 nvidia,tristate = <TEGRA_PIN_ENABLE>;
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231 };
232 conf_ld17_0 {
233 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
234 "ld23_22";
ba4104e7 235 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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236 };
237 conf_ls {
238 nvidia,pins = "ls", "pmce";
ba4104e7 239 nvidia,pull = <TEGRA_PIN_PULL_UP>;
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240 };
241 drive_dap1 {
242 nvidia,pins = "drive_dap1";
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243 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
244 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
245 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_8>;
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246 nvidia,pull-down-strength = <0>;
247 nvidia,pull-up-strength = <0>;
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248 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
249 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
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250 };
251 };
252 };
253
254 i2s@70002800 {
255 status = "okay";
256 };
257
258 serial@70006000 {
259 status = "okay";
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260 };
261
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262 hdmi_ddc: i2c@7000c400 {
263 status = "okay";
264 clock-frequency = <100000>;
265 };
266
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267 i2c@7000d000 {
268 status = "okay";
269 clock-frequency = <100000>;
270
271 codec: codec@1a {
272 compatible = "wlf,wm8753";
273 reg = <0x1a>;
274 };
275
276 tca6416: gpio@20 {
277 compatible = "ti,tca6416";
278 reg = <0x20>;
279 gpio-controller;
280 #gpio-cells = <2>;
281 };
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282
283 max8907@3c {
284 compatible = "maxim,max8907";
285 reg = <0x3c>;
6cecf916 286 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
e7765b37 287
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288 maxim,system-power-controller;
289
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290 mbatt-supply = <&usb0_vbus_reg>;
291 in-v1-supply = <&mbatt_reg>;
292 in-v2-supply = <&mbatt_reg>;
293 in-v3-supply = <&mbatt_reg>;
294 in1-supply = <&mbatt_reg>;
295 in2-supply = <&nvvdd_sv3_reg>;
296 in3-supply = <&mbatt_reg>;
297 in4-supply = <&mbatt_reg>;
298 in5-supply = <&mbatt_reg>;
299 in6-supply = <&mbatt_reg>;
300 in7-supply = <&mbatt_reg>;
301 in8-supply = <&mbatt_reg>;
302 in9-supply = <&mbatt_reg>;
303 in10-supply = <&mbatt_reg>;
304 in11-supply = <&mbatt_reg>;
305 in12-supply = <&mbatt_reg>;
306 in13-supply = <&mbatt_reg>;
307 in14-supply = <&mbatt_reg>;
308 in15-supply = <&mbatt_reg>;
309 in16-supply = <&mbatt_reg>;
310 in17-supply = <&nvvdd_sv3_reg>;
311 in18-supply = <&nvvdd_sv3_reg>;
312 in19-supply = <&mbatt_reg>;
313 in20-supply = <&mbatt_reg>;
314
315 regulators {
b9c665d7 316 mbatt_reg: mbatt {
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317 regulator-name = "vbat_pmu";
318 regulator-always-on;
319 };
320
b9c665d7 321 sd1 {
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322 regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
323 regulator-min-microvolt = <1000000>;
324 regulator-max-microvolt = <1000000>;
325 regulator-always-on;
326 };
327
b9c665d7 328 sd2 {
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329 regulator-name = "nvvdd_sv2,vdd_core";
330 regulator-min-microvolt = <1200000>;
331 regulator-max-microvolt = <1200000>;
332 regulator-always-on;
333 };
334
b9c665d7 335 nvvdd_sv3_reg: sd3 {
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336 regulator-name = "nvvdd_sv3";
337 regulator-min-microvolt = <1800000>;
338 regulator-max-microvolt = <1800000>;
339 regulator-always-on;
340 };
341
b9c665d7 342 ldo1 {
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343 regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
344 regulator-min-microvolt = <3300000>;
345 regulator-max-microvolt = <3300000>;
346 regulator-always-on;
347 };
348
b9c665d7 349 ldo2 {
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350 regulator-name = "nvvdd_ldo2,avdd_pll*";
351 regulator-min-microvolt = <1100000>;
352 regulator-max-microvolt = <1100000>;
353 regulator-always-on;
354 };
355
b9c665d7 356 ldo3 {
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357 regulator-name = "nvvdd_ldo3,vcom_1v8b";
358 regulator-min-microvolt = <1800000>;
359 regulator-max-microvolt = <1800000>;
360 regulator-always-on;
361 };
362
b9c665d7 363 ldo4 {
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364 regulator-name = "nvvdd_ldo4,avdd_usb*";
365 regulator-min-microvolt = <3300000>;
366 regulator-max-microvolt = <3300000>;
367 regulator-always-on;
368 };
369
b9c665d7 370 ldo5 {
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371 regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
372 regulator-min-microvolt = <2800000>;
373 regulator-max-microvolt = <2800000>;
374 regulator-always-on;
375 };
376
2658ef15 377 hdmi_pll_reg: ldo6 {
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378 regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
379 regulator-min-microvolt = <1800000>;
380 regulator-max-microvolt = <1800000>;
381 };
382
b9c665d7 383 ldo7 {
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384 regulator-name = "nvvdd_ldo7,avddio_audio";
385 regulator-min-microvolt = <2800000>;
386 regulator-max-microvolt = <2800000>;
387 regulator-always-on;
388 };
389
b9c665d7 390 ldo8 {
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391 regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
392 regulator-min-microvolt = <3000000>;
393 regulator-max-microvolt = <3000000>;
394 };
395
b9c665d7 396 ldo9 {
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397 regulator-name = "nvvdd_ldo9,avdd_cam*";
398 regulator-min-microvolt = <2800000>;
399 regulator-max-microvolt = <2800000>;
400 };
401
b9c665d7 402 ldo10 {
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403 regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
404 regulator-min-microvolt = <3000000>;
405 regulator-max-microvolt = <3000000>;
406 regulator-always-on;
407 };
408
2658ef15 409 hdmi_vdd_reg: ldo11 {
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410 regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
411 regulator-min-microvolt = <3300000>;
412 regulator-max-microvolt = <3300000>;
413 };
414
b9c665d7 415 ldo12 {
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416 regulator-name = "nvvdd_ldo12,vddio_sdio";
417 regulator-min-microvolt = <2800000>;
418 regulator-max-microvolt = <2800000>;
419 regulator-always-on;
420 };
421
b9c665d7 422 ldo13 {
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423 regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
424 regulator-min-microvolt = <2800000>;
425 regulator-max-microvolt = <2800000>;
426 };
427
b9c665d7 428 ldo14 {
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429 regulator-name = "nvvdd_ldo14,avdd_vdac";
430 regulator-min-microvolt = <2800000>;
431 regulator-max-microvolt = <2800000>;
432 };
433
b9c665d7 434 ldo15 {
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435 regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
436 regulator-min-microvolt = <3300000>;
437 regulator-max-microvolt = <3300000>;
438 };
439
b9c665d7 440 ldo16 {
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441 regulator-name = "nvvdd_ldo16,vdd_dbrtr";
442 regulator-min-microvolt = <1300000>;
443 regulator-max-microvolt = <1300000>;
444 };
445
b9c665d7 446 ldo17 {
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447 regulator-name = "nvvdd_ldo17,vddio_mipi";
448 regulator-min-microvolt = <1200000>;
449 regulator-max-microvolt = <1200000>;
450 };
451
b9c665d7 452 ldo18 {
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453 regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
454 regulator-min-microvolt = <1800000>;
455 regulator-max-microvolt = <1800000>;
456 };
457
b9c665d7 458 ldo19 {
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459 regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
460 regulator-min-microvolt = <2800000>;
461 regulator-max-microvolt = <2800000>;
462 };
463
b9c665d7 464 ldo20 {
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465 regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
466 regulator-min-microvolt = <1200000>;
467 regulator-max-microvolt = <1200000>;
468 regulator-always-on;
469 };
470
b9c665d7 471 out5v {
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472 regulator-name = "usb0_vbus_reg";
473 };
474
b9c665d7 475 out33v {
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476 regulator-name = "pmu_out3v3";
477 };
478
b9c665d7 479 bbat {
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480 regulator-name = "pmu_bbat";
481 regulator-min-microvolt = <2400000>;
482 regulator-max-microvolt = <2400000>;
483 regulator-always-on;
484 };
485
b9c665d7 486 sdby {
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487 regulator-name = "vdd_aon";
488 regulator-always-on;
489 };
490
b9c665d7 491 vrtc {
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492 regulator-name = "vrtc,pmu_vccadc";
493 regulator-always-on;
494 };
495 };
496 };
497 };
498
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SW
499 kbc@7000e200 {
500 status = "okay";
501 nvidia,debounce-delay-ms = <20>;
502 nvidia,repeat-delay-ms = <160>;
503 nvidia,kbc-row-pins = <0 1 2>;
504 nvidia,kbc-col-pins = <16 17>;
505 nvidia,wakeup-source;
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LD
506 linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_POWER)
507 MATRIX_KEY(0x01, 0x00, KEY_HOME)
508 MATRIX_KEY(0x01, 0x01, KEY_BACK)
509 MATRIX_KEY(0x02, 0x01, KEY_MENU)>;
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SW
510 };
511
58ecb23f 512 pmc@7000e400 {
e7765b37 513 nvidia,invert-interrupt;
47d2d63b 514 nvidia,suspend-mode = <1>;
a44a019d
JL
515 nvidia,cpu-pwr-good-time = <2000>;
516 nvidia,cpu-pwr-off-time = <1000>;
517 nvidia,core-pwr-good-time = <0 3845>;
518 nvidia,core-pwr-off-time = <93727>;
519 nvidia,core-power-req-active-high;
520 nvidia,sys-clock-req-active-high;
521 nvidia,combined-power-req;
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SW
522 };
523
524 usb@c5000000 {
525 status = "okay";
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SW
526 };
527
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528 usb-phy@c5000000 {
529 status = "okay";
530 vbus-supply = <&vbus1_reg>;
531 };
532
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533 usb@c5008000 {
534 status = "okay";
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SW
535 };
536
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VB
537 usb-phy@c5008000 {
538 status = "okay";
539 vbus-supply = <&vbus3_reg>;
540 };
541
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542 sdhci@c8000400 {
543 status = "okay";
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544 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
545 wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
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546 bus-width = <8>;
547 };
548
549 sdhci@c8000600 {
550 status = "okay";
551 bus-width = <8>;
7a2617a6 552 non-removable;
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SW
553 };
554
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JL
555 clocks {
556 compatible = "simple-bus";
557 #address-cells = <1>;
558 #size-cells = <0>;
559
58ecb23f 560 clk32k_in: clock@0 {
7021d122
JL
561 compatible = "fixed-clock";
562 reg=<0>;
563 #clock-cells = <0>;
564 clock-frequency = <32768>;
565 };
566 };
567
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SW
568 regulators {
569 compatible = "simple-bus";
570 #address-cells = <1>;
571 #size-cells = <0>;
572
58ecb23f 573 usb0_vbus_reg: regulator@0 {
e7765b37
SW
574 compatible = "regulator-fixed";
575 reg = <0>;
576 regulator-name = "usb0_vbus";
577 regulator-min-microvolt = <5000000>;
578 regulator-max-microvolt = <5000000>;
579 regulator-always-on;
580 };
4c94c8b5
VB
581
582 vbus1_reg: regulator@2 {
583 compatible = "regulator-fixed";
584 reg = <2>;
585 regulator-name = "vbus1";
586 regulator-min-microvolt = <5000000>;
587 regulator-max-microvolt = <5000000>;
9f310ded 588 enable-active-high;
4c94c8b5 589 gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
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SW
590 regulator-always-on;
591 regulator-boot-on;
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VB
592 };
593
594 vbus3_reg: regulator@3 {
595 compatible = "regulator-fixed";
596 reg = <3>;
597 regulator-name = "vbus3";
598 regulator-min-microvolt = <5000000>;
599 regulator-max-microvolt = <5000000>;
9f310ded 600 enable-active-high;
4c94c8b5 601 gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
30ca2226
SW
602 regulator-always-on;
603 regulator-boot-on;
4c94c8b5 604 };
e7765b37
SW
605 };
606
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SW
607 sound {
608 compatible = "nvidia,tegra-audio-wm8753-whistler",
609 "nvidia,tegra-audio-wm8753";
610 nvidia,model = "NVIDIA Tegra Whistler";
611
612 nvidia,audio-routing =
613 "Headphone Jack", "LOUT1",
614 "Headphone Jack", "ROUT1",
615 "MIC2", "Mic Jack",
616 "MIC2N", "Mic Jack";
617
618 nvidia,i2s-controller = <&tegra_i2s1>;
619 nvidia,audio-codec = <&codec>;
f9cd2b3b 620
885a8cfa
HD
621 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
622 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
623 <&tegra_car TEGRA20_CLK_CDEV1>;
f9cd2b3b 624 clock-names = "pll_a", "pll_a_out0", "mclk";
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SW
625 };
626};