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Commit | Line | Data |
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885a8cfa | 1 | #include <dt-bindings/clock/tegra20-car.h> |
3325f1bc | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
ba4104e7 | 3 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
6cecf916 | 4 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
3325f1bc | 5 | |
1bd0bd49 | 6 | #include "skeleton.dtsi" |
8e267f3d GL |
7 | |
8 | / { | |
9 | compatible = "nvidia,tegra20"; | |
10 | interrupt-parent = <&intc>; | |
11 | ||
b6551bb9 LD |
12 | aliases { |
13 | serial0 = &uarta; | |
14 | serial1 = &uartb; | |
15 | serial2 = &uartc; | |
16 | serial3 = &uartd; | |
17 | serial4 = &uarte; | |
18 | }; | |
19 | ||
58ecb23f | 20 | host1x@50000000 { |
ed821f07 TR |
21 | compatible = "nvidia,tegra20-host1x", "simple-bus"; |
22 | reg = <0x50000000 0x00024000>; | |
6cecf916 SW |
23 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
24 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ | |
885a8cfa | 25 | clocks = <&tegra_car TEGRA20_CLK_HOST1X>; |
3393d422 SW |
26 | resets = <&tegra_car 28>; |
27 | reset-names = "host1x"; | |
ed821f07 TR |
28 | |
29 | #address-cells = <1>; | |
30 | #size-cells = <1>; | |
31 | ||
32 | ranges = <0x54000000 0x54000000 0x04000000>; | |
33 | ||
58ecb23f | 34 | mpe@54040000 { |
ed821f07 TR |
35 | compatible = "nvidia,tegra20-mpe"; |
36 | reg = <0x54040000 0x00040000>; | |
6cecf916 | 37 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 38 | clocks = <&tegra_car TEGRA20_CLK_MPE>; |
3393d422 SW |
39 | resets = <&tegra_car 60>; |
40 | reset-names = "mpe"; | |
ed821f07 TR |
41 | }; |
42 | ||
58ecb23f | 43 | vi@54080000 { |
ed821f07 TR |
44 | compatible = "nvidia,tegra20-vi"; |
45 | reg = <0x54080000 0x00040000>; | |
6cecf916 | 46 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 47 | clocks = <&tegra_car TEGRA20_CLK_VI>; |
3393d422 SW |
48 | resets = <&tegra_car 20>; |
49 | reset-names = "vi"; | |
ed821f07 TR |
50 | }; |
51 | ||
58ecb23f | 52 | epp@540c0000 { |
ed821f07 TR |
53 | compatible = "nvidia,tegra20-epp"; |
54 | reg = <0x540c0000 0x00040000>; | |
6cecf916 | 55 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 56 | clocks = <&tegra_car TEGRA20_CLK_EPP>; |
3393d422 SW |
57 | resets = <&tegra_car 19>; |
58 | reset-names = "epp"; | |
ed821f07 TR |
59 | }; |
60 | ||
58ecb23f | 61 | isp@54100000 { |
ed821f07 TR |
62 | compatible = "nvidia,tegra20-isp"; |
63 | reg = <0x54100000 0x00040000>; | |
6cecf916 | 64 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 65 | clocks = <&tegra_car TEGRA20_CLK_ISP>; |
3393d422 SW |
66 | resets = <&tegra_car 23>; |
67 | reset-names = "isp"; | |
ed821f07 TR |
68 | }; |
69 | ||
58ecb23f | 70 | gr2d@54140000 { |
ed821f07 TR |
71 | compatible = "nvidia,tegra20-gr2d"; |
72 | reg = <0x54140000 0x00040000>; | |
6cecf916 | 73 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 74 | clocks = <&tegra_car TEGRA20_CLK_GR2D>; |
3393d422 SW |
75 | resets = <&tegra_car 21>; |
76 | reset-names = "2d"; | |
ed821f07 TR |
77 | }; |
78 | ||
58ecb23f | 79 | gr3d@54140000 { |
ed821f07 | 80 | compatible = "nvidia,tegra20-gr3d"; |
58ecb23f | 81 | reg = <0x54140000 0x00040000>; |
885a8cfa | 82 | clocks = <&tegra_car TEGRA20_CLK_GR3D>; |
3393d422 SW |
83 | resets = <&tegra_car 24>; |
84 | reset-names = "3d"; | |
ed821f07 TR |
85 | }; |
86 | ||
87 | dc@54200000 { | |
88 | compatible = "nvidia,tegra20-dc"; | |
89 | reg = <0x54200000 0x00040000>; | |
6cecf916 | 90 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa HD |
91 | clocks = <&tegra_car TEGRA20_CLK_DISP1>, |
92 | <&tegra_car TEGRA20_CLK_PLL_P>; | |
d8f64797 | 93 | clock-names = "dc", "parent"; |
3393d422 SW |
94 | resets = <&tegra_car 27>; |
95 | reset-names = "dc"; | |
ed821f07 | 96 | |
688b56b4 TR |
97 | nvidia,head = <0>; |
98 | ||
ed821f07 TR |
99 | rgb { |
100 | status = "disabled"; | |
101 | }; | |
102 | }; | |
103 | ||
104 | dc@54240000 { | |
105 | compatible = "nvidia,tegra20-dc"; | |
106 | reg = <0x54240000 0x00040000>; | |
6cecf916 | 107 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa HD |
108 | clocks = <&tegra_car TEGRA20_CLK_DISP2>, |
109 | <&tegra_car TEGRA20_CLK_PLL_P>; | |
d8f64797 | 110 | clock-names = "dc", "parent"; |
3393d422 SW |
111 | resets = <&tegra_car 26>; |
112 | reset-names = "dc"; | |
ed821f07 | 113 | |
688b56b4 TR |
114 | nvidia,head = <1>; |
115 | ||
ed821f07 TR |
116 | rgb { |
117 | status = "disabled"; | |
118 | }; | |
119 | }; | |
120 | ||
58ecb23f | 121 | hdmi@54280000 { |
ed821f07 TR |
122 | compatible = "nvidia,tegra20-hdmi"; |
123 | reg = <0x54280000 0x00040000>; | |
6cecf916 | 124 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa HD |
125 | clocks = <&tegra_car TEGRA20_CLK_HDMI>, |
126 | <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; | |
8d8b43da | 127 | clock-names = "hdmi", "parent"; |
3393d422 SW |
128 | resets = <&tegra_car 51>; |
129 | reset-names = "hdmi"; | |
ed821f07 TR |
130 | status = "disabled"; |
131 | }; | |
132 | ||
58ecb23f | 133 | tvo@542c0000 { |
ed821f07 TR |
134 | compatible = "nvidia,tegra20-tvo"; |
135 | reg = <0x542c0000 0x00040000>; | |
6cecf916 | 136 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 137 | clocks = <&tegra_car TEGRA20_CLK_TVO>; |
ed821f07 TR |
138 | status = "disabled"; |
139 | }; | |
140 | ||
58ecb23f | 141 | dsi@542c0000 { |
ed821f07 | 142 | compatible = "nvidia,tegra20-dsi"; |
58ecb23f | 143 | reg = <0x542c0000 0x00040000>; |
885a8cfa | 144 | clocks = <&tegra_car TEGRA20_CLK_DSI>; |
3393d422 SW |
145 | resets = <&tegra_car 48>; |
146 | reset-names = "dsi"; | |
ed821f07 TR |
147 | status = "disabled"; |
148 | }; | |
149 | }; | |
150 | ||
73368ba0 SW |
151 | timer@50004600 { |
152 | compatible = "arm,cortex-a9-twd-timer"; | |
153 | reg = <0x50040600 0x20>; | |
6cecf916 SW |
154 | interrupts = <GIC_PPI 13 |
155 | (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; | |
885a8cfa | 156 | clocks = <&tegra_car TEGRA20_CLK_TWD>; |
73368ba0 SW |
157 | }; |
158 | ||
58ecb23f | 159 | intc: interrupt-controller@50041000 { |
0d4f7479 | 160 | compatible = "arm,cortex-a9-gic"; |
5ff48887 SW |
161 | reg = <0x50041000 0x1000 |
162 | 0x50040100 0x0100>; | |
2eaab06e SW |
163 | interrupt-controller; |
164 | #interrupt-cells = <3>; | |
8e267f3d GL |
165 | }; |
166 | ||
58ecb23f | 167 | cache-controller@50043000 { |
bb2c1de9 SW |
168 | compatible = "arm,pl310-cache"; |
169 | reg = <0x50043000 0x1000>; | |
170 | arm,data-latency = <5 5 2>; | |
171 | arm,tag-latency = <4 4 2>; | |
172 | cache-unified; | |
173 | cache-level = <2>; | |
174 | }; | |
175 | ||
2f2b7fb2 SW |
176 | timer@60005000 { |
177 | compatible = "nvidia,tegra20-timer"; | |
178 | reg = <0x60005000 0x60>; | |
6cecf916 SW |
179 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
180 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
181 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
182 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
885a8cfa | 183 | clocks = <&tegra_car TEGRA20_CLK_TIMER>; |
2f2b7fb2 SW |
184 | }; |
185 | ||
58ecb23f | 186 | tegra_car: clock@60006000 { |
270f8ce3 SW |
187 | compatible = "nvidia,tegra20-car"; |
188 | reg = <0x60006000 0x1000>; | |
189 | #clock-cells = <1>; | |
3393d422 | 190 | #reset-cells = <1>; |
270f8ce3 SW |
191 | }; |
192 | ||
58ecb23f | 193 | apbdma: dma@6000a000 { |
8051b75a SW |
194 | compatible = "nvidia,tegra20-apbdma"; |
195 | reg = <0x6000a000 0x1200>; | |
6cecf916 SW |
196 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
197 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
198 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
199 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
200 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
201 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
202 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
203 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
204 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
205 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
206 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
207 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
208 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
209 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
210 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
211 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; | |
885a8cfa | 212 | clocks = <&tegra_car TEGRA20_CLK_APBDMA>; |
3393d422 SW |
213 | resets = <&tegra_car 34>; |
214 | reset-names = "dma"; | |
034d023f | 215 | #dma-cells = <1>; |
8051b75a SW |
216 | }; |
217 | ||
58ecb23f | 218 | ahb@6000c004 { |
c04abb3a SW |
219 | compatible = "nvidia,tegra20-ahb"; |
220 | reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ | |
8e267f3d GL |
221 | }; |
222 | ||
58ecb23f | 223 | gpio: gpio@6000d000 { |
8e267f3d | 224 | compatible = "nvidia,tegra20-gpio"; |
95decf84 | 225 | reg = <0x6000d000 0x1000>; |
6cecf916 SW |
226 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
227 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
228 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, | |
229 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, | |
230 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
231 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
232 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
8e267f3d GL |
233 | #gpio-cells = <2>; |
234 | gpio-controller; | |
6f74dc9b SW |
235 | #interrupt-cells = <2>; |
236 | interrupt-controller; | |
8e267f3d GL |
237 | }; |
238 | ||
155dfc7b PDS |
239 | apbmisc@70000800 { |
240 | compatible = "nvidia,tegra20-apbmisc"; | |
241 | reg = <0x70000800 0x64 /* Chip revision */ | |
242 | 0x70000008 0x04>; /* Strapping options */ | |
243 | }; | |
244 | ||
58ecb23f | 245 | pinmux: pinmux@70000014 { |
f62f548c | 246 | compatible = "nvidia,tegra20-pinmux"; |
95decf84 SW |
247 | reg = <0x70000014 0x10 /* Tri-state registers */ |
248 | 0x70000080 0x20 /* Mux registers */ | |
249 | 0x700000a0 0x14 /* Pull-up/down registers */ | |
250 | 0x70000868 0xa8>; /* Pad control registers */ | |
f62f548c SW |
251 | }; |
252 | ||
58ecb23f | 253 | das@70000c00 { |
c04abb3a SW |
254 | compatible = "nvidia,tegra20-das"; |
255 | reg = <0x70000c00 0x80>; | |
256 | }; | |
fc5c306b | 257 | |
58ecb23f | 258 | tegra_ac97: ac97@70002000 { |
0698ed19 LS |
259 | compatible = "nvidia,tegra20-ac97"; |
260 | reg = <0x70002000 0x200>; | |
6cecf916 | 261 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 262 | clocks = <&tegra_car TEGRA20_CLK_AC97>; |
3393d422 SW |
263 | resets = <&tegra_car 3>; |
264 | reset-names = "ac97"; | |
034d023f SW |
265 | dmas = <&apbdma 12>, <&apbdma 12>; |
266 | dma-names = "rx", "tx"; | |
0698ed19 LS |
267 | status = "disabled"; |
268 | }; | |
c04abb3a SW |
269 | |
270 | tegra_i2s1: i2s@70002800 { | |
271 | compatible = "nvidia,tegra20-i2s"; | |
272 | reg = <0x70002800 0x200>; | |
6cecf916 | 273 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 274 | clocks = <&tegra_car TEGRA20_CLK_I2S1>; |
3393d422 SW |
275 | resets = <&tegra_car 11>; |
276 | reset-names = "i2s"; | |
034d023f SW |
277 | dmas = <&apbdma 2>, <&apbdma 2>; |
278 | dma-names = "rx", "tx"; | |
223ef78d | 279 | status = "disabled"; |
c04abb3a SW |
280 | }; |
281 | ||
282 | tegra_i2s2: i2s@70002a00 { | |
283 | compatible = "nvidia,tegra20-i2s"; | |
284 | reg = <0x70002a00 0x200>; | |
6cecf916 | 285 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 286 | clocks = <&tegra_car TEGRA20_CLK_I2S2>; |
3393d422 SW |
287 | resets = <&tegra_car 18>; |
288 | reset-names = "i2s"; | |
034d023f SW |
289 | dmas = <&apbdma 1>, <&apbdma 1>; |
290 | dma-names = "rx", "tx"; | |
223ef78d | 291 | status = "disabled"; |
c04abb3a SW |
292 | }; |
293 | ||
b6551bb9 LD |
294 | /* |
295 | * There are two serial driver i.e. 8250 based simple serial | |
296 | * driver and APB DMA based serial driver for higher baudrate | |
297 | * and performace. To enable the 8250 based driver, the compatible | |
298 | * is "nvidia,tegra20-uart" and to enable the APB DMA based serial | |
299 | * driver, the comptible is "nvidia,tegra20-hsuart". | |
300 | */ | |
301 | uarta: serial@70006000 { | |
8e267f3d GL |
302 | compatible = "nvidia,tegra20-uart"; |
303 | reg = <0x70006000 0x40>; | |
304 | reg-shift = <2>; | |
6cecf916 | 305 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 306 | clocks = <&tegra_car TEGRA20_CLK_UARTA>; |
3393d422 SW |
307 | resets = <&tegra_car 6>; |
308 | reset-names = "serial"; | |
034d023f SW |
309 | dmas = <&apbdma 8>, <&apbdma 8>; |
310 | dma-names = "rx", "tx"; | |
223ef78d | 311 | status = "disabled"; |
8e267f3d GL |
312 | }; |
313 | ||
b6551bb9 | 314 | uartb: serial@70006040 { |
8e267f3d GL |
315 | compatible = "nvidia,tegra20-uart"; |
316 | reg = <0x70006040 0x40>; | |
317 | reg-shift = <2>; | |
6cecf916 | 318 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 319 | clocks = <&tegra_car TEGRA20_CLK_UARTB>; |
3393d422 SW |
320 | resets = <&tegra_car 7>; |
321 | reset-names = "serial"; | |
034d023f SW |
322 | dmas = <&apbdma 9>, <&apbdma 9>; |
323 | dma-names = "rx", "tx"; | |
223ef78d | 324 | status = "disabled"; |
8e267f3d GL |
325 | }; |
326 | ||
b6551bb9 | 327 | uartc: serial@70006200 { |
8e267f3d GL |
328 | compatible = "nvidia,tegra20-uart"; |
329 | reg = <0x70006200 0x100>; | |
330 | reg-shift = <2>; | |
6cecf916 | 331 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 332 | clocks = <&tegra_car TEGRA20_CLK_UARTC>; |
3393d422 SW |
333 | resets = <&tegra_car 55>; |
334 | reset-names = "serial"; | |
034d023f SW |
335 | dmas = <&apbdma 10>, <&apbdma 10>; |
336 | dma-names = "rx", "tx"; | |
223ef78d | 337 | status = "disabled"; |
8e267f3d GL |
338 | }; |
339 | ||
b6551bb9 | 340 | uartd: serial@70006300 { |
8e267f3d GL |
341 | compatible = "nvidia,tegra20-uart"; |
342 | reg = <0x70006300 0x100>; | |
343 | reg-shift = <2>; | |
6cecf916 | 344 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 345 | clocks = <&tegra_car TEGRA20_CLK_UARTD>; |
3393d422 SW |
346 | resets = <&tegra_car 65>; |
347 | reset-names = "serial"; | |
034d023f SW |
348 | dmas = <&apbdma 19>, <&apbdma 19>; |
349 | dma-names = "rx", "tx"; | |
223ef78d | 350 | status = "disabled"; |
8e267f3d GL |
351 | }; |
352 | ||
b6551bb9 | 353 | uarte: serial@70006400 { |
8e267f3d GL |
354 | compatible = "nvidia,tegra20-uart"; |
355 | reg = <0x70006400 0x100>; | |
356 | reg-shift = <2>; | |
6cecf916 | 357 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 358 | clocks = <&tegra_car TEGRA20_CLK_UARTE>; |
3393d422 SW |
359 | resets = <&tegra_car 66>; |
360 | reset-names = "serial"; | |
034d023f SW |
361 | dmas = <&apbdma 20>, <&apbdma 20>; |
362 | dma-names = "rx", "tx"; | |
223ef78d | 363 | status = "disabled"; |
8e267f3d GL |
364 | }; |
365 | ||
58ecb23f | 366 | pwm: pwm@7000a000 { |
140fd977 TR |
367 | compatible = "nvidia,tegra20-pwm"; |
368 | reg = <0x7000a000 0x100>; | |
369 | #pwm-cells = <2>; | |
885a8cfa | 370 | clocks = <&tegra_car TEGRA20_CLK_PWM>; |
3393d422 SW |
371 | resets = <&tegra_car 17>; |
372 | reset-names = "pwm"; | |
b69cd984 | 373 | status = "disabled"; |
140fd977 TR |
374 | }; |
375 | ||
58ecb23f | 376 | rtc@7000e000 { |
380e04ac SW |
377 | compatible = "nvidia,tegra20-rtc"; |
378 | reg = <0x7000e000 0x100>; | |
6cecf916 | 379 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 380 | clocks = <&tegra_car TEGRA20_CLK_RTC>; |
380e04ac SW |
381 | }; |
382 | ||
c04abb3a | 383 | i2c@7000c000 { |
c04abb3a SW |
384 | compatible = "nvidia,tegra20-i2c"; |
385 | reg = <0x7000c000 0x100>; | |
6cecf916 | 386 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
387 | #address-cells = <1>; |
388 | #size-cells = <0>; | |
885a8cfa HD |
389 | clocks = <&tegra_car TEGRA20_CLK_I2C1>, |
390 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
8d8b43da | 391 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
392 | resets = <&tegra_car 12>; |
393 | reset-names = "i2c"; | |
034d023f SW |
394 | dmas = <&apbdma 21>, <&apbdma 21>; |
395 | dma-names = "rx", "tx"; | |
223ef78d | 396 | status = "disabled"; |
0c6700ab OJ |
397 | }; |
398 | ||
fa98a114 LD |
399 | spi@7000c380 { |
400 | compatible = "nvidia,tegra20-sflash"; | |
401 | reg = <0x7000c380 0x80>; | |
6cecf916 | 402 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
fa98a114 LD |
403 | #address-cells = <1>; |
404 | #size-cells = <0>; | |
885a8cfa | 405 | clocks = <&tegra_car TEGRA20_CLK_SPI>; |
3393d422 SW |
406 | resets = <&tegra_car 43>; |
407 | reset-names = "spi"; | |
034d023f SW |
408 | dmas = <&apbdma 11>, <&apbdma 11>; |
409 | dma-names = "rx", "tx"; | |
fa98a114 LD |
410 | status = "disabled"; |
411 | }; | |
412 | ||
c04abb3a | 413 | i2c@7000c400 { |
c04abb3a SW |
414 | compatible = "nvidia,tegra20-i2c"; |
415 | reg = <0x7000c400 0x100>; | |
6cecf916 | 416 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
417 | #address-cells = <1>; |
418 | #size-cells = <0>; | |
885a8cfa HD |
419 | clocks = <&tegra_car TEGRA20_CLK_I2C2>, |
420 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
8d8b43da | 421 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
422 | resets = <&tegra_car 54>; |
423 | reset-names = "i2c"; | |
034d023f SW |
424 | dmas = <&apbdma 22>, <&apbdma 22>; |
425 | dma-names = "rx", "tx"; | |
223ef78d | 426 | status = "disabled"; |
8e267f3d GL |
427 | }; |
428 | ||
c04abb3a | 429 | i2c@7000c500 { |
c04abb3a SW |
430 | compatible = "nvidia,tegra20-i2c"; |
431 | reg = <0x7000c500 0x100>; | |
6cecf916 | 432 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
433 | #address-cells = <1>; |
434 | #size-cells = <0>; | |
885a8cfa HD |
435 | clocks = <&tegra_car TEGRA20_CLK_I2C3>, |
436 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
8d8b43da | 437 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
438 | resets = <&tegra_car 67>; |
439 | reset-names = "i2c"; | |
034d023f SW |
440 | dmas = <&apbdma 23>, <&apbdma 23>; |
441 | dma-names = "rx", "tx"; | |
223ef78d | 442 | status = "disabled"; |
8e267f3d GL |
443 | }; |
444 | ||
c04abb3a | 445 | i2c@7000d000 { |
c04abb3a SW |
446 | compatible = "nvidia,tegra20-i2c-dvc"; |
447 | reg = <0x7000d000 0x200>; | |
6cecf916 | 448 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
449 | #address-cells = <1>; |
450 | #size-cells = <0>; | |
885a8cfa HD |
451 | clocks = <&tegra_car TEGRA20_CLK_DVC>, |
452 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
8d8b43da | 453 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
454 | resets = <&tegra_car 47>; |
455 | reset-names = "i2c"; | |
034d023f SW |
456 | dmas = <&apbdma 24>, <&apbdma 24>; |
457 | dma-names = "rx", "tx"; | |
223ef78d | 458 | status = "disabled"; |
8e267f3d GL |
459 | }; |
460 | ||
a86b0db3 LD |
461 | spi@7000d400 { |
462 | compatible = "nvidia,tegra20-slink"; | |
463 | reg = <0x7000d400 0x200>; | |
6cecf916 | 464 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
465 | #address-cells = <1>; |
466 | #size-cells = <0>; | |
885a8cfa | 467 | clocks = <&tegra_car TEGRA20_CLK_SBC1>; |
3393d422 SW |
468 | resets = <&tegra_car 41>; |
469 | reset-names = "spi"; | |
034d023f SW |
470 | dmas = <&apbdma 15>, <&apbdma 15>; |
471 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
472 | status = "disabled"; |
473 | }; | |
474 | ||
475 | spi@7000d600 { | |
476 | compatible = "nvidia,tegra20-slink"; | |
477 | reg = <0x7000d600 0x200>; | |
6cecf916 | 478 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
479 | #address-cells = <1>; |
480 | #size-cells = <0>; | |
885a8cfa | 481 | clocks = <&tegra_car TEGRA20_CLK_SBC2>; |
3393d422 SW |
482 | resets = <&tegra_car 44>; |
483 | reset-names = "spi"; | |
034d023f SW |
484 | dmas = <&apbdma 16>, <&apbdma 16>; |
485 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
486 | status = "disabled"; |
487 | }; | |
488 | ||
489 | spi@7000d800 { | |
490 | compatible = "nvidia,tegra20-slink"; | |
57471c8d | 491 | reg = <0x7000d800 0x200>; |
6cecf916 | 492 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
493 | #address-cells = <1>; |
494 | #size-cells = <0>; | |
885a8cfa | 495 | clocks = <&tegra_car TEGRA20_CLK_SBC3>; |
3393d422 SW |
496 | resets = <&tegra_car 46>; |
497 | reset-names = "spi"; | |
034d023f SW |
498 | dmas = <&apbdma 17>, <&apbdma 17>; |
499 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
500 | status = "disabled"; |
501 | }; | |
502 | ||
503 | spi@7000da00 { | |
504 | compatible = "nvidia,tegra20-slink"; | |
505 | reg = <0x7000da00 0x200>; | |
6cecf916 | 506 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
507 | #address-cells = <1>; |
508 | #size-cells = <0>; | |
885a8cfa | 509 | clocks = <&tegra_car TEGRA20_CLK_SBC4>; |
3393d422 SW |
510 | resets = <&tegra_car 68>; |
511 | reset-names = "spi"; | |
034d023f SW |
512 | dmas = <&apbdma 18>, <&apbdma 18>; |
513 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
514 | status = "disabled"; |
515 | }; | |
516 | ||
58ecb23f | 517 | kbc@7000e200 { |
699ed4b9 LD |
518 | compatible = "nvidia,tegra20-kbc"; |
519 | reg = <0x7000e200 0x100>; | |
6cecf916 | 520 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 521 | clocks = <&tegra_car TEGRA20_CLK_KBC>; |
3393d422 SW |
522 | resets = <&tegra_car 36>; |
523 | reset-names = "kbc"; | |
699ed4b9 LD |
524 | status = "disabled"; |
525 | }; | |
526 | ||
58ecb23f | 527 | pmc@7000e400 { |
c04abb3a SW |
528 | compatible = "nvidia,tegra20-pmc"; |
529 | reg = <0x7000e400 0x400>; | |
885a8cfa | 530 | clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; |
7021d122 | 531 | clock-names = "pclk", "clk32k_in"; |
c04abb3a SW |
532 | }; |
533 | ||
bbfc33bd | 534 | memory-controller@7000f000 { |
c04abb3a SW |
535 | compatible = "nvidia,tegra20-mc"; |
536 | reg = <0x7000f000 0x024 | |
537 | 0x7000f03c 0x3c4>; | |
6cecf916 | 538 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
c04abb3a SW |
539 | }; |
540 | ||
58ecb23f | 541 | iommu@7000f024 { |
c04abb3a SW |
542 | compatible = "nvidia,tegra20-gart"; |
543 | reg = <0x7000f024 0x00000018 /* controller registers */ | |
544 | 0x58000000 0x02000000>; /* GART aperture */ | |
545 | }; | |
546 | ||
bbfc33bd | 547 | memory-controller@7000f400 { |
c04abb3a SW |
548 | compatible = "nvidia,tegra20-emc"; |
549 | reg = <0x7000f400 0x200>; | |
2eaab06e SW |
550 | #address-cells = <1>; |
551 | #size-cells = <0>; | |
8e267f3d | 552 | }; |
c27317c0 | 553 | |
155dfc7b PDS |
554 | fuse@7000f800 { |
555 | compatible = "nvidia,tegra20-efuse"; | |
556 | reg = <0x7000F800 0x400>; | |
557 | clocks = <&tegra_car TEGRA20_CLK_FUSE>; | |
558 | clock-names = "fuse"; | |
559 | resets = <&tegra_car 39>; | |
560 | reset-names = "fuse"; | |
561 | }; | |
562 | ||
58ecb23f | 563 | pcie-controller@80003000 { |
1b62b611 TR |
564 | compatible = "nvidia,tegra20-pcie"; |
565 | device_type = "pci"; | |
566 | reg = <0x80003000 0x00000800 /* PADS registers */ | |
567 | 0x80003800 0x00000200 /* AFI registers */ | |
568 | 0x90000000 0x10000000>; /* configuration space */ | |
569 | reg-names = "pads", "afi", "cs"; | |
570 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ | |
571 | GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ | |
572 | interrupt-names = "intr", "msi"; | |
573 | ||
97070bd4 LS |
574 | #interrupt-cells = <1>; |
575 | interrupt-map-mask = <0 0 0 0>; | |
576 | interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
577 | ||
1b62b611 TR |
578 | bus-range = <0x00 0xff>; |
579 | #address-cells = <3>; | |
580 | #size-cells = <2>; | |
581 | ||
582 | ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ | |
583 | 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ | |
584 | 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ | |
d7283c11 JA |
585 | 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ |
586 | 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ | |
1b62b611 TR |
587 | |
588 | clocks = <&tegra_car TEGRA20_CLK_PEX>, | |
589 | <&tegra_car TEGRA20_CLK_AFI>, | |
1b62b611 | 590 | <&tegra_car TEGRA20_CLK_PLL_E>; |
2bd541ff | 591 | clock-names = "pex", "afi", "pll_e"; |
3393d422 SW |
592 | resets = <&tegra_car 70>, |
593 | <&tegra_car 72>, | |
594 | <&tegra_car 74>; | |
595 | reset-names = "pex", "afi", "pcie_x"; | |
1b62b611 TR |
596 | status = "disabled"; |
597 | ||
598 | pci@1,0 { | |
599 | device_type = "pci"; | |
600 | assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; | |
601 | reg = <0x000800 0 0 0 0>; | |
602 | status = "disabled"; | |
603 | ||
604 | #address-cells = <3>; | |
605 | #size-cells = <2>; | |
606 | ranges; | |
607 | ||
608 | nvidia,num-lanes = <2>; | |
609 | }; | |
610 | ||
611 | pci@2,0 { | |
612 | device_type = "pci"; | |
613 | assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; | |
614 | reg = <0x001000 0 0 0 0>; | |
615 | status = "disabled"; | |
616 | ||
617 | #address-cells = <3>; | |
618 | #size-cells = <2>; | |
619 | ranges; | |
620 | ||
621 | nvidia,num-lanes = <2>; | |
622 | }; | |
623 | }; | |
624 | ||
c27317c0 OJ |
625 | usb@c5000000 { |
626 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | |
627 | reg = <0xc5000000 0x4000>; | |
6cecf916 | 628 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
c27317c0 | 629 | phy_type = "utmi"; |
ba202f15 | 630 | nvidia,has-legacy-mode; |
885a8cfa | 631 | clocks = <&tegra_car TEGRA20_CLK_USBD>; |
3393d422 SW |
632 | resets = <&tegra_car 22>; |
633 | reset-names = "usb"; | |
b4e07478 | 634 | nvidia,needs-double-reset; |
e374b65c | 635 | nvidia,phy = <&phy1>; |
223ef78d | 636 | status = "disabled"; |
c27317c0 OJ |
637 | }; |
638 | ||
4c94c8b5 | 639 | phy1: usb-phy@c5000000 { |
5d324410 | 640 | compatible = "nvidia,tegra20-usb-phy"; |
4c94c8b5 | 641 | reg = <0xc5000000 0x4000 0xc5000000 0x4000>; |
5d324410 | 642 | phy_type = "utmi"; |
885a8cfa HD |
643 | clocks = <&tegra_car TEGRA20_CLK_USBD>, |
644 | <&tegra_car TEGRA20_CLK_PLL_U>, | |
645 | <&tegra_car TEGRA20_CLK_CLK_M>, | |
646 | <&tegra_car TEGRA20_CLK_USBD>; | |
4c94c8b5 | 647 | clock-names = "reg", "pll_u", "timer", "utmi-pads"; |
308efde2 TT |
648 | resets = <&tegra_car 22>, <&tegra_car 22>; |
649 | reset-names = "usb", "utmi-pads"; | |
5d324410 | 650 | nvidia,has-legacy-mode; |
c49667e5 MP |
651 | nvidia,hssync-start-delay = <9>; |
652 | nvidia,idle-wait-delay = <17>; | |
653 | nvidia,elastic-limit = <16>; | |
654 | nvidia,term-range-adj = <6>; | |
655 | nvidia,xcvr-setup = <9>; | |
656 | nvidia,xcvr-lsfslew = <1>; | |
657 | nvidia,xcvr-lsrslew = <1>; | |
308efde2 | 658 | nvidia,has-utmi-pad-registers; |
4c94c8b5 | 659 | status = "disabled"; |
5d324410 SW |
660 | }; |
661 | ||
c27317c0 OJ |
662 | usb@c5004000 { |
663 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | |
664 | reg = <0xc5004000 0x4000>; | |
6cecf916 | 665 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
c27317c0 | 666 | phy_type = "ulpi"; |
885a8cfa | 667 | clocks = <&tegra_car TEGRA20_CLK_USB2>; |
3393d422 SW |
668 | resets = <&tegra_car 58>; |
669 | reset-names = "usb"; | |
e374b65c | 670 | nvidia,phy = <&phy2>; |
223ef78d | 671 | status = "disabled"; |
c27317c0 OJ |
672 | }; |
673 | ||
4c94c8b5 | 674 | phy2: usb-phy@c5004000 { |
5d324410 | 675 | compatible = "nvidia,tegra20-usb-phy"; |
4c94c8b5 | 676 | reg = <0xc5004000 0x4000>; |
5d324410 | 677 | phy_type = "ulpi"; |
885a8cfa HD |
678 | clocks = <&tegra_car TEGRA20_CLK_USB2>, |
679 | <&tegra_car TEGRA20_CLK_PLL_U>, | |
680 | <&tegra_car TEGRA20_CLK_CDEV2>; | |
4c94c8b5 | 681 | clock-names = "reg", "pll_u", "ulpi-link"; |
308efde2 TT |
682 | resets = <&tegra_car 58>, <&tegra_car 22>; |
683 | reset-names = "usb", "utmi-pads"; | |
4c94c8b5 | 684 | status = "disabled"; |
5d324410 SW |
685 | }; |
686 | ||
c27317c0 OJ |
687 | usb@c5008000 { |
688 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | |
689 | reg = <0xc5008000 0x4000>; | |
6cecf916 | 690 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
c27317c0 | 691 | phy_type = "utmi"; |
885a8cfa | 692 | clocks = <&tegra_car TEGRA20_CLK_USB3>; |
3393d422 SW |
693 | resets = <&tegra_car 59>; |
694 | reset-names = "usb"; | |
e374b65c | 695 | nvidia,phy = <&phy3>; |
223ef78d | 696 | status = "disabled"; |
c27317c0 | 697 | }; |
7868a9bc | 698 | |
4c94c8b5 | 699 | phy3: usb-phy@c5008000 { |
5d324410 | 700 | compatible = "nvidia,tegra20-usb-phy"; |
4c94c8b5 | 701 | reg = <0xc5008000 0x4000 0xc5000000 0x4000>; |
5d324410 | 702 | phy_type = "utmi"; |
885a8cfa HD |
703 | clocks = <&tegra_car TEGRA20_CLK_USB3>, |
704 | <&tegra_car TEGRA20_CLK_PLL_U>, | |
705 | <&tegra_car TEGRA20_CLK_CLK_M>, | |
706 | <&tegra_car TEGRA20_CLK_USBD>; | |
4c94c8b5 | 707 | clock-names = "reg", "pll_u", "timer", "utmi-pads"; |
308efde2 TT |
708 | resets = <&tegra_car 59>, <&tegra_car 22>; |
709 | reset-names = "usb", "utmi-pads"; | |
c49667e5 MP |
710 | nvidia,hssync-start-delay = <9>; |
711 | nvidia,idle-wait-delay = <17>; | |
712 | nvidia,elastic-limit = <16>; | |
713 | nvidia,term-range-adj = <6>; | |
714 | nvidia,xcvr-setup = <9>; | |
715 | nvidia,xcvr-lsfslew = <2>; | |
716 | nvidia,xcvr-lsrslew = <2>; | |
4c94c8b5 | 717 | status = "disabled"; |
5d324410 SW |
718 | }; |
719 | ||
c04abb3a SW |
720 | sdhci@c8000000 { |
721 | compatible = "nvidia,tegra20-sdhci"; | |
722 | reg = <0xc8000000 0x200>; | |
6cecf916 | 723 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 724 | clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; |
3393d422 SW |
725 | resets = <&tegra_car 14>; |
726 | reset-names = "sdhci"; | |
223ef78d | 727 | status = "disabled"; |
7868a9bc | 728 | }; |
4a82f2b3 | 729 | |
c04abb3a SW |
730 | sdhci@c8000200 { |
731 | compatible = "nvidia,tegra20-sdhci"; | |
732 | reg = <0xc8000200 0x200>; | |
6cecf916 | 733 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 734 | clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; |
3393d422 SW |
735 | resets = <&tegra_car 9>; |
736 | reset-names = "sdhci"; | |
223ef78d | 737 | status = "disabled"; |
4a82f2b3 | 738 | }; |
6a943e0e | 739 | |
c04abb3a SW |
740 | sdhci@c8000400 { |
741 | compatible = "nvidia,tegra20-sdhci"; | |
742 | reg = <0xc8000400 0x200>; | |
6cecf916 | 743 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 744 | clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; |
3393d422 SW |
745 | resets = <&tegra_car 69>; |
746 | reset-names = "sdhci"; | |
223ef78d | 747 | status = "disabled"; |
c04abb3a SW |
748 | }; |
749 | ||
750 | sdhci@c8000600 { | |
751 | compatible = "nvidia,tegra20-sdhci"; | |
752 | reg = <0xc8000600 0x200>; | |
6cecf916 | 753 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 754 | clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; |
3393d422 SW |
755 | resets = <&tegra_car 15>; |
756 | reset-names = "sdhci"; | |
223ef78d | 757 | status = "disabled"; |
c04abb3a SW |
758 | }; |
759 | ||
4dd2bd37 HD |
760 | cpus { |
761 | #address-cells = <1>; | |
762 | #size-cells = <0>; | |
763 | ||
764 | cpu@0 { | |
765 | device_type = "cpu"; | |
766 | compatible = "arm,cortex-a9"; | |
767 | reg = <0>; | |
768 | }; | |
769 | ||
770 | cpu@1 { | |
771 | device_type = "cpu"; | |
772 | compatible = "arm,cortex-a9"; | |
773 | reg = <1>; | |
774 | }; | |
775 | }; | |
776 | ||
c04abb3a SW |
777 | pmu { |
778 | compatible = "arm,cortex-a9-pmu"; | |
6cecf916 SW |
779 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
780 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
6a943e0e | 781 | }; |
8e267f3d | 782 | }; |