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Commit | Line | Data |
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885a8cfa | 1 | #include <dt-bindings/clock/tegra20-car.h> |
3325f1bc | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
ba4104e7 | 3 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
6cecf916 | 4 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
3325f1bc | 5 | |
1bd0bd49 | 6 | #include "skeleton.dtsi" |
8e267f3d GL |
7 | |
8 | / { | |
9 | compatible = "nvidia,tegra20"; | |
870c81a4 | 10 | interrupt-parent = <&lic>; |
8e267f3d | 11 | |
58ecb23f | 12 | host1x@50000000 { |
ed821f07 TR |
13 | compatible = "nvidia,tegra20-host1x", "simple-bus"; |
14 | reg = <0x50000000 0x00024000>; | |
6cecf916 SW |
15 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
16 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ | |
885a8cfa | 17 | clocks = <&tegra_car TEGRA20_CLK_HOST1X>; |
3393d422 SW |
18 | resets = <&tegra_car 28>; |
19 | reset-names = "host1x"; | |
ed821f07 TR |
20 | |
21 | #address-cells = <1>; | |
22 | #size-cells = <1>; | |
23 | ||
24 | ranges = <0x54000000 0x54000000 0x04000000>; | |
25 | ||
58ecb23f | 26 | mpe@54040000 { |
ed821f07 TR |
27 | compatible = "nvidia,tegra20-mpe"; |
28 | reg = <0x54040000 0x00040000>; | |
6cecf916 | 29 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 30 | clocks = <&tegra_car TEGRA20_CLK_MPE>; |
3393d422 SW |
31 | resets = <&tegra_car 60>; |
32 | reset-names = "mpe"; | |
ed821f07 TR |
33 | }; |
34 | ||
58ecb23f | 35 | vi@54080000 { |
ed821f07 TR |
36 | compatible = "nvidia,tegra20-vi"; |
37 | reg = <0x54080000 0x00040000>; | |
6cecf916 | 38 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 39 | clocks = <&tegra_car TEGRA20_CLK_VI>; |
3393d422 SW |
40 | resets = <&tegra_car 20>; |
41 | reset-names = "vi"; | |
ed821f07 TR |
42 | }; |
43 | ||
58ecb23f | 44 | epp@540c0000 { |
ed821f07 TR |
45 | compatible = "nvidia,tegra20-epp"; |
46 | reg = <0x540c0000 0x00040000>; | |
6cecf916 | 47 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 48 | clocks = <&tegra_car TEGRA20_CLK_EPP>; |
3393d422 SW |
49 | resets = <&tegra_car 19>; |
50 | reset-names = "epp"; | |
ed821f07 TR |
51 | }; |
52 | ||
58ecb23f | 53 | isp@54100000 { |
ed821f07 TR |
54 | compatible = "nvidia,tegra20-isp"; |
55 | reg = <0x54100000 0x00040000>; | |
6cecf916 | 56 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 57 | clocks = <&tegra_car TEGRA20_CLK_ISP>; |
3393d422 SW |
58 | resets = <&tegra_car 23>; |
59 | reset-names = "isp"; | |
ed821f07 TR |
60 | }; |
61 | ||
58ecb23f | 62 | gr2d@54140000 { |
ed821f07 TR |
63 | compatible = "nvidia,tegra20-gr2d"; |
64 | reg = <0x54140000 0x00040000>; | |
6cecf916 | 65 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 66 | clocks = <&tegra_car TEGRA20_CLK_GR2D>; |
3393d422 SW |
67 | resets = <&tegra_car 21>; |
68 | reset-names = "2d"; | |
ed821f07 TR |
69 | }; |
70 | ||
de47699d | 71 | gr3d@54180000 { |
ed821f07 | 72 | compatible = "nvidia,tegra20-gr3d"; |
de47699d | 73 | reg = <0x54180000 0x00040000>; |
885a8cfa | 74 | clocks = <&tegra_car TEGRA20_CLK_GR3D>; |
3393d422 SW |
75 | resets = <&tegra_car 24>; |
76 | reset-names = "3d"; | |
ed821f07 TR |
77 | }; |
78 | ||
79 | dc@54200000 { | |
80 | compatible = "nvidia,tegra20-dc"; | |
81 | reg = <0x54200000 0x00040000>; | |
6cecf916 | 82 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa HD |
83 | clocks = <&tegra_car TEGRA20_CLK_DISP1>, |
84 | <&tegra_car TEGRA20_CLK_PLL_P>; | |
d8f64797 | 85 | clock-names = "dc", "parent"; |
3393d422 SW |
86 | resets = <&tegra_car 27>; |
87 | reset-names = "dc"; | |
ed821f07 | 88 | |
688b56b4 TR |
89 | nvidia,head = <0>; |
90 | ||
ed821f07 TR |
91 | rgb { |
92 | status = "disabled"; | |
93 | }; | |
94 | }; | |
95 | ||
96 | dc@54240000 { | |
97 | compatible = "nvidia,tegra20-dc"; | |
98 | reg = <0x54240000 0x00040000>; | |
6cecf916 | 99 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa HD |
100 | clocks = <&tegra_car TEGRA20_CLK_DISP2>, |
101 | <&tegra_car TEGRA20_CLK_PLL_P>; | |
d8f64797 | 102 | clock-names = "dc", "parent"; |
3393d422 SW |
103 | resets = <&tegra_car 26>; |
104 | reset-names = "dc"; | |
ed821f07 | 105 | |
688b56b4 TR |
106 | nvidia,head = <1>; |
107 | ||
ed821f07 TR |
108 | rgb { |
109 | status = "disabled"; | |
110 | }; | |
111 | }; | |
112 | ||
58ecb23f | 113 | hdmi@54280000 { |
ed821f07 TR |
114 | compatible = "nvidia,tegra20-hdmi"; |
115 | reg = <0x54280000 0x00040000>; | |
6cecf916 | 116 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa HD |
117 | clocks = <&tegra_car TEGRA20_CLK_HDMI>, |
118 | <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; | |
8d8b43da | 119 | clock-names = "hdmi", "parent"; |
3393d422 SW |
120 | resets = <&tegra_car 51>; |
121 | reset-names = "hdmi"; | |
ed821f07 TR |
122 | status = "disabled"; |
123 | }; | |
124 | ||
58ecb23f | 125 | tvo@542c0000 { |
ed821f07 TR |
126 | compatible = "nvidia,tegra20-tvo"; |
127 | reg = <0x542c0000 0x00040000>; | |
6cecf916 | 128 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 129 | clocks = <&tegra_car TEGRA20_CLK_TVO>; |
ed821f07 TR |
130 | status = "disabled"; |
131 | }; | |
132 | ||
de47699d | 133 | dsi@54300000 { |
ed821f07 | 134 | compatible = "nvidia,tegra20-dsi"; |
de47699d | 135 | reg = <0x54300000 0x00040000>; |
885a8cfa | 136 | clocks = <&tegra_car TEGRA20_CLK_DSI>; |
3393d422 SW |
137 | resets = <&tegra_car 48>; |
138 | reset-names = "dsi"; | |
ed821f07 TR |
139 | status = "disabled"; |
140 | }; | |
141 | }; | |
142 | ||
2cda1880 | 143 | timer@50040600 { |
73368ba0 | 144 | compatible = "arm,cortex-a9-twd-timer"; |
870c81a4 | 145 | interrupt-parent = <&intc>; |
73368ba0 | 146 | reg = <0x50040600 0x20>; |
6cecf916 | 147 | interrupts = <GIC_PPI 13 |
e7d9b270 | 148 | (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; |
885a8cfa | 149 | clocks = <&tegra_car TEGRA20_CLK_TWD>; |
73368ba0 SW |
150 | }; |
151 | ||
58ecb23f | 152 | intc: interrupt-controller@50041000 { |
0d4f7479 | 153 | compatible = "arm,cortex-a9-gic"; |
5ff48887 SW |
154 | reg = <0x50041000 0x1000 |
155 | 0x50040100 0x0100>; | |
2eaab06e SW |
156 | interrupt-controller; |
157 | #interrupt-cells = <3>; | |
870c81a4 | 158 | interrupt-parent = <&intc>; |
8e267f3d GL |
159 | }; |
160 | ||
58ecb23f | 161 | cache-controller@50043000 { |
bb2c1de9 SW |
162 | compatible = "arm,pl310-cache"; |
163 | reg = <0x50043000 0x1000>; | |
164 | arm,data-latency = <5 5 2>; | |
165 | arm,tag-latency = <4 4 2>; | |
166 | cache-unified; | |
167 | cache-level = <2>; | |
168 | }; | |
169 | ||
870c81a4 MZ |
170 | lic: interrupt-controller@60004000 { |
171 | compatible = "nvidia,tegra20-ictlr"; | |
172 | reg = <0x60004000 0x100>, | |
173 | <0x60004100 0x50>, | |
174 | <0x60004200 0x50>, | |
175 | <0x60004300 0x50>; | |
176 | interrupt-controller; | |
177 | #interrupt-cells = <3>; | |
178 | interrupt-parent = <&intc>; | |
179 | }; | |
180 | ||
2f2b7fb2 SW |
181 | timer@60005000 { |
182 | compatible = "nvidia,tegra20-timer"; | |
183 | reg = <0x60005000 0x60>; | |
6cecf916 SW |
184 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
185 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
186 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
187 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
885a8cfa | 188 | clocks = <&tegra_car TEGRA20_CLK_TIMER>; |
2f2b7fb2 SW |
189 | }; |
190 | ||
58ecb23f | 191 | tegra_car: clock@60006000 { |
270f8ce3 SW |
192 | compatible = "nvidia,tegra20-car"; |
193 | reg = <0x60006000 0x1000>; | |
194 | #clock-cells = <1>; | |
3393d422 | 195 | #reset-cells = <1>; |
270f8ce3 SW |
196 | }; |
197 | ||
b1023134 TR |
198 | flow-controller@60007000 { |
199 | compatible = "nvidia,tegra20-flowctrl"; | |
200 | reg = <0x60007000 0x1000>; | |
201 | }; | |
202 | ||
58ecb23f | 203 | apbdma: dma@6000a000 { |
8051b75a SW |
204 | compatible = "nvidia,tegra20-apbdma"; |
205 | reg = <0x6000a000 0x1200>; | |
6cecf916 SW |
206 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
207 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
208 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
209 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
210 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
211 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
212 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
213 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
214 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
215 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
216 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
217 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
218 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
219 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
220 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
221 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; | |
885a8cfa | 222 | clocks = <&tegra_car TEGRA20_CLK_APBDMA>; |
3393d422 SW |
223 | resets = <&tegra_car 34>; |
224 | reset-names = "dma"; | |
034d023f | 225 | #dma-cells = <1>; |
8051b75a SW |
226 | }; |
227 | ||
0d5ccb38 | 228 | ahb@6000c000 { |
c04abb3a | 229 | compatible = "nvidia,tegra20-ahb"; |
0d5ccb38 | 230 | reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */ |
8e267f3d GL |
231 | }; |
232 | ||
58ecb23f | 233 | gpio: gpio@6000d000 { |
8e267f3d | 234 | compatible = "nvidia,tegra20-gpio"; |
95decf84 | 235 | reg = <0x6000d000 0x1000>; |
6cecf916 SW |
236 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
237 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
238 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, | |
239 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, | |
240 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
241 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
242 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
8e267f3d GL |
243 | #gpio-cells = <2>; |
244 | gpio-controller; | |
6f74dc9b SW |
245 | #interrupt-cells = <2>; |
246 | interrupt-controller; | |
4f1d8414 | 247 | /* |
17cdddf0 | 248 | gpio-ranges = <&pinmux 0 0 224>; |
4f1d8414 | 249 | */ |
8e267f3d GL |
250 | }; |
251 | ||
155dfc7b PDS |
252 | apbmisc@70000800 { |
253 | compatible = "nvidia,tegra20-apbmisc"; | |
254 | reg = <0x70000800 0x64 /* Chip revision */ | |
255 | 0x70000008 0x04>; /* Strapping options */ | |
256 | }; | |
257 | ||
58ecb23f | 258 | pinmux: pinmux@70000014 { |
f62f548c | 259 | compatible = "nvidia,tegra20-pinmux"; |
95decf84 SW |
260 | reg = <0x70000014 0x10 /* Tri-state registers */ |
261 | 0x70000080 0x20 /* Mux registers */ | |
262 | 0x700000a0 0x14 /* Pull-up/down registers */ | |
263 | 0x70000868 0xa8>; /* Pad control registers */ | |
f62f548c SW |
264 | }; |
265 | ||
58ecb23f | 266 | das@70000c00 { |
c04abb3a SW |
267 | compatible = "nvidia,tegra20-das"; |
268 | reg = <0x70000c00 0x80>; | |
269 | }; | |
fc5c306b | 270 | |
58ecb23f | 271 | tegra_ac97: ac97@70002000 { |
0698ed19 LS |
272 | compatible = "nvidia,tegra20-ac97"; |
273 | reg = <0x70002000 0x200>; | |
6cecf916 | 274 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 275 | clocks = <&tegra_car TEGRA20_CLK_AC97>; |
3393d422 SW |
276 | resets = <&tegra_car 3>; |
277 | reset-names = "ac97"; | |
034d023f SW |
278 | dmas = <&apbdma 12>, <&apbdma 12>; |
279 | dma-names = "rx", "tx"; | |
0698ed19 LS |
280 | status = "disabled"; |
281 | }; | |
c04abb3a SW |
282 | |
283 | tegra_i2s1: i2s@70002800 { | |
284 | compatible = "nvidia,tegra20-i2s"; | |
285 | reg = <0x70002800 0x200>; | |
6cecf916 | 286 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 287 | clocks = <&tegra_car TEGRA20_CLK_I2S1>; |
3393d422 SW |
288 | resets = <&tegra_car 11>; |
289 | reset-names = "i2s"; | |
034d023f SW |
290 | dmas = <&apbdma 2>, <&apbdma 2>; |
291 | dma-names = "rx", "tx"; | |
223ef78d | 292 | status = "disabled"; |
c04abb3a SW |
293 | }; |
294 | ||
295 | tegra_i2s2: i2s@70002a00 { | |
296 | compatible = "nvidia,tegra20-i2s"; | |
297 | reg = <0x70002a00 0x200>; | |
6cecf916 | 298 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 299 | clocks = <&tegra_car TEGRA20_CLK_I2S2>; |
3393d422 SW |
300 | resets = <&tegra_car 18>; |
301 | reset-names = "i2s"; | |
034d023f SW |
302 | dmas = <&apbdma 1>, <&apbdma 1>; |
303 | dma-names = "rx", "tx"; | |
223ef78d | 304 | status = "disabled"; |
c04abb3a SW |
305 | }; |
306 | ||
b6551bb9 LD |
307 | /* |
308 | * There are two serial driver i.e. 8250 based simple serial | |
309 | * driver and APB DMA based serial driver for higher baudrate | |
310 | * and performace. To enable the 8250 based driver, the compatible | |
311 | * is "nvidia,tegra20-uart" and to enable the APB DMA based serial | |
e1098248 | 312 | * driver, the compatible is "nvidia,tegra20-hsuart". |
b6551bb9 LD |
313 | */ |
314 | uarta: serial@70006000 { | |
8e267f3d GL |
315 | compatible = "nvidia,tegra20-uart"; |
316 | reg = <0x70006000 0x40>; | |
317 | reg-shift = <2>; | |
6cecf916 | 318 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 319 | clocks = <&tegra_car TEGRA20_CLK_UARTA>; |
3393d422 SW |
320 | resets = <&tegra_car 6>; |
321 | reset-names = "serial"; | |
034d023f SW |
322 | dmas = <&apbdma 8>, <&apbdma 8>; |
323 | dma-names = "rx", "tx"; | |
223ef78d | 324 | status = "disabled"; |
8e267f3d GL |
325 | }; |
326 | ||
b6551bb9 | 327 | uartb: serial@70006040 { |
8e267f3d GL |
328 | compatible = "nvidia,tegra20-uart"; |
329 | reg = <0x70006040 0x40>; | |
330 | reg-shift = <2>; | |
6cecf916 | 331 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 332 | clocks = <&tegra_car TEGRA20_CLK_UARTB>; |
3393d422 SW |
333 | resets = <&tegra_car 7>; |
334 | reset-names = "serial"; | |
034d023f SW |
335 | dmas = <&apbdma 9>, <&apbdma 9>; |
336 | dma-names = "rx", "tx"; | |
223ef78d | 337 | status = "disabled"; |
8e267f3d GL |
338 | }; |
339 | ||
b6551bb9 | 340 | uartc: serial@70006200 { |
8e267f3d GL |
341 | compatible = "nvidia,tegra20-uart"; |
342 | reg = <0x70006200 0x100>; | |
343 | reg-shift = <2>; | |
6cecf916 | 344 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 345 | clocks = <&tegra_car TEGRA20_CLK_UARTC>; |
3393d422 SW |
346 | resets = <&tegra_car 55>; |
347 | reset-names = "serial"; | |
034d023f SW |
348 | dmas = <&apbdma 10>, <&apbdma 10>; |
349 | dma-names = "rx", "tx"; | |
223ef78d | 350 | status = "disabled"; |
8e267f3d GL |
351 | }; |
352 | ||
b6551bb9 | 353 | uartd: serial@70006300 { |
8e267f3d GL |
354 | compatible = "nvidia,tegra20-uart"; |
355 | reg = <0x70006300 0x100>; | |
356 | reg-shift = <2>; | |
6cecf916 | 357 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 358 | clocks = <&tegra_car TEGRA20_CLK_UARTD>; |
3393d422 SW |
359 | resets = <&tegra_car 65>; |
360 | reset-names = "serial"; | |
034d023f SW |
361 | dmas = <&apbdma 19>, <&apbdma 19>; |
362 | dma-names = "rx", "tx"; | |
223ef78d | 363 | status = "disabled"; |
8e267f3d GL |
364 | }; |
365 | ||
b6551bb9 | 366 | uarte: serial@70006400 { |
8e267f3d GL |
367 | compatible = "nvidia,tegra20-uart"; |
368 | reg = <0x70006400 0x100>; | |
369 | reg-shift = <2>; | |
6cecf916 | 370 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 371 | clocks = <&tegra_car TEGRA20_CLK_UARTE>; |
3393d422 SW |
372 | resets = <&tegra_car 66>; |
373 | reset-names = "serial"; | |
034d023f SW |
374 | dmas = <&apbdma 20>, <&apbdma 20>; |
375 | dma-names = "rx", "tx"; | |
223ef78d | 376 | status = "disabled"; |
8e267f3d GL |
377 | }; |
378 | ||
c1700644 MK |
379 | gmi@70009000 { |
380 | compatible = "nvidia,tegra20-gmi"; | |
381 | reg = <0x70009000 0x1000>; | |
382 | #address-cells = <2>; | |
383 | #size-cells = <1>; | |
384 | ranges = <0 0 0xd0000000 0xfffffff>; | |
385 | clocks = <&tegra_car TEGRA20_CLK_NOR>; | |
386 | clock-names = "gmi"; | |
387 | resets = <&tegra_car 42>; | |
388 | reset-names = "gmi"; | |
389 | status = "disabled"; | |
390 | }; | |
391 | ||
58ecb23f | 392 | pwm: pwm@7000a000 { |
140fd977 TR |
393 | compatible = "nvidia,tegra20-pwm"; |
394 | reg = <0x7000a000 0x100>; | |
395 | #pwm-cells = <2>; | |
885a8cfa | 396 | clocks = <&tegra_car TEGRA20_CLK_PWM>; |
3393d422 SW |
397 | resets = <&tegra_car 17>; |
398 | reset-names = "pwm"; | |
b69cd984 | 399 | status = "disabled"; |
140fd977 TR |
400 | }; |
401 | ||
58ecb23f | 402 | rtc@7000e000 { |
380e04ac SW |
403 | compatible = "nvidia,tegra20-rtc"; |
404 | reg = <0x7000e000 0x100>; | |
6cecf916 | 405 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 406 | clocks = <&tegra_car TEGRA20_CLK_RTC>; |
380e04ac SW |
407 | }; |
408 | ||
c04abb3a | 409 | i2c@7000c000 { |
c04abb3a SW |
410 | compatible = "nvidia,tegra20-i2c"; |
411 | reg = <0x7000c000 0x100>; | |
6cecf916 | 412 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
413 | #address-cells = <1>; |
414 | #size-cells = <0>; | |
885a8cfa HD |
415 | clocks = <&tegra_car TEGRA20_CLK_I2C1>, |
416 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
8d8b43da | 417 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
418 | resets = <&tegra_car 12>; |
419 | reset-names = "i2c"; | |
034d023f SW |
420 | dmas = <&apbdma 21>, <&apbdma 21>; |
421 | dma-names = "rx", "tx"; | |
223ef78d | 422 | status = "disabled"; |
0c6700ab OJ |
423 | }; |
424 | ||
fa98a114 LD |
425 | spi@7000c380 { |
426 | compatible = "nvidia,tegra20-sflash"; | |
427 | reg = <0x7000c380 0x80>; | |
6cecf916 | 428 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
fa98a114 LD |
429 | #address-cells = <1>; |
430 | #size-cells = <0>; | |
885a8cfa | 431 | clocks = <&tegra_car TEGRA20_CLK_SPI>; |
3393d422 SW |
432 | resets = <&tegra_car 43>; |
433 | reset-names = "spi"; | |
034d023f SW |
434 | dmas = <&apbdma 11>, <&apbdma 11>; |
435 | dma-names = "rx", "tx"; | |
fa98a114 LD |
436 | status = "disabled"; |
437 | }; | |
438 | ||
c04abb3a | 439 | i2c@7000c400 { |
c04abb3a SW |
440 | compatible = "nvidia,tegra20-i2c"; |
441 | reg = <0x7000c400 0x100>; | |
6cecf916 | 442 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
443 | #address-cells = <1>; |
444 | #size-cells = <0>; | |
885a8cfa HD |
445 | clocks = <&tegra_car TEGRA20_CLK_I2C2>, |
446 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
8d8b43da | 447 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
448 | resets = <&tegra_car 54>; |
449 | reset-names = "i2c"; | |
034d023f SW |
450 | dmas = <&apbdma 22>, <&apbdma 22>; |
451 | dma-names = "rx", "tx"; | |
223ef78d | 452 | status = "disabled"; |
8e267f3d GL |
453 | }; |
454 | ||
c04abb3a | 455 | i2c@7000c500 { |
c04abb3a SW |
456 | compatible = "nvidia,tegra20-i2c"; |
457 | reg = <0x7000c500 0x100>; | |
6cecf916 | 458 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
459 | #address-cells = <1>; |
460 | #size-cells = <0>; | |
885a8cfa HD |
461 | clocks = <&tegra_car TEGRA20_CLK_I2C3>, |
462 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
8d8b43da | 463 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
464 | resets = <&tegra_car 67>; |
465 | reset-names = "i2c"; | |
034d023f SW |
466 | dmas = <&apbdma 23>, <&apbdma 23>; |
467 | dma-names = "rx", "tx"; | |
223ef78d | 468 | status = "disabled"; |
8e267f3d GL |
469 | }; |
470 | ||
c04abb3a | 471 | i2c@7000d000 { |
c04abb3a SW |
472 | compatible = "nvidia,tegra20-i2c-dvc"; |
473 | reg = <0x7000d000 0x200>; | |
6cecf916 | 474 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
475 | #address-cells = <1>; |
476 | #size-cells = <0>; | |
885a8cfa HD |
477 | clocks = <&tegra_car TEGRA20_CLK_DVC>, |
478 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
8d8b43da | 479 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
480 | resets = <&tegra_car 47>; |
481 | reset-names = "i2c"; | |
034d023f SW |
482 | dmas = <&apbdma 24>, <&apbdma 24>; |
483 | dma-names = "rx", "tx"; | |
223ef78d | 484 | status = "disabled"; |
8e267f3d GL |
485 | }; |
486 | ||
a86b0db3 LD |
487 | spi@7000d400 { |
488 | compatible = "nvidia,tegra20-slink"; | |
489 | reg = <0x7000d400 0x200>; | |
6cecf916 | 490 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
491 | #address-cells = <1>; |
492 | #size-cells = <0>; | |
885a8cfa | 493 | clocks = <&tegra_car TEGRA20_CLK_SBC1>; |
3393d422 SW |
494 | resets = <&tegra_car 41>; |
495 | reset-names = "spi"; | |
034d023f SW |
496 | dmas = <&apbdma 15>, <&apbdma 15>; |
497 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
498 | status = "disabled"; |
499 | }; | |
500 | ||
501 | spi@7000d600 { | |
502 | compatible = "nvidia,tegra20-slink"; | |
503 | reg = <0x7000d600 0x200>; | |
6cecf916 | 504 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
505 | #address-cells = <1>; |
506 | #size-cells = <0>; | |
885a8cfa | 507 | clocks = <&tegra_car TEGRA20_CLK_SBC2>; |
3393d422 SW |
508 | resets = <&tegra_car 44>; |
509 | reset-names = "spi"; | |
034d023f SW |
510 | dmas = <&apbdma 16>, <&apbdma 16>; |
511 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
512 | status = "disabled"; |
513 | }; | |
514 | ||
515 | spi@7000d800 { | |
516 | compatible = "nvidia,tegra20-slink"; | |
57471c8d | 517 | reg = <0x7000d800 0x200>; |
6cecf916 | 518 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
519 | #address-cells = <1>; |
520 | #size-cells = <0>; | |
885a8cfa | 521 | clocks = <&tegra_car TEGRA20_CLK_SBC3>; |
3393d422 SW |
522 | resets = <&tegra_car 46>; |
523 | reset-names = "spi"; | |
034d023f SW |
524 | dmas = <&apbdma 17>, <&apbdma 17>; |
525 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
526 | status = "disabled"; |
527 | }; | |
528 | ||
529 | spi@7000da00 { | |
530 | compatible = "nvidia,tegra20-slink"; | |
531 | reg = <0x7000da00 0x200>; | |
6cecf916 | 532 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
533 | #address-cells = <1>; |
534 | #size-cells = <0>; | |
885a8cfa | 535 | clocks = <&tegra_car TEGRA20_CLK_SBC4>; |
3393d422 SW |
536 | resets = <&tegra_car 68>; |
537 | reset-names = "spi"; | |
034d023f SW |
538 | dmas = <&apbdma 18>, <&apbdma 18>; |
539 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
540 | status = "disabled"; |
541 | }; | |
542 | ||
58ecb23f | 543 | kbc@7000e200 { |
699ed4b9 LD |
544 | compatible = "nvidia,tegra20-kbc"; |
545 | reg = <0x7000e200 0x100>; | |
6cecf916 | 546 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 547 | clocks = <&tegra_car TEGRA20_CLK_KBC>; |
3393d422 SW |
548 | resets = <&tegra_car 36>; |
549 | reset-names = "kbc"; | |
699ed4b9 LD |
550 | status = "disabled"; |
551 | }; | |
552 | ||
58ecb23f | 553 | pmc@7000e400 { |
c04abb3a SW |
554 | compatible = "nvidia,tegra20-pmc"; |
555 | reg = <0x7000e400 0x400>; | |
885a8cfa | 556 | clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; |
7021d122 | 557 | clock-names = "pclk", "clk32k_in"; |
c04abb3a SW |
558 | }; |
559 | ||
bbfc33bd | 560 | memory-controller@7000f000 { |
c04abb3a SW |
561 | compatible = "nvidia,tegra20-mc"; |
562 | reg = <0x7000f000 0x024 | |
563 | 0x7000f03c 0x3c4>; | |
6cecf916 | 564 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
c04abb3a SW |
565 | }; |
566 | ||
58ecb23f | 567 | iommu@7000f024 { |
c04abb3a SW |
568 | compatible = "nvidia,tegra20-gart"; |
569 | reg = <0x7000f024 0x00000018 /* controller registers */ | |
570 | 0x58000000 0x02000000>; /* GART aperture */ | |
571 | }; | |
572 | ||
bbfc33bd | 573 | memory-controller@7000f400 { |
c04abb3a SW |
574 | compatible = "nvidia,tegra20-emc"; |
575 | reg = <0x7000f400 0x200>; | |
2eaab06e SW |
576 | #address-cells = <1>; |
577 | #size-cells = <0>; | |
8e267f3d | 578 | }; |
c27317c0 | 579 | |
155dfc7b PDS |
580 | fuse@7000f800 { |
581 | compatible = "nvidia,tegra20-efuse"; | |
5431b0fd | 582 | reg = <0x7000f800 0x400>; |
155dfc7b PDS |
583 | clocks = <&tegra_car TEGRA20_CLK_FUSE>; |
584 | clock-names = "fuse"; | |
585 | resets = <&tegra_car 39>; | |
586 | reset-names = "fuse"; | |
587 | }; | |
588 | ||
58ecb23f | 589 | pcie-controller@80003000 { |
1b62b611 TR |
590 | compatible = "nvidia,tegra20-pcie"; |
591 | device_type = "pci"; | |
592 | reg = <0x80003000 0x00000800 /* PADS registers */ | |
593 | 0x80003800 0x00000200 /* AFI registers */ | |
594 | 0x90000000 0x10000000>; /* configuration space */ | |
595 | reg-names = "pads", "afi", "cs"; | |
596 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ | |
597 | GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ | |
598 | interrupt-names = "intr", "msi"; | |
599 | ||
97070bd4 LS |
600 | #interrupt-cells = <1>; |
601 | interrupt-map-mask = <0 0 0 0>; | |
602 | interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
603 | ||
1b62b611 TR |
604 | bus-range = <0x00 0xff>; |
605 | #address-cells = <3>; | |
606 | #size-cells = <2>; | |
607 | ||
608 | ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ | |
609 | 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ | |
610 | 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ | |
d7283c11 JA |
611 | 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ |
612 | 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ | |
1b62b611 TR |
613 | |
614 | clocks = <&tegra_car TEGRA20_CLK_PEX>, | |
615 | <&tegra_car TEGRA20_CLK_AFI>, | |
1b62b611 | 616 | <&tegra_car TEGRA20_CLK_PLL_E>; |
2bd541ff | 617 | clock-names = "pex", "afi", "pll_e"; |
3393d422 | 618 | resets = <&tegra_car 70>, |
d8b316b2 MZ |
619 | <&tegra_car 72>, |
620 | <&tegra_car 74>; | |
3393d422 | 621 | reset-names = "pex", "afi", "pcie_x"; |
1b62b611 TR |
622 | status = "disabled"; |
623 | ||
624 | pci@1,0 { | |
625 | device_type = "pci"; | |
626 | assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; | |
627 | reg = <0x000800 0 0 0 0>; | |
628 | status = "disabled"; | |
629 | ||
630 | #address-cells = <3>; | |
631 | #size-cells = <2>; | |
632 | ranges; | |
633 | ||
634 | nvidia,num-lanes = <2>; | |
635 | }; | |
636 | ||
637 | pci@2,0 { | |
638 | device_type = "pci"; | |
639 | assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; | |
640 | reg = <0x001000 0 0 0 0>; | |
641 | status = "disabled"; | |
642 | ||
643 | #address-cells = <3>; | |
644 | #size-cells = <2>; | |
645 | ranges; | |
646 | ||
647 | nvidia,num-lanes = <2>; | |
648 | }; | |
649 | }; | |
650 | ||
c27317c0 OJ |
651 | usb@c5000000 { |
652 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | |
653 | reg = <0xc5000000 0x4000>; | |
6cecf916 | 654 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
c27317c0 | 655 | phy_type = "utmi"; |
ba202f15 | 656 | nvidia,has-legacy-mode; |
885a8cfa | 657 | clocks = <&tegra_car TEGRA20_CLK_USBD>; |
3393d422 SW |
658 | resets = <&tegra_car 22>; |
659 | reset-names = "usb"; | |
b4e07478 | 660 | nvidia,needs-double-reset; |
e374b65c | 661 | nvidia,phy = <&phy1>; |
223ef78d | 662 | status = "disabled"; |
c27317c0 OJ |
663 | }; |
664 | ||
4c94c8b5 | 665 | phy1: usb-phy@c5000000 { |
5d324410 | 666 | compatible = "nvidia,tegra20-usb-phy"; |
4c94c8b5 | 667 | reg = <0xc5000000 0x4000 0xc5000000 0x4000>; |
5d324410 | 668 | phy_type = "utmi"; |
885a8cfa HD |
669 | clocks = <&tegra_car TEGRA20_CLK_USBD>, |
670 | <&tegra_car TEGRA20_CLK_PLL_U>, | |
671 | <&tegra_car TEGRA20_CLK_CLK_M>, | |
672 | <&tegra_car TEGRA20_CLK_USBD>; | |
4c94c8b5 | 673 | clock-names = "reg", "pll_u", "timer", "utmi-pads"; |
308efde2 TT |
674 | resets = <&tegra_car 22>, <&tegra_car 22>; |
675 | reset-names = "usb", "utmi-pads"; | |
5d324410 | 676 | nvidia,has-legacy-mode; |
c49667e5 MP |
677 | nvidia,hssync-start-delay = <9>; |
678 | nvidia,idle-wait-delay = <17>; | |
679 | nvidia,elastic-limit = <16>; | |
680 | nvidia,term-range-adj = <6>; | |
681 | nvidia,xcvr-setup = <9>; | |
682 | nvidia,xcvr-lsfslew = <1>; | |
683 | nvidia,xcvr-lsrslew = <1>; | |
308efde2 | 684 | nvidia,has-utmi-pad-registers; |
4c94c8b5 | 685 | status = "disabled"; |
5d324410 SW |
686 | }; |
687 | ||
c27317c0 OJ |
688 | usb@c5004000 { |
689 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | |
690 | reg = <0xc5004000 0x4000>; | |
6cecf916 | 691 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
c27317c0 | 692 | phy_type = "ulpi"; |
885a8cfa | 693 | clocks = <&tegra_car TEGRA20_CLK_USB2>; |
3393d422 SW |
694 | resets = <&tegra_car 58>; |
695 | reset-names = "usb"; | |
e374b65c | 696 | nvidia,phy = <&phy2>; |
223ef78d | 697 | status = "disabled"; |
c27317c0 OJ |
698 | }; |
699 | ||
4c94c8b5 | 700 | phy2: usb-phy@c5004000 { |
5d324410 | 701 | compatible = "nvidia,tegra20-usb-phy"; |
4c94c8b5 | 702 | reg = <0xc5004000 0x4000>; |
5d324410 | 703 | phy_type = "ulpi"; |
885a8cfa HD |
704 | clocks = <&tegra_car TEGRA20_CLK_USB2>, |
705 | <&tegra_car TEGRA20_CLK_PLL_U>, | |
706 | <&tegra_car TEGRA20_CLK_CDEV2>; | |
4c94c8b5 | 707 | clock-names = "reg", "pll_u", "ulpi-link"; |
308efde2 TT |
708 | resets = <&tegra_car 58>, <&tegra_car 22>; |
709 | reset-names = "usb", "utmi-pads"; | |
4c94c8b5 | 710 | status = "disabled"; |
5d324410 SW |
711 | }; |
712 | ||
c27317c0 OJ |
713 | usb@c5008000 { |
714 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | |
715 | reg = <0xc5008000 0x4000>; | |
6cecf916 | 716 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
c27317c0 | 717 | phy_type = "utmi"; |
885a8cfa | 718 | clocks = <&tegra_car TEGRA20_CLK_USB3>; |
3393d422 SW |
719 | resets = <&tegra_car 59>; |
720 | reset-names = "usb"; | |
e374b65c | 721 | nvidia,phy = <&phy3>; |
223ef78d | 722 | status = "disabled"; |
c27317c0 | 723 | }; |
7868a9bc | 724 | |
4c94c8b5 | 725 | phy3: usb-phy@c5008000 { |
5d324410 | 726 | compatible = "nvidia,tegra20-usb-phy"; |
4c94c8b5 | 727 | reg = <0xc5008000 0x4000 0xc5000000 0x4000>; |
5d324410 | 728 | phy_type = "utmi"; |
885a8cfa HD |
729 | clocks = <&tegra_car TEGRA20_CLK_USB3>, |
730 | <&tegra_car TEGRA20_CLK_PLL_U>, | |
731 | <&tegra_car TEGRA20_CLK_CLK_M>, | |
732 | <&tegra_car TEGRA20_CLK_USBD>; | |
4c94c8b5 | 733 | clock-names = "reg", "pll_u", "timer", "utmi-pads"; |
308efde2 TT |
734 | resets = <&tegra_car 59>, <&tegra_car 22>; |
735 | reset-names = "usb", "utmi-pads"; | |
c49667e5 MP |
736 | nvidia,hssync-start-delay = <9>; |
737 | nvidia,idle-wait-delay = <17>; | |
738 | nvidia,elastic-limit = <16>; | |
739 | nvidia,term-range-adj = <6>; | |
740 | nvidia,xcvr-setup = <9>; | |
741 | nvidia,xcvr-lsfslew = <2>; | |
742 | nvidia,xcvr-lsrslew = <2>; | |
4c94c8b5 | 743 | status = "disabled"; |
5d324410 SW |
744 | }; |
745 | ||
c04abb3a SW |
746 | sdhci@c8000000 { |
747 | compatible = "nvidia,tegra20-sdhci"; | |
748 | reg = <0xc8000000 0x200>; | |
6cecf916 | 749 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 750 | clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; |
3393d422 SW |
751 | resets = <&tegra_car 14>; |
752 | reset-names = "sdhci"; | |
223ef78d | 753 | status = "disabled"; |
7868a9bc | 754 | }; |
4a82f2b3 | 755 | |
c04abb3a SW |
756 | sdhci@c8000200 { |
757 | compatible = "nvidia,tegra20-sdhci"; | |
758 | reg = <0xc8000200 0x200>; | |
6cecf916 | 759 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 760 | clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; |
3393d422 SW |
761 | resets = <&tegra_car 9>; |
762 | reset-names = "sdhci"; | |
223ef78d | 763 | status = "disabled"; |
4a82f2b3 | 764 | }; |
6a943e0e | 765 | |
c04abb3a SW |
766 | sdhci@c8000400 { |
767 | compatible = "nvidia,tegra20-sdhci"; | |
768 | reg = <0xc8000400 0x200>; | |
6cecf916 | 769 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 770 | clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; |
3393d422 SW |
771 | resets = <&tegra_car 69>; |
772 | reset-names = "sdhci"; | |
223ef78d | 773 | status = "disabled"; |
c04abb3a SW |
774 | }; |
775 | ||
776 | sdhci@c8000600 { | |
777 | compatible = "nvidia,tegra20-sdhci"; | |
778 | reg = <0xc8000600 0x200>; | |
6cecf916 | 779 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 780 | clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; |
3393d422 SW |
781 | resets = <&tegra_car 15>; |
782 | reset-names = "sdhci"; | |
223ef78d | 783 | status = "disabled"; |
c04abb3a SW |
784 | }; |
785 | ||
4dd2bd37 HD |
786 | cpus { |
787 | #address-cells = <1>; | |
788 | #size-cells = <0>; | |
789 | ||
790 | cpu@0 { | |
791 | device_type = "cpu"; | |
792 | compatible = "arm,cortex-a9"; | |
793 | reg = <0>; | |
794 | }; | |
795 | ||
796 | cpu@1 { | |
797 | device_type = "cpu"; | |
798 | compatible = "arm,cortex-a9"; | |
799 | reg = <1>; | |
800 | }; | |
801 | }; | |
802 | ||
c04abb3a SW |
803 | pmu { |
804 | compatible = "arm,cortex-a9-pmu"; | |
6cecf916 SW |
805 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
806 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
6a943e0e | 807 | }; |
8e267f3d | 808 | }; |