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Merge remote-tracking branches 'asoc/topic/rcar', 'asoc/topic/reg-default', 'asoc...
[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / tegra20.dtsi
CommitLineData
885a8cfa 1#include <dt-bindings/clock/tegra20-car.h>
3325f1bc 2#include <dt-bindings/gpio/tegra-gpio.h>
ba4104e7 3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6cecf916 4#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 5
1bd0bd49 6#include "skeleton.dtsi"
8e267f3d
GL		 7
8/ {
9 compatible = "nvidia,tegra20";
870c81a4 10 interrupt-parent = <&lic>;
8e267f3d 11
58ecb23f 12 host1x@50000000 {
ed821f07
TR		 13 compatible = "nvidia,tegra20-host1x", "simple-bus";
14 reg = <0x50000000 0x00024000>;
6cecf916
SW		 15 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
16 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
885a8cfa 17 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
3393d422
SW		 18 resets = <&tegra_car 28>;
19 reset-names = "host1x";
ed821f07
TR		 20
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 ranges = <0x54000000 0x54000000 0x04000000>;
25
58ecb23f 26 mpe@54040000 {
ed821f07
TR		 27 compatible = "nvidia,tegra20-mpe";
28 reg = <0x54040000 0x00040000>;
6cecf916 29 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 30 clocks = <&tegra_car TEGRA20_CLK_MPE>;
3393d422
SW		 31 resets = <&tegra_car 60>;
32 reset-names = "mpe";
ed821f07
TR		 33 };
34
58ecb23f 35 vi@54080000 {
ed821f07
TR		 36 compatible = "nvidia,tegra20-vi";
37 reg = <0x54080000 0x00040000>;
6cecf916 38 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 39 clocks = <&tegra_car TEGRA20_CLK_VI>;
3393d422
SW		 40 resets = <&tegra_car 20>;
41 reset-names = "vi";
ed821f07
TR		 42 };
43
58ecb23f 44 epp@540c0000 {
ed821f07
TR		 45 compatible = "nvidia,tegra20-epp";
46 reg = <0x540c0000 0x00040000>;
6cecf916 47 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 48 clocks = <&tegra_car TEGRA20_CLK_EPP>;
3393d422
SW		 49 resets = <&tegra_car 19>;
50 reset-names = "epp";
ed821f07
TR		 51 };
52
58ecb23f 53 isp@54100000 {
ed821f07
TR		 54 compatible = "nvidia,tegra20-isp";
55 reg = <0x54100000 0x00040000>;
6cecf916 56 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 57 clocks = <&tegra_car TEGRA20_CLK_ISP>;
3393d422
SW		 58 resets = <&tegra_car 23>;
59 reset-names = "isp";
ed821f07
TR		 60 };
61
58ecb23f 62 gr2d@54140000 {
ed821f07
TR		 63 compatible = "nvidia,tegra20-gr2d";
64 reg = <0x54140000 0x00040000>;
6cecf916 65 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 66 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
3393d422
SW		 67 resets = <&tegra_car 21>;
68 reset-names = "2d";
ed821f07
TR		 69 };
70
de47699d 71 gr3d@54180000 {
ed821f07 72 compatible = "nvidia,tegra20-gr3d";
de47699d 73 reg = <0x54180000 0x00040000>;
885a8cfa 74 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
3393d422
SW		 75 resets = <&tegra_car 24>;
76 reset-names = "3d";
ed821f07
TR		 77 };
78
79 dc@54200000 {
80 compatible = "nvidia,tegra20-dc";
81 reg = <0x54200000 0x00040000>;
6cecf916 82 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 83 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
84 <&tegra_car TEGRA20_CLK_PLL_P>;
d8f64797 85 clock-names = "dc", "parent";
3393d422
SW		 86 resets = <&tegra_car 27>;
87 reset-names = "dc";
ed821f07 88
688b56b4
TR		 89 nvidia,head = <0>;
90
ed821f07
TR		 91 rgb {
92 status = "disabled";
93 };
94 };
95
96 dc@54240000 {
97 compatible = "nvidia,tegra20-dc";
98 reg = <0x54240000 0x00040000>;
6cecf916 99 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 100 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
101 <&tegra_car TEGRA20_CLK_PLL_P>;
d8f64797 102 clock-names = "dc", "parent";
3393d422
SW		 103 resets = <&tegra_car 26>;
104 reset-names = "dc";
ed821f07 105
688b56b4
TR		 106 nvidia,head = <1>;
107
ed821f07
TR		 108 rgb {
109 status = "disabled";
110 };
111 };
112
58ecb23f 113 hdmi@54280000 {
ed821f07
TR		 114 compatible = "nvidia,tegra20-hdmi";
115 reg = <0x54280000 0x00040000>;
6cecf916 116 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 117 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
118 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
8d8b43da 119 clock-names = "hdmi", "parent";
3393d422
SW		 120 resets = <&tegra_car 51>;
121 reset-names = "hdmi";
ed821f07
TR		 122 status = "disabled";
123 };
124
58ecb23f 125 tvo@542c0000 {
ed821f07
TR		 126 compatible = "nvidia,tegra20-tvo";
127 reg = <0x542c0000 0x00040000>;
6cecf916 128 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 129 clocks = <&tegra_car TEGRA20_CLK_TVO>;
ed821f07
TR		 130 status = "disabled";
131 };
132
de47699d 133 dsi@54300000 {
ed821f07 134 compatible = "nvidia,tegra20-dsi";
de47699d 135 reg = <0x54300000 0x00040000>;
885a8cfa 136 clocks = <&tegra_car TEGRA20_CLK_DSI>;
3393d422
SW		 137 resets = <&tegra_car 48>;
138 reset-names = "dsi";
ed821f07
TR		 139 status = "disabled";
140 };
141 };
142
2cda1880 143 timer@50040600 {
73368ba0 144 compatible = "arm,cortex-a9-twd-timer";
870c81a4 145 interrupt-parent = <&intc>;
73368ba0 146 reg = <0x50040600 0x20>;
6cecf916
SW		 147 interrupts = <GIC_PPI 13
148 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
885a8cfa 149 clocks = <&tegra_car TEGRA20_CLK_TWD>;
73368ba0
SW		 150 };
151
58ecb23f 152 intc: interrupt-controller@50041000 {
0d4f7479 153 compatible = "arm,cortex-a9-gic";
5ff48887
SW		 154 reg = <0x50041000 0x1000
155 0x50040100 0x0100>;
2eaab06e
SW		 156 interrupt-controller;
157 #interrupt-cells = <3>;
870c81a4 158 interrupt-parent = <&intc>;
8e267f3d
GL		 159 };
160
58ecb23f 161 cache-controller@50043000 {
bb2c1de9
SW		 162 compatible = "arm,pl310-cache";
163 reg = <0x50043000 0x1000>;
164 arm,data-latency = <5 5 2>;
165 arm,tag-latency = <4 4 2>;
166 cache-unified;
167 cache-level = <2>;
168 };
169
870c81a4
MZ		 170 lic: interrupt-controller@60004000 {
171 compatible = "nvidia,tegra20-ictlr";
172 reg = <0x60004000 0x100>,
173 <0x60004100 0x50>,
174 <0x60004200 0x50>,
175 <0x60004300 0x50>;
176 interrupt-controller;
177 #interrupt-cells = <3>;
178 interrupt-parent = <&intc>;
179 };
180
2f2b7fb2
SW		 181 timer@60005000 {
182 compatible = "nvidia,tegra20-timer";
183 reg = <0x60005000 0x60>;
6cecf916
SW		 184 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 188 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
2f2b7fb2
SW		 189 };
190
58ecb23f 191 tegra_car: clock@60006000 {
270f8ce3
SW		 192 compatible = "nvidia,tegra20-car";
193 reg = <0x60006000 0x1000>;
194 #clock-cells = <1>;
3393d422 195 #reset-cells = <1>;
270f8ce3
SW		 196 };
197
b1023134
TR		 198 flow-controller@60007000 {
199 compatible = "nvidia,tegra20-flowctrl";
200 reg = <0x60007000 0x1000>;
201 };
202
58ecb23f 203 apbdma: dma@6000a000 {
8051b75a
SW		 204 compatible = "nvidia,tegra20-apbdma";
205 reg = <0x6000a000 0x1200>;
6cecf916
SW		 206 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 222 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
3393d422
SW		 223 resets = <&tegra_car 34>;
224 reset-names = "dma";
034d023f 225 #dma-cells = <1>;
8051b75a
SW		 226 };
227
58ecb23f 228 ahb@6000c004 {
c04abb3a
SW		 229 compatible = "nvidia,tegra20-ahb";
230 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
8e267f3d
GL		 231 };
232
58ecb23f 233 gpio: gpio@6000d000 {
8e267f3d 234 compatible = "nvidia,tegra20-gpio";
95decf84 235 reg = <0x6000d000 0x1000>;
6cecf916
SW		 236 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
8e267f3d
GL		 243 #gpio-cells = <2>;
244 gpio-controller;
6f74dc9b
SW		 245 #interrupt-cells = <2>;
246 interrupt-controller;
8e267f3d
GL		 247 };
248
155dfc7b
PDS		 249 apbmisc@70000800 {
250 compatible = "nvidia,tegra20-apbmisc";
251 reg = <0x70000800 0x64 /* Chip revision */
252 0x70000008 0x04>; /* Strapping options */
253 };
254
58ecb23f 255 pinmux: pinmux@70000014 {
f62f548c 256 compatible = "nvidia,tegra20-pinmux";
95decf84
SW		 257 reg = <0x70000014 0x10 /* Tri-state registers */
258 0x70000080 0x20 /* Mux registers */
259 0x700000a0 0x14 /* Pull-up/down registers */
260 0x70000868 0xa8>; /* Pad control registers */
f62f548c
SW		 261 };
262
58ecb23f 263 das@70000c00 {
c04abb3a
SW		 264 compatible = "nvidia,tegra20-das";
265 reg = <0x70000c00 0x80>;
266 };
fc5c306b 267
58ecb23f 268 tegra_ac97: ac97@70002000 {
0698ed19
LS		 269 compatible = "nvidia,tegra20-ac97";
270 reg = <0x70002000 0x200>;
6cecf916 271 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 272 clocks = <&tegra_car TEGRA20_CLK_AC97>;
3393d422
SW		 273 resets = <&tegra_car 3>;
274 reset-names = "ac97";
034d023f
SW		 275 dmas = <&apbdma 12>, <&apbdma 12>;
276 dma-names = "rx", "tx";
0698ed19
LS		 277 status = "disabled";
278 };
c04abb3a
SW		 279
280 tegra_i2s1: i2s@70002800 {
281 compatible = "nvidia,tegra20-i2s";
282 reg = <0x70002800 0x200>;
6cecf916 283 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 284 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
3393d422
SW		 285 resets = <&tegra_car 11>;
286 reset-names = "i2s";
034d023f
SW		 287 dmas = <&apbdma 2>, <&apbdma 2>;
288 dma-names = "rx", "tx";
223ef78d 289 status = "disabled";
c04abb3a
SW		 290 };
291
292 tegra_i2s2: i2s@70002a00 {
293 compatible = "nvidia,tegra20-i2s";
294 reg = <0x70002a00 0x200>;
6cecf916 295 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 296 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
3393d422
SW		 297 resets = <&tegra_car 18>;
298 reset-names = "i2s";
034d023f
SW		 299 dmas = <&apbdma 1>, <&apbdma 1>;
300 dma-names = "rx", "tx";
223ef78d 301 status = "disabled";
c04abb3a
SW		 302 };
303
b6551bb9
LD		 304 /*
305 * There are two serial driver i.e. 8250 based simple serial
306 * driver and APB DMA based serial driver for higher baudrate
307 * and performace. To enable the 8250 based driver, the compatible
308 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
309 * driver, the comptible is "nvidia,tegra20-hsuart".
310 */
311 uarta: serial@70006000 {
8e267f3d
GL		 312 compatible = "nvidia,tegra20-uart";
313 reg = <0x70006000 0x40>;
314 reg-shift = <2>;
6cecf916 315 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 316 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
3393d422
SW		 317 resets = <&tegra_car 6>;
318 reset-names = "serial";
034d023f
SW		 319 dmas = <&apbdma 8>, <&apbdma 8>;
320 dma-names = "rx", "tx";
223ef78d 321 status = "disabled";
8e267f3d
GL		 322 };
323
b6551bb9 324 uartb: serial@70006040 {
8e267f3d
GL		 325 compatible = "nvidia,tegra20-uart";
326 reg = <0x70006040 0x40>;
327 reg-shift = <2>;
6cecf916 328 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 329 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
3393d422
SW		 330 resets = <&tegra_car 7>;
331 reset-names = "serial";
034d023f
SW		 332 dmas = <&apbdma 9>, <&apbdma 9>;
333 dma-names = "rx", "tx";
223ef78d 334 status = "disabled";
8e267f3d
GL		 335 };
336
b6551bb9 337 uartc: serial@70006200 {
8e267f3d
GL		 338 compatible = "nvidia,tegra20-uart";
339 reg = <0x70006200 0x100>;
340 reg-shift = <2>;
6cecf916 341 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 342 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
3393d422
SW		 343 resets = <&tegra_car 55>;
344 reset-names = "serial";
034d023f
SW		 345 dmas = <&apbdma 10>, <&apbdma 10>;
346 dma-names = "rx", "tx";
223ef78d 347 status = "disabled";
8e267f3d
GL		 348 };
349
b6551bb9 350 uartd: serial@70006300 {
8e267f3d
GL		 351 compatible = "nvidia,tegra20-uart";
352 reg = <0x70006300 0x100>;
353 reg-shift = <2>;
6cecf916 354 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 355 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
3393d422
SW		 356 resets = <&tegra_car 65>;
357 reset-names = "serial";
034d023f
SW		 358 dmas = <&apbdma 19>, <&apbdma 19>;
359 dma-names = "rx", "tx";
223ef78d 360 status = "disabled";
8e267f3d
GL		 361 };
362
b6551bb9 363 uarte: serial@70006400 {
8e267f3d
GL		 364 compatible = "nvidia,tegra20-uart";
365 reg = <0x70006400 0x100>;
366 reg-shift = <2>;
6cecf916 367 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 368 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
3393d422
SW		 369 resets = <&tegra_car 66>;
370 reset-names = "serial";
034d023f
SW		 371 dmas = <&apbdma 20>, <&apbdma 20>;
372 dma-names = "rx", "tx";
223ef78d 373 status = "disabled";
8e267f3d
GL		 374 };
375
58ecb23f 376 pwm: pwm@7000a000 {
140fd977
TR		 377 compatible = "nvidia,tegra20-pwm";
378 reg = <0x7000a000 0x100>;
379 #pwm-cells = <2>;
885a8cfa 380 clocks = <&tegra_car TEGRA20_CLK_PWM>;
3393d422
SW		 381 resets = <&tegra_car 17>;
382 reset-names = "pwm";
b69cd984 383 status = "disabled";
140fd977
TR		 384 };
385
58ecb23f 386 rtc@7000e000 {
380e04ac
SW		 387 compatible = "nvidia,tegra20-rtc";
388 reg = <0x7000e000 0x100>;
6cecf916 389 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 390 clocks = <&tegra_car TEGRA20_CLK_RTC>;
380e04ac
SW		 391 };
392
c04abb3a 393 i2c@7000c000 {
c04abb3a
SW		 394 compatible = "nvidia,tegra20-i2c";
395 reg = <0x7000c000 0x100>;
6cecf916 396 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 397 #address-cells = <1>;
398 #size-cells = <0>;
885a8cfa
HD		 399 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
400 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 401 clock-names = "div-clk", "fast-clk";
3393d422
SW		 402 resets = <&tegra_car 12>;
403 reset-names = "i2c";
034d023f
SW		 404 dmas = <&apbdma 21>, <&apbdma 21>;
405 dma-names = "rx", "tx";
223ef78d 406 status = "disabled";
0c6700ab
OJ		 407 };
408
fa98a114
LD		 409 spi@7000c380 {
410 compatible = "nvidia,tegra20-sflash";
411 reg = <0x7000c380 0x80>;
6cecf916 412 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
fa98a114
LD		 413 #address-cells = <1>;
414 #size-cells = <0>;
885a8cfa 415 clocks = <&tegra_car TEGRA20_CLK_SPI>;
3393d422
SW		 416 resets = <&tegra_car 43>;
417 reset-names = "spi";
034d023f
SW		 418 dmas = <&apbdma 11>, <&apbdma 11>;
419 dma-names = "rx", "tx";
fa98a114
LD		 420 status = "disabled";
421 };
422
c04abb3a 423 i2c@7000c400 {
c04abb3a
SW		 424 compatible = "nvidia,tegra20-i2c";
425 reg = <0x7000c400 0x100>;
6cecf916 426 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 427 #address-cells = <1>;
428 #size-cells = <0>;
885a8cfa
HD		 429 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
430 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 431 clock-names = "div-clk", "fast-clk";
3393d422
SW		 432 resets = <&tegra_car 54>;
433 reset-names = "i2c";
034d023f
SW		 434 dmas = <&apbdma 22>, <&apbdma 22>;
435 dma-names = "rx", "tx";
223ef78d 436 status = "disabled";
8e267f3d
GL		 437 };
438
c04abb3a 439 i2c@7000c500 {
c04abb3a
SW		 440 compatible = "nvidia,tegra20-i2c";
441 reg = <0x7000c500 0x100>;
6cecf916 442 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 443 #address-cells = <1>;
444 #size-cells = <0>;
885a8cfa
HD		 445 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
446 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 447 clock-names = "div-clk", "fast-clk";
3393d422
SW		 448 resets = <&tegra_car 67>;
449 reset-names = "i2c";
034d023f
SW		 450 dmas = <&apbdma 23>, <&apbdma 23>;
451 dma-names = "rx", "tx";
223ef78d 452 status = "disabled";
8e267f3d
GL		 453 };
454
c04abb3a 455 i2c@7000d000 {
c04abb3a
SW		 456 compatible = "nvidia,tegra20-i2c-dvc";
457 reg = <0x7000d000 0x200>;
6cecf916 458 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 459 #address-cells = <1>;
460 #size-cells = <0>;
885a8cfa
HD		 461 clocks = <&tegra_car TEGRA20_CLK_DVC>,
462 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 463 clock-names = "div-clk", "fast-clk";
3393d422
SW		 464 resets = <&tegra_car 47>;
465 reset-names = "i2c";
034d023f
SW		 466 dmas = <&apbdma 24>, <&apbdma 24>;
467 dma-names = "rx", "tx";
223ef78d 468 status = "disabled";
8e267f3d
GL		 469 };
470
a86b0db3
LD		 471 spi@7000d400 {
472 compatible = "nvidia,tegra20-slink";
473 reg = <0x7000d400 0x200>;
6cecf916 474 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 475 #address-cells = <1>;
476 #size-cells = <0>;
885a8cfa 477 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
3393d422
SW		 478 resets = <&tegra_car 41>;
479 reset-names = "spi";
034d023f
SW		 480 dmas = <&apbdma 15>, <&apbdma 15>;
481 dma-names = "rx", "tx";
a86b0db3
LD		 482 status = "disabled";
483 };
484
485 spi@7000d600 {
486 compatible = "nvidia,tegra20-slink";
487 reg = <0x7000d600 0x200>;
6cecf916 488 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 489 #address-cells = <1>;
490 #size-cells = <0>;
885a8cfa 491 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
3393d422
SW		 492 resets = <&tegra_car 44>;
493 reset-names = "spi";
034d023f
SW		 494 dmas = <&apbdma 16>, <&apbdma 16>;
495 dma-names = "rx", "tx";
a86b0db3
LD		 496 status = "disabled";
497 };
498
499 spi@7000d800 {
500 compatible = "nvidia,tegra20-slink";
57471c8d 501 reg = <0x7000d800 0x200>;
6cecf916 502 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 503 #address-cells = <1>;
504 #size-cells = <0>;
885a8cfa 505 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
3393d422
SW		 506 resets = <&tegra_car 46>;
507 reset-names = "spi";
034d023f
SW		 508 dmas = <&apbdma 17>, <&apbdma 17>;
509 dma-names = "rx", "tx";
a86b0db3
LD		 510 status = "disabled";
511 };
512
513 spi@7000da00 {
514 compatible = "nvidia,tegra20-slink";
515 reg = <0x7000da00 0x200>;
6cecf916 516 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 517 #address-cells = <1>;
518 #size-cells = <0>;
885a8cfa 519 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
3393d422
SW		 520 resets = <&tegra_car 68>;
521 reset-names = "spi";
034d023f
SW		 522 dmas = <&apbdma 18>, <&apbdma 18>;
523 dma-names = "rx", "tx";
a86b0db3
LD		 524 status = "disabled";
525 };
526
58ecb23f 527 kbc@7000e200 {
699ed4b9
LD		 528 compatible = "nvidia,tegra20-kbc";
529 reg = <0x7000e200 0x100>;
6cecf916 530 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 531 clocks = <&tegra_car TEGRA20_CLK_KBC>;
3393d422
SW		 532 resets = <&tegra_car 36>;
533 reset-names = "kbc";
699ed4b9
LD		 534 status = "disabled";
535 };
536
58ecb23f 537 pmc@7000e400 {
c04abb3a
SW		 538 compatible = "nvidia,tegra20-pmc";
539 reg = <0x7000e400 0x400>;
885a8cfa 540 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
7021d122 541 clock-names = "pclk", "clk32k_in";
c04abb3a
SW		 542 };
543
bbfc33bd 544 memory-controller@7000f000 {
c04abb3a
SW		 545 compatible = "nvidia,tegra20-mc";
546 reg = <0x7000f000 0x024
547 0x7000f03c 0x3c4>;
6cecf916 548 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a
SW		 549 };
550
58ecb23f 551 iommu@7000f024 {
c04abb3a
SW		 552 compatible = "nvidia,tegra20-gart";
553 reg = <0x7000f024 0x00000018 /* controller registers */
554 0x58000000 0x02000000>; /* GART aperture */
555 };
556
bbfc33bd 557 memory-controller@7000f400 {
c04abb3a
SW		 558 compatible = "nvidia,tegra20-emc";
559 reg = <0x7000f400 0x200>;
2eaab06e
SW		 560 #address-cells = <1>;
561 #size-cells = <0>;
8e267f3d 562 };
c27317c0 563
155dfc7b
PDS		 564 fuse@7000f800 {
565 compatible = "nvidia,tegra20-efuse";
5431b0fd 566 reg = <0x7000f800 0x400>;
155dfc7b
PDS		 567 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
568 clock-names = "fuse";
569 resets = <&tegra_car 39>;
570 reset-names = "fuse";
571 };
572
58ecb23f 573 pcie-controller@80003000 {
1b62b611
TR		 574 compatible = "nvidia,tegra20-pcie";
575 device_type = "pci";
576 reg = <0x80003000 0x00000800 /* PADS registers */
577 0x80003800 0x00000200 /* AFI registers */
578 0x90000000 0x10000000>; /* configuration space */
579 reg-names = "pads", "afi", "cs";
580 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
581 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
582 interrupt-names = "intr", "msi";
583
97070bd4
LS		 584 #interrupt-cells = <1>;
585 interrupt-map-mask = <0 0 0 0>;
586 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
587
1b62b611
TR		 588 bus-range = <0x00 0xff>;
589 #address-cells = <3>;
590 #size-cells = <2>;
591
592 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
593 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
594 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
d7283c11
JA		 595 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
596 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
1b62b611
TR		 597
598 clocks = <&tegra_car TEGRA20_CLK_PEX>,
599 <&tegra_car TEGRA20_CLK_AFI>,
1b62b611 600 <&tegra_car TEGRA20_CLK_PLL_E>;
2bd541ff 601 clock-names = "pex", "afi", "pll_e";
3393d422
SW		 602 resets = <&tegra_car 70>,
603 <&tegra_car 72>,
604 <&tegra_car 74>;
605 reset-names = "pex", "afi", "pcie_x";
1b62b611
TR		 606 status = "disabled";
607
608 pci@1,0 {
609 device_type = "pci";
610 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
611 reg = <0x000800 0 0 0 0>;
612 status = "disabled";
613
614 #address-cells = <3>;
615 #size-cells = <2>;
616 ranges;
617
618 nvidia,num-lanes = <2>;
619 };
620
621 pci@2,0 {
622 device_type = "pci";
623 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
624 reg = <0x001000 0 0 0 0>;
625 status = "disabled";
626
627 #address-cells = <3>;
628 #size-cells = <2>;
629 ranges;
630
631 nvidia,num-lanes = <2>;
632 };
633 };
634
c27317c0
OJ		 635 usb@c5000000 {
636 compatible = "nvidia,tegra20-ehci", "usb-ehci";
637 reg = <0xc5000000 0x4000>;
6cecf916 638 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 639 phy_type = "utmi";
ba202f15 640 nvidia,has-legacy-mode;
885a8cfa 641 clocks = <&tegra_car TEGRA20_CLK_USBD>;
3393d422
SW		 642 resets = <&tegra_car 22>;
643 reset-names = "usb";
b4e07478 644 nvidia,needs-double-reset;
e374b65c 645 nvidia,phy = <&phy1>;
223ef78d 646 status = "disabled";
c27317c0
OJ		 647 };
648
4c94c8b5 649 phy1: usb-phy@c5000000 {
5d324410 650 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 651 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
5d324410 652 phy_type = "utmi";
885a8cfa
HD		 653 clocks = <&tegra_car TEGRA20_CLK_USBD>,
654 <&tegra_car TEGRA20_CLK_PLL_U>,
655 <&tegra_car TEGRA20_CLK_CLK_M>,
656 <&tegra_car TEGRA20_CLK_USBD>;
4c94c8b5 657 clock-names = "reg", "pll_u", "timer", "utmi-pads";
308efde2
TT		 658 resets = <&tegra_car 22>, <&tegra_car 22>;
659 reset-names = "usb", "utmi-pads";
5d324410 660 nvidia,has-legacy-mode;
c49667e5
MP		 661 nvidia,hssync-start-delay = <9>;
662 nvidia,idle-wait-delay = <17>;
663 nvidia,elastic-limit = <16>;
664 nvidia,term-range-adj = <6>;
665 nvidia,xcvr-setup = <9>;
666 nvidia,xcvr-lsfslew = <1>;
667 nvidia,xcvr-lsrslew = <1>;
308efde2 668 nvidia,has-utmi-pad-registers;
4c94c8b5 669 status = "disabled";
5d324410
SW		 670 };
671
c27317c0
OJ		 672 usb@c5004000 {
673 compatible = "nvidia,tegra20-ehci", "usb-ehci";
674 reg = <0xc5004000 0x4000>;
6cecf916 675 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 676 phy_type = "ulpi";
885a8cfa 677 clocks = <&tegra_car TEGRA20_CLK_USB2>;
3393d422
SW		 678 resets = <&tegra_car 58>;
679 reset-names = "usb";
e374b65c 680 nvidia,phy = <&phy2>;
223ef78d 681 status = "disabled";
c27317c0
OJ		 682 };
683
4c94c8b5 684 phy2: usb-phy@c5004000 {
5d324410 685 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 686 reg = <0xc5004000 0x4000>;
5d324410 687 phy_type = "ulpi";
885a8cfa
HD		 688 clocks = <&tegra_car TEGRA20_CLK_USB2>,
689 <&tegra_car TEGRA20_CLK_PLL_U>,
690 <&tegra_car TEGRA20_CLK_CDEV2>;
4c94c8b5 691 clock-names = "reg", "pll_u", "ulpi-link";
308efde2
TT		 692 resets = <&tegra_car 58>, <&tegra_car 22>;
693 reset-names = "usb", "utmi-pads";
4c94c8b5 694 status = "disabled";
5d324410
SW		 695 };
696
c27317c0
OJ		 697 usb@c5008000 {
698 compatible = "nvidia,tegra20-ehci", "usb-ehci";
699 reg = <0xc5008000 0x4000>;
6cecf916 700 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 701 phy_type = "utmi";
885a8cfa 702 clocks = <&tegra_car TEGRA20_CLK_USB3>;
3393d422
SW		 703 resets = <&tegra_car 59>;
704 reset-names = "usb";
e374b65c 705 nvidia,phy = <&phy3>;
223ef78d 706 status = "disabled";
c27317c0 707 };
7868a9bc 708
4c94c8b5 709 phy3: usb-phy@c5008000 {
5d324410 710 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 711 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
5d324410 712 phy_type = "utmi";
885a8cfa
HD		 713 clocks = <&tegra_car TEGRA20_CLK_USB3>,
714 <&tegra_car TEGRA20_CLK_PLL_U>,
715 <&tegra_car TEGRA20_CLK_CLK_M>,
716 <&tegra_car TEGRA20_CLK_USBD>;
4c94c8b5 717 clock-names = "reg", "pll_u", "timer", "utmi-pads";
308efde2
TT		 718 resets = <&tegra_car 59>, <&tegra_car 22>;
719 reset-names = "usb", "utmi-pads";
c49667e5
MP		 720 nvidia,hssync-start-delay = <9>;
721 nvidia,idle-wait-delay = <17>;
722 nvidia,elastic-limit = <16>;
723 nvidia,term-range-adj = <6>;
724 nvidia,xcvr-setup = <9>;
725 nvidia,xcvr-lsfslew = <2>;
726 nvidia,xcvr-lsrslew = <2>;
4c94c8b5 727 status = "disabled";
5d324410
SW		 728 };
729
c04abb3a
SW		 730 sdhci@c8000000 {
731 compatible = "nvidia,tegra20-sdhci";
732 reg = <0xc8000000 0x200>;
6cecf916 733 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 734 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
3393d422
SW		 735 resets = <&tegra_car 14>;
736 reset-names = "sdhci";
223ef78d 737 status = "disabled";
7868a9bc 738 };
4a82f2b3 739
c04abb3a
SW		 740 sdhci@c8000200 {
741 compatible = "nvidia,tegra20-sdhci";
742 reg = <0xc8000200 0x200>;
6cecf916 743 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 744 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
3393d422
SW		 745 resets = <&tegra_car 9>;
746 reset-names = "sdhci";
223ef78d 747 status = "disabled";
4a82f2b3 748 };
6a943e0e 749
c04abb3a
SW		 750 sdhci@c8000400 {
751 compatible = "nvidia,tegra20-sdhci";
752 reg = <0xc8000400 0x200>;
6cecf916 753 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 754 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
3393d422
SW		 755 resets = <&tegra_car 69>;
756 reset-names = "sdhci";
223ef78d 757 status = "disabled";
c04abb3a
SW		 758 };
759
760 sdhci@c8000600 {
761 compatible = "nvidia,tegra20-sdhci";
762 reg = <0xc8000600 0x200>;
6cecf916 763 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 764 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
3393d422
SW		 765 resets = <&tegra_car 15>;
766 reset-names = "sdhci";
223ef78d 767 status = "disabled";
c04abb3a
SW		 768 };
769
4dd2bd37
HD		 770 cpus {
771 #address-cells = <1>;
772 #size-cells = <0>;
773
774 cpu@0 {
775 device_type = "cpu";
776 compatible = "arm,cortex-a9";
777 reg = <0>;
778 };
779
780 cpu@1 {
781 device_type = "cpu";
782 compatible = "arm,cortex-a9";
783 reg = <1>;
784 };
785 };
786
c04abb3a
SW		 787 pmu {
788 compatible = "arm,cortex-a9-pmu";
6cecf916
SW		 789 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6a943e0e 791 };
8e267f3d 792};
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