[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / tegra20.dtsi

/include/ "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra20";
	interrupt-parent = <&intc>;

	host1x {
		compatible = "nvidia,tegra20-host1x", "simple-bus";
		reg = <0x50000000 0x00024000>;
		interrupts = <0 65 0x04   /* mpcore syncpt */
			      0 67 0x04>; /* mpcore general */
		clocks = <&tegra_car 28>;

		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x54000000 0x54000000 0x04000000>;

		mpe {
			compatible = "nvidia,tegra20-mpe";
			reg = <0x54040000 0x00040000>;
			interrupts = <0 68 0x04>;
			clocks = <&tegra_car 60>;
		};

		vi {
			compatible = "nvidia,tegra20-vi";
			reg = <0x54080000 0x00040000>;
			interrupts = <0 69 0x04>;
			clocks = <&tegra_car 100>;
		};

		epp {
			compatible = "nvidia,tegra20-epp";
			reg = <0x540c0000 0x00040000>;
			interrupts = <0 70 0x04>;
			clocks = <&tegra_car 19>;
		};

		isp {
			compatible = "nvidia,tegra20-isp";
			reg = <0x54100000 0x00040000>;
			interrupts = <0 71 0x04>;
			clocks = <&tegra_car 23>;
		};

		gr2d {
			compatible = "nvidia,tegra20-gr2d";
			reg = <0x54140000 0x00040000>;
			interrupts = <0 72 0x04>;
			clocks = <&tegra_car 21>;
		};

		gr3d {
			compatible = "nvidia,tegra20-gr3d";
			reg = <0x54180000 0x00040000>;
			clocks = <&tegra_car 24>;
		};

		dc@54200000 {
			compatible = "nvidia,tegra20-dc";
			reg = <0x54200000 0x00040000>;
			interrupts = <0 73 0x04>;
			clocks = <&tegra_car 27>, <&tegra_car 121>;
			clock-names = "disp1", "parent";

			rgb {
				status = "disabled";
			};
		};

		dc@54240000 {
			compatible = "nvidia,tegra20-dc";
			reg = <0x54240000 0x00040000>;
			interrupts = <0 74 0x04>;
			clocks = <&tegra_car 26>, <&tegra_car 121>;
			clock-names = "disp2", "parent";

			rgb {
				status = "disabled";
			};
		};

		hdmi {
			compatible = "nvidia,tegra20-hdmi";
			reg = <0x54280000 0x00040000>;
			interrupts = <0 75 0x04>;
			clocks = <&tegra_car 51>, <&tegra_car 117>;
			clock-names = "hdmi", "parent";
			status = "disabled";
		};

		tvo {
			compatible = "nvidia,tegra20-tvo";
			reg = <0x542c0000 0x00040000>;
			interrupts = <0 76 0x04>;
			clocks = <&tegra_car 102>;
			status = "disabled";
		};

		dsi {
			compatible = "nvidia,tegra20-dsi";
			reg = <0x54300000 0x00040000>;
			clocks = <&tegra_car 48>;
			status = "disabled";
		};
	};

	timer@50004600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x50040600 0x20>;
		interrupts = <1 13 0x304>;
	};

	cache-controller@50043000 {
		compatible = "arm,pl310-cache";
		reg = <0x50043000 0x1000>;
		arm,data-latency = <5 5 2>;
		arm,tag-latency = <4 4 2>;
		cache-unified;
		cache-level = <2>;
	};

	intc: interrupt-controller {
		compatible = "arm,cortex-a9-gic";
		reg = <0x50041000 0x1000
		       0x50040100 0x0100>;
		interrupt-controller;
		#interrupt-cells = <3>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra20-timer";
		reg = <0x60005000 0x60>;
		interrupts = <0 0 0x04
			      0 1 0x04
			      0 41 0x04
			      0 42 0x04>;
	};

	tegra_car: clock {
		compatible = "nvidia,tegra20-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
	};

	apbdma: dma {
		compatible = "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1200>;
		interrupts = <0 104 0x04
			      0 105 0x04
			      0 106 0x04
			      0 107 0x04
			      0 108 0x04
			      0 109 0x04
			      0 110 0x04
			      0 111 0x04
			      0 112 0x04
			      0 113 0x04
			      0 114 0x04
			      0 115 0x04
			      0 116 0x04
			      0 117 0x04
			      0 118 0x04
			      0 119 0x04>;
		clocks = <&tegra_car 34>;
	};

	ahb {
		compatible = "nvidia,tegra20-ahb";
		reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
	};

	gpio: gpio {
		compatible = "nvidia,tegra20-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <0 32 0x04
			      0 33 0x04
			      0 34 0x04
			      0 35 0x04
			      0 55 0x04
			      0 87 0x04
			      0 89 0x04>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pinmux: pinmux {
		compatible = "nvidia,tegra20-pinmux";
		reg = <0x70000014 0x10   /* Tri-state registers */
		       0x70000080 0x20   /* Mux registers */
		       0x700000a0 0x14   /* Pull-up/down registers */
		       0x70000868 0xa8>; /* Pad control registers */
	};

	das {
		compatible = "nvidia,tegra20-das";
		reg = <0x70000c00 0x80>;
	};

	tegra_i2s1: i2s@70002800 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002800 0x200>;
		interrupts = <0 13 0x04>;
		nvidia,dma-request-selector = <&apbdma 2>;
		clocks = <&tegra_car 11>;
		status = "disabled";
	};

	tegra_i2s2: i2s@70002a00 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002a00 0x200>;
		interrupts = <0 3 0x04>;
		nvidia,dma-request-selector = <&apbdma 1>;
		clocks = <&tegra_car 18>;
		status = "disabled";
	};

	serial@70006000 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <0 36 0x04>;
		clocks = <&tegra_car 6>;
		status = "disabled";
	};

	serial@70006040 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <0 37 0x04>;
		clocks = <&tegra_car 96>;
		status = "disabled";
	};

	serial@70006200 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <0 46 0x04>;
		clocks = <&tegra_car 55>;
		status = "disabled";
	};

	serial@70006300 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <0 90 0x04>;
		clocks = <&tegra_car 65>;
		status = "disabled";
	};

	serial@70006400 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006400 0x100>;
		reg-shift = <2>;
		interrupts = <0 91 0x04>;
		clocks = <&tegra_car 66>;
		status = "disabled";
	};

	pwm: pwm {
		compatible = "nvidia,tegra20-pwm";
		reg = <0x7000a000 0x100>;
		#pwm-cells = <2>;
		clocks = <&tegra_car 17>;
	};

	rtc {
		compatible = "nvidia,tegra20-rtc";
		reg = <0x7000e000 0x100>;
		interrupts = <0 2 0x04>;
	};

	i2c@7000c000 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <0 38 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 12>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	spi@7000c380 {
		compatible = "nvidia,tegra20-sflash";
		reg = <0x7000c380 0x80>;
		interrupts = <0 39 0x04>;
		nvidia,dma-request-selector = <&apbdma 11>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 43>;
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <0 84 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 54>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <0 92 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 67>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra20-i2c-dvc";
		reg = <0x7000d000 0x200>;
		interrupts = <0 53 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 47>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	spi@7000d400 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d400 0x200>;
		interrupts = <0 59 0x04>;
		nvidia,dma-request-selector = <&apbdma 15>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 41>;
		status = "disabled";
	};

	spi@7000d600 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d600 0x200>;
		interrupts = <0 82 0x04>;
		nvidia,dma-request-selector = <&apbdma 16>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 44>;
		status = "disabled";
	};

	spi@7000d800 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d480 0x200>;
		interrupts = <0 83 0x04>;
		nvidia,dma-request-selector = <&apbdma 17>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 46>;
		status = "disabled";
	};

	spi@7000da00 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000da00 0x200>;
		interrupts = <0 93 0x04>;
		nvidia,dma-request-selector = <&apbdma 18>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 68>;
		status = "disabled";
	};

	pmc {
		compatible = "nvidia,tegra20-pmc";
		reg = <0x7000e400 0x400>;
	};

	memory-controller@7000f000 {
		compatible = "nvidia,tegra20-mc";
		reg = <0x7000f000 0x024
		       0x7000f03c 0x3c4>;
		interrupts = <0 77 0x04>;
	};

	gart {
		compatible = "nvidia,tegra20-gart";
		reg = <0x7000f024 0x00000018	/* controller registers */
		       0x58000000 0x02000000>;	/* GART aperture */
	};

	memory-controller@7000f400 {
		compatible = "nvidia,tegra20-emc";
		reg = <0x7000f400 0x200>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	phy1: usb-phy@c5000400 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5000400 0x3c00>;
		phy_type = "utmi";
		nvidia,has-legacy-mode;
		clocks = <&tegra_car 22>, <&tegra_car 127>;
		clock-names = "phy", "pll_u";
	};

	phy2: usb-phy@c5004400 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5004400 0x3c00>;
		phy_type = "ulpi";
		clocks = <&tegra_car 94>, <&tegra_car 127>;
		clock-names = "phy", "pll_u";
	};

	phy3: usb-phy@c5008400 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5008400 0x3C00>;
		phy_type = "utmi";
		clocks = <&tegra_car 22>, <&tegra_car 127>;
		clock-names = "phy", "pll_u";
	};

	usb@c5000000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5000000 0x4000>;
		interrupts = <0 20 0x04>;
		phy_type = "utmi";
		nvidia,has-legacy-mode;
		clocks = <&tegra_car 22>;
		nvidia,needs-double-reset;
		nvidia,phy = <&phy1>;
		status = "disabled";
	};

	usb@c5004000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5004000 0x4000>;
		interrupts = <0 21 0x04>;
		phy_type = "ulpi";
		clocks = <&tegra_car 58>;
		nvidia,phy = <&phy2>;
		status = "disabled";
	};

	usb@c5008000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5008000 0x4000>;
		interrupts = <0 97 0x04>;
		phy_type = "utmi";
		clocks = <&tegra_car 59>;
		nvidia,phy = <&phy3>;
		status = "disabled";
	};

	sdhci@c8000000 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000000 0x200>;
		interrupts = <0 14 0x04>;
		clocks = <&tegra_car 14>;
		status = "disabled";
	};

	sdhci@c8000200 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000200 0x200>;
		interrupts = <0 15 0x04>;
		clocks = <&tegra_car 9>;
		status = "disabled";
	};

	sdhci@c8000400 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000400 0x200>;
		interrupts = <0 19 0x04>;
		clocks = <&tegra_car 69>;
		status = "disabled";
	};

	sdhci@c8000600 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000600 0x200>;
		interrupts = <0 31 0x04>;
		clocks = <&tegra_car 15>;
		status = "disabled";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 56 0x04
			      0 57 0x04>;
	};
};
Commit	Line	Data
8e267f3d GL	1	/include/ "skeleton.dtsi"
	2
	3	/ {
	4	compatible = "nvidia,tegra20";
	5	interrupt-parent = <&intc>;
	6
ed821f07 TR	7	host1x {
	8	compatible = "nvidia,tegra20-host1x", "simple-bus";
	9	reg = <0x50000000 0x00024000>;
	10	interrupts = <0 65 0x04 /* mpcore syncpt */
	11	0 67 0x04>; /* mpcore general */
8d8b43da	12	clocks = <&tegra_car 28>;
ed821f07 TR	13
	14	#address-cells = <1>;
	15	#size-cells = <1>;
	16
	17	ranges = <0x54000000 0x54000000 0x04000000>;
	18
	19	mpe {
	20	compatible = "nvidia,tegra20-mpe";
	21	reg = <0x54040000 0x00040000>;
	22	interrupts = <0 68 0x04>;
8d8b43da	23	clocks = <&tegra_car 60>;
ed821f07 TR	24	};
	25
	26	vi {
	27	compatible = "nvidia,tegra20-vi";
	28	reg = <0x54080000 0x00040000>;
	29	interrupts = <0 69 0x04>;
8d8b43da	30	clocks = <&tegra_car 100>;
ed821f07 TR	31	};
	32
	33	epp {
	34	compatible = "nvidia,tegra20-epp";
	35	reg = <0x540c0000 0x00040000>;
	36	interrupts = <0 70 0x04>;
8d8b43da	37	clocks = <&tegra_car 19>;
ed821f07 TR	38	};
	39
	40	isp {
	41	compatible = "nvidia,tegra20-isp";
	42	reg = <0x54100000 0x00040000>;
	43	interrupts = <0 71 0x04>;
8d8b43da	44	clocks = <&tegra_car 23>;
ed821f07 TR	45	};
	46
	47	gr2d {
	48	compatible = "nvidia,tegra20-gr2d";
	49	reg = <0x54140000 0x00040000>;
	50	interrupts = <0 72 0x04>;
8d8b43da	51	clocks = <&tegra_car 21>;
ed821f07 TR	52	};
	53
	54	gr3d {
	55	compatible = "nvidia,tegra20-gr3d";
	56	reg = <0x54180000 0x00040000>;
8d8b43da	57	clocks = <&tegra_car 24>;
ed821f07 TR	58	};
	59
	60	dc@54200000 {
	61	compatible = "nvidia,tegra20-dc";
	62	reg = <0x54200000 0x00040000>;
	63	interrupts = <0 73 0x04>;
8d8b43da PG	64	clocks = <&tegra_car 27>, <&tegra_car 121>;
8d8b43da PG	65	clock-names = "disp1", "parent";
ed821f07 TR	66
	67	rgb {
	68	status = "disabled";
	69	};
	70	};
	71
	72	dc@54240000 {
	73	compatible = "nvidia,tegra20-dc";
	74	reg = <0x54240000 0x00040000>;
	75	interrupts = <0 74 0x04>;
8d8b43da PG	76	clocks = <&tegra_car 26>, <&tegra_car 121>;
8d8b43da PG	77	clock-names = "disp2", "parent";
ed821f07 TR	78
	79	rgb {
	80	status = "disabled";
	81	};
	82	};
	83
	84	hdmi {
	85	compatible = "nvidia,tegra20-hdmi";
	86	reg = <0x54280000 0x00040000>;
	87	interrupts = <0 75 0x04>;
8d8b43da PG	88	clocks = <&tegra_car 51>, <&tegra_car 117>;
8d8b43da PG	89	clock-names = "hdmi", "parent";
ed821f07 TR	90	status = "disabled";
	91	};
	92
	93	tvo {
	94	compatible = "nvidia,tegra20-tvo";
	95	reg = <0x542c0000 0x00040000>;
	96	interrupts = <0 76 0x04>;
8d8b43da	97	clocks = <&tegra_car 102>;
ed821f07 TR	98	status = "disabled";
	99	};
	100
	101	dsi {
	102	compatible = "nvidia,tegra20-dsi";
	103	reg = <0x54300000 0x00040000>;
8d8b43da	104	clocks = <&tegra_car 48>;
ed821f07 TR	105	status = "disabled";
	106	};
	107	};
	108
73368ba0 SW	109	timer@50004600 {
	110	compatible = "arm,cortex-a9-twd-timer";
	111	reg = <0x50040600 0x20>;
	112	interrupts = <1 13 0x304>;
	113	};
	114
5ab134ad JL	115	cache-controller@50043000 {
	116	compatible = "arm,pl310-cache";
	117	reg = <0x50043000 0x1000>;
	118	arm,data-latency = <5 5 2>;
	119	arm,tag-latency = <4 4 2>;
	120	cache-unified;
	121	cache-level = <2>;
	122	};
	123
f9eb26a4	124	intc: interrupt-controller {
0d4f7479	125	compatible = "arm,cortex-a9-gic";
5ff48887 SW	126	reg = <0x50041000 0x1000
5ff48887 SW	127	0x50040100 0x0100>;
2eaab06e SW	128	interrupt-controller;
2eaab06e SW	129	#interrupt-cells = <3>;
8e267f3d GL	130	};
8e267f3d GL	131
2f2b7fb2 SW	132	timer@60005000 {
	133	compatible = "nvidia,tegra20-timer";
	134	reg = <0x60005000 0x60>;
	135	interrupts = <0 0 0x04
	136	0 1 0x04
	137	0 41 0x04
	138	0 42 0x04>;
	139	};
	140
270f8ce3 SW	141	tegra_car: clock {
	142	compatible = "nvidia,tegra20-car";
	143	reg = <0x60006000 0x1000>;
	144	#clock-cells = <1>;
	145	};
	146
f9eb26a4	147	apbdma: dma {
8051b75a SW	148	compatible = "nvidia,tegra20-apbdma";
8051b75a SW	149	reg = <0x6000a000 0x1200>;
95decf84 SW	150	interrupts = <0 104 0x04
	151	0 105 0x04
	152	0 106 0x04
	153	0 107 0x04
	154	0 108 0x04
	155	0 109 0x04
	156	0 110 0x04
	157	0 111 0x04
	158	0 112 0x04
	159	0 113 0x04
	160	0 114 0x04
	161	0 115 0x04
	162	0 116 0x04
	163	0 117 0x04
	164	0 118 0x04
	165	0 119 0x04>;
8d8b43da	166	clocks = <&tegra_car 34>;
8051b75a SW	167	};
8051b75a SW	168
c04abb3a SW	169	ahb {
	170	compatible = "nvidia,tegra20-ahb";
	171	reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
8e267f3d GL	172	};
8e267f3d GL	173
f9eb26a4	174	gpio: gpio {
8e267f3d	175	compatible = "nvidia,tegra20-gpio";
95decf84 SW	176	reg = <0x6000d000 0x1000>;
	177	interrupts = <0 32 0x04
	178	0 33 0x04
	179	0 34 0x04
	180	0 35 0x04
	181	0 55 0x04
	182	0 87 0x04
	183	0 89 0x04>;
8e267f3d GL	184	#gpio-cells = <2>;
8e267f3d GL	185	gpio-controller;
6f74dc9b SW	186	#interrupt-cells = <2>;
6f74dc9b SW	187	interrupt-controller;
8e267f3d GL	188	};
8e267f3d GL	189
f9eb26a4	190	pinmux: pinmux {
f62f548c	191	compatible = "nvidia,tegra20-pinmux";
95decf84 SW	192	reg = <0x70000014 0x10 /* Tri-state registers */
	193	0x70000080 0x20 /* Mux registers */
	194	0x700000a0 0x14 /* Pull-up/down registers */
	195	0x70000868 0xa8>; /* Pad control registers */
f62f548c SW	196	};
f62f548c SW	197
c04abb3a SW	198	das {
	199	compatible = "nvidia,tegra20-das";
	200	reg = <0x70000c00 0x80>;
	201	};
	202
	203	tegra_i2s1: i2s@70002800 {
	204	compatible = "nvidia,tegra20-i2s";
	205	reg = <0x70002800 0x200>;
	206	interrupts = <0 13 0x04>;
	207	nvidia,dma-request-selector = <&apbdma 2>;
8d8b43da	208	clocks = <&tegra_car 11>;
223ef78d	209	status = "disabled";
c04abb3a SW	210	};
	211
	212	tegra_i2s2: i2s@70002a00 {
	213	compatible = "nvidia,tegra20-i2s";
	214	reg = <0x70002a00 0x200>;
	215	interrupts = <0 3 0x04>;
	216	nvidia,dma-request-selector = <&apbdma 1>;
8d8b43da	217	clocks = <&tegra_car 18>;
223ef78d	218	status = "disabled";
c04abb3a SW	219	};
c04abb3a SW	220
8e267f3d GL	221	serial@70006000 {
	222	compatible = "nvidia,tegra20-uart";
	223	reg = <0x70006000 0x40>;
	224	reg-shift = <2>;
95decf84	225	interrupts = <0 36 0x04>;
8d8b43da	226	clocks = <&tegra_car 6>;
223ef78d	227	status = "disabled";
8e267f3d GL	228	};
	229
	230	serial@70006040 {
	231	compatible = "nvidia,tegra20-uart";
	232	reg = <0x70006040 0x40>;
	233	reg-shift = <2>;
95decf84	234	interrupts = <0 37 0x04>;
8d8b43da	235	clocks = <&tegra_car 96>;
223ef78d	236	status = "disabled";
8e267f3d GL	237	};
	238
	239	serial@70006200 {
	240	compatible = "nvidia,tegra20-uart";
	241	reg = <0x70006200 0x100>;
	242	reg-shift = <2>;
95decf84	243	interrupts = <0 46 0x04>;
8d8b43da	244	clocks = <&tegra_car 55>;
223ef78d	245	status = "disabled";
8e267f3d GL	246	};
	247
	248	serial@70006300 {
	249	compatible = "nvidia,tegra20-uart";
	250	reg = <0x70006300 0x100>;
	251	reg-shift = <2>;
95decf84	252	interrupts = <0 90 0x04>;
8d8b43da	253	clocks = <&tegra_car 65>;
223ef78d	254	status = "disabled";
8e267f3d GL	255	};
	256
	257	serial@70006400 {
	258	compatible = "nvidia,tegra20-uart";
	259	reg = <0x70006400 0x100>;
	260	reg-shift = <2>;
95decf84	261	interrupts = <0 91 0x04>;
8d8b43da	262	clocks = <&tegra_car 66>;
223ef78d	263	status = "disabled";
8e267f3d GL	264	};
8e267f3d GL	265
2b8b15da	266	pwm: pwm {
140fd977 TR	267	compatible = "nvidia,tegra20-pwm";
	268	reg = <0x7000a000 0x100>;
	269	#pwm-cells = <2>;
8d8b43da	270	clocks = <&tegra_car 17>;
140fd977 TR	271	};
140fd977 TR	272
380e04ac SW	273	rtc {
	274	compatible = "nvidia,tegra20-rtc";
	275	reg = <0x7000e000 0x100>;
	276	interrupts = <0 2 0x04>;
	277	};
	278
c04abb3a	279	i2c@7000c000 {
c04abb3a SW	280	compatible = "nvidia,tegra20-i2c";
	281	reg = <0x7000c000 0x100>;
	282	interrupts = <0 38 0x04>;
2eaab06e SW	283	#address-cells = <1>;
2eaab06e SW	284	#size-cells = <0>;
8d8b43da PG	285	clocks = <&tegra_car 12>, <&tegra_car 124>;
8d8b43da PG	286	clock-names = "div-clk", "fast-clk";
223ef78d	287	status = "disabled";
0c6700ab OJ	288	};
0c6700ab OJ	289
fa98a114 LD	290	spi@7000c380 {
	291	compatible = "nvidia,tegra20-sflash";
	292	reg = <0x7000c380 0x80>;
	293	interrupts = <0 39 0x04>;
	294	nvidia,dma-request-selector = <&apbdma 11>;
	295	#address-cells = <1>;
	296	#size-cells = <0>;
8d8b43da	297	clocks = <&tegra_car 43>;
fa98a114 LD	298	status = "disabled";
	299	};
	300
c04abb3a	301	i2c@7000c400 {
c04abb3a SW	302	compatible = "nvidia,tegra20-i2c";
	303	reg = <0x7000c400 0x100>;
	304	interrupts = <0 84 0x04>;
2eaab06e SW	305	#address-cells = <1>;
2eaab06e SW	306	#size-cells = <0>;
8d8b43da PG	307	clocks = <&tegra_car 54>, <&tegra_car 124>;
8d8b43da PG	308	clock-names = "div-clk", "fast-clk";
223ef78d	309	status = "disabled";
8e267f3d GL	310	};
8e267f3d GL	311
c04abb3a	312	i2c@7000c500 {
c04abb3a SW	313	compatible = "nvidia,tegra20-i2c";
	314	reg = <0x7000c500 0x100>;
	315	interrupts = <0 92 0x04>;
2eaab06e SW	316	#address-cells = <1>;
2eaab06e SW	317	#size-cells = <0>;
8d8b43da PG	318	clocks = <&tegra_car 67>, <&tegra_car 124>;
8d8b43da PG	319	clock-names = "div-clk", "fast-clk";
223ef78d	320	status = "disabled";
8e267f3d GL	321	};
8e267f3d GL	322
c04abb3a	323	i2c@7000d000 {
c04abb3a SW	324	compatible = "nvidia,tegra20-i2c-dvc";
	325	reg = <0x7000d000 0x200>;
	326	interrupts = <0 53 0x04>;
2eaab06e SW	327	#address-cells = <1>;
2eaab06e SW	328	#size-cells = <0>;
8d8b43da PG	329	clocks = <&tegra_car 47>, <&tegra_car 124>;
8d8b43da PG	330	clock-names = "div-clk", "fast-clk";
223ef78d	331	status = "disabled";
8e267f3d GL	332	};
8e267f3d GL	333
a86b0db3 LD	334	spi@7000d400 {
	335	compatible = "nvidia,tegra20-slink";
	336	reg = <0x7000d400 0x200>;
	337	interrupts = <0 59 0x04>;
	338	nvidia,dma-request-selector = <&apbdma 15>;
	339	#address-cells = <1>;
	340	#size-cells = <0>;
8d8b43da	341	clocks = <&tegra_car 41>;
a86b0db3 LD	342	status = "disabled";
	343	};
	344
	345	spi@7000d600 {
	346	compatible = "nvidia,tegra20-slink";
	347	reg = <0x7000d600 0x200>;
	348	interrupts = <0 82 0x04>;
	349	nvidia,dma-request-selector = <&apbdma 16>;
	350	#address-cells = <1>;
	351	#size-cells = <0>;
8d8b43da	352	clocks = <&tegra_car 44>;
a86b0db3 LD	353	status = "disabled";
	354	};
	355
	356	spi@7000d800 {
	357	compatible = "nvidia,tegra20-slink";
	358	reg = <0x7000d480 0x200>;
	359	interrupts = <0 83 0x04>;
	360	nvidia,dma-request-selector = <&apbdma 17>;
	361	#address-cells = <1>;
	362	#size-cells = <0>;
8d8b43da	363	clocks = <&tegra_car 46>;
a86b0db3 LD	364	status = "disabled";
	365	};
	366
	367	spi@7000da00 {
	368	compatible = "nvidia,tegra20-slink";
	369	reg = <0x7000da00 0x200>;
	370	interrupts = <0 93 0x04>;
	371	nvidia,dma-request-selector = <&apbdma 18>;
	372	#address-cells = <1>;
	373	#size-cells = <0>;
8d8b43da	374	clocks = <&tegra_car 68>;
a86b0db3 LD	375	status = "disabled";
	376	};
	377
c04abb3a SW	378	pmc {
	379	compatible = "nvidia,tegra20-pmc";
	380	reg = <0x7000e400 0x400>;
	381	};
	382
bbfc33bd	383	memory-controller@7000f000 {
c04abb3a SW	384	compatible = "nvidia,tegra20-mc";
	385	reg = <0x7000f000 0x024
	386	0x7000f03c 0x3c4>;
	387	interrupts = <0 77 0x04>;
	388	};
	389
	390	gart {
	391	compatible = "nvidia,tegra20-gart";
	392	reg = <0x7000f024 0x00000018 /* controller registers */
	393	0x58000000 0x02000000>; /* GART aperture */
	394	};
	395
bbfc33bd	396	memory-controller@7000f400 {
c04abb3a SW	397	compatible = "nvidia,tegra20-emc";
c04abb3a SW	398	reg = <0x7000f400 0x200>;
2eaab06e SW	399	#address-cells = <1>;
2eaab06e SW	400	#size-cells = <0>;
8e267f3d	401	};
c27317c0	402
e374b65c VB	403	phy1: usb-phy@c5000400 {
	404	compatible = "nvidia,tegra20-usb-phy";
	405	reg = <0xc5000400 0x3c00>;
	406	phy_type = "utmi";
	407	nvidia,has-legacy-mode;
540fc9d9 SW	408	clocks = <&tegra_car 22>, <&tegra_car 127>;
540fc9d9 SW	409	clock-names = "phy", "pll_u";
e374b65c VB	410	};
	411
	412	phy2: usb-phy@c5004400 {
	413	compatible = "nvidia,tegra20-usb-phy";
	414	reg = <0xc5004400 0x3c00>;
	415	phy_type = "ulpi";
540fc9d9 SW	416	clocks = <&tegra_car 94>, <&tegra_car 127>;
540fc9d9 SW	417	clock-names = "phy", "pll_u";
e374b65c VB	418	};
	419
	420	phy3: usb-phy@c5008400 {
	421	compatible = "nvidia,tegra20-usb-phy";
	422	reg = <0xc5008400 0x3C00>;
	423	phy_type = "utmi";
540fc9d9 SW	424	clocks = <&tegra_car 22>, <&tegra_car 127>;
540fc9d9 SW	425	clock-names = "phy", "pll_u";
e374b65c VB	426	};
e374b65c VB	427
c27317c0 OJ	428	usb@c5000000 {
	429	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	430	reg = <0xc5000000 0x4000>;
95decf84	431	interrupts = <0 20 0x04>;
c27317c0	432	phy_type = "utmi";
ba202f15	433	nvidia,has-legacy-mode;
8d8b43da	434	clocks = <&tegra_car 22>;
b4e07478	435	nvidia,needs-double-reset;
e374b65c	436	nvidia,phy = <&phy1>;
223ef78d	437	status = "disabled";
c27317c0 OJ	438	};
	439
	440	usb@c5004000 {
	441	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	442	reg = <0xc5004000 0x4000>;
95decf84	443	interrupts = <0 21 0x04>;
c27317c0	444	phy_type = "ulpi";
8d8b43da	445	clocks = <&tegra_car 58>;
e374b65c	446	nvidia,phy = <&phy2>;
223ef78d	447	status = "disabled";
c27317c0 OJ	448	};
	449
	450	usb@c5008000 {
	451	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	452	reg = <0xc5008000 0x4000>;
95decf84	453	interrupts = <0 97 0x04>;
c27317c0	454	phy_type = "utmi";
8d8b43da	455	clocks = <&tegra_car 59>;
e374b65c	456	nvidia,phy = <&phy3>;
223ef78d	457	status = "disabled";
c27317c0	458	};
7868a9bc	459
c04abb3a SW	460	sdhci@c8000000 {
	461	compatible = "nvidia,tegra20-sdhci";
	462	reg = <0xc8000000 0x200>;
	463	interrupts = <0 14 0x04>;
8d8b43da	464	clocks = <&tegra_car 14>;
223ef78d	465	status = "disabled";
7868a9bc	466	};
4a82f2b3	467
c04abb3a SW	468	sdhci@c8000200 {
	469	compatible = "nvidia,tegra20-sdhci";
	470	reg = <0xc8000200 0x200>;
	471	interrupts = <0 15 0x04>;
8d8b43da	472	clocks = <&tegra_car 9>;
223ef78d	473	status = "disabled";
4a82f2b3	474	};
6a943e0e	475
c04abb3a SW	476	sdhci@c8000400 {
	477	compatible = "nvidia,tegra20-sdhci";
	478	reg = <0xc8000400 0x200>;
	479	interrupts = <0 19 0x04>;
8d8b43da	480	clocks = <&tegra_car 69>;
223ef78d	481	status = "disabled";
c04abb3a SW	482	};
	483
	484	sdhci@c8000600 {
	485	compatible = "nvidia,tegra20-sdhci";
	486	reg = <0xc8000600 0x200>;
	487	interrupts = <0 31 0x04>;
8d8b43da	488	clocks = <&tegra_car 15>;
223ef78d	489	status = "disabled";
c04abb3a SW	490	};
c04abb3a SW	491
4dd2bd37 HD	492	cpus {
	493	#address-cells = <1>;
	494	#size-cells = <0>;
	495
	496	cpu@0 {
	497	device_type = "cpu";
	498	compatible = "arm,cortex-a9";
	499	reg = <0>;
	500	};
	501
	502	cpu@1 {
	503	device_type = "cpu";
	504	compatible = "arm,cortex-a9";
	505	reg = <1>;
	506	};
	507	};
	508
c04abb3a SW	509	pmu {
	510	compatible = "arm,cortex-a9-pmu";
	511	interrupts = <0 56 0x04
	512	0 57 0x04>;
6a943e0e	513	};
8e267f3d	514	};